CN217085612U - Clock device and microcontroller - Google Patents
Clock device and microcontroller Download PDFInfo
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- CN217085612U CN217085612U CN202220344218.9U CN202220344218U CN217085612U CN 217085612 U CN217085612 U CN 217085612U CN 202220344218 U CN202220344218 U CN 202220344218U CN 217085612 U CN217085612 U CN 217085612U
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Abstract
The utility model provides a clock device and microcontroller, clock device includes: the charging and discharging control circuit comprises a current source, a threshold voltage source, a comparator, a first inverter, a first energy storage assembly, a second energy storage assembly and a charging and discharging control circuit; the charging and discharging control circuit comprises a first switch, a second switch, a third switch and a fourth switch; the first energy storage assembly is connected with the positive input end of the comparator through a first switch; the second energy storage assembly is connected with the negative input end of the comparator through a second switch; the positive input end of the current source, the positive input end of the comparator and the negative input end of the comparator are respectively connected with three ports of the third switch; the threshold voltage source, the positive input end of the comparator and the negative input end of the comparator are respectively connected with three ports of the fourth switch; the first phase inverter is connected with the output end of the comparator, the output end of the comparator outputs a second signal, and the first phase inverter outputs a first signal. The scheme has simple structure, does not need external elements and is flexible and convenient to apply.
Description
Technical Field
The utility model relates to an integrated circuit chip technical field especially relates to a clock device and microcontroller.
Background
With the rapid rise of the internet of things market, a large number of internet of things terminals gradually enter various fields of our lives. The last key module in the node of the internet of things is the MCU, the MCU is used as a core module for controlling the whole node of the internet of things, wireless communication, sensors and signal acquisition functions are integrated together, and the power consumption of the MCU is usually not negligible. The controller chips are driven by a high-precision clock to obtain different control time sequences based on a system clock, so that instructions sent to the microcontroller by a user can be correctly executed step by step, and accurate control of equipment is finished. In a microcontroller circuit, a clock oscillator module usually has multiple modes, and in order to be convenient for a user to use, more and more oscillators adopt an internal integration mode, so that the clock oscillator module is convenient for the user to use on the premise of exerting the performance to the maximum extent. In many complex digital architecture microcontrollers, the clock performance requirements are very stringent. For an internal integrated clock source, the power consumption of a chip is continuously reduced on the premise of ensuring the clock precision. There is currently no corresponding solution to meet this need.
SUMMERY OF THE UTILITY MODEL
In view of the above, the present invention provides a clock device and a microcontroller to overcome the deficiencies in the prior art.
The utility model provides a following technical scheme:
an embodiment of the utility model provides a clock device, include: the charging and discharging control circuit comprises a current source, a threshold voltage source, a comparator, a first inverter, a first energy storage assembly, a second energy storage assembly and a charging and discharging control circuit; the charging and discharging control circuit comprises a first switch, a second switch, a third switch and a fourth switch;
the first energy storage component is connected with the positive input end of the comparator through the first switch; the first switch is used for realizing the conduction of the first energy storage component and the positive input end of the comparator when receiving a first signal with high level;
the second energy storage assembly is connected with the negative input end of the comparator through the second switch; the second switch is used for realizing the conduction of the second energy storage component and the negative input end of the comparator when receiving a second signal with high level;
the current source, the positive input end of the comparator and the negative input end of the comparator are respectively connected with three ports of the third switch, the third switch realizes the conduction of the current source and the positive input end of the comparator when receiving a first signal with high level, and the third switch realizes the conduction of the current source and the negative input end of the comparator when receiving a second signal with high level;
the threshold voltage source, the positive input end of the comparator and the negative input end of the comparator are respectively connected with three ports of the fourth switch, the fourth switch realizes the conduction of the threshold voltage source and the negative input end of the comparator when receiving a first signal with high level, and the fourth switch realizes the conduction of the current source and the positive input end of the comparator when receiving a second signal with high level;
the first phase inverter is connected with the output end of the comparator, the output end of the comparator outputs the second signal, and the first phase inverter outputs the first signal.
In a specific embodiment, the method further comprises the following steps: a second inverter connected with the first inverter.
In a specific embodiment, the first inverter is the same as the second inverter.
In a specific embodiment, the first energy storage assembly comprises: a first capacitor; the first end of the first capacitor is connected with the first switch, and the second end of the first capacitor is grounded.
In a specific embodiment, the first energy storage assembly further comprises: a fifth switch; one end of the fifth switch is connected with the first end of the first capacitor, and the other end of the fifth switch is grounded; the fifth switch enables the first end of the first capacitor to be grounded when receiving the second signal with high level.
In a specific embodiment, the second energy storage assembly comprises: a second capacitor; and the first end of the second capacitor is connected with the second switch, and the second end of the second capacitor is grounded.
In a specific embodiment, the second energy storage assembly further comprises a sixth switch; one end of the sixth switch is connected with the first end of the second capacitor, and the other end of the sixth switch is grounded; the sixth switch enables the first end of the second capacitor to be grounded when receiving the first signal with high level.
In a specific embodiment, the threshold voltage source is a voltage source with adjustable voltage.
In a specific embodiment, the first switch and the second switch are both MOS transistors.
In a specific embodiment, the third switch is the same as the fourth switch.
The embodiment of the utility model provides a microcontroller is still provided, including foretell clock device.
The embodiment of the utility model has the following advantage:
the embodiment of the utility model provides a clock device and microcontroller, clock device includes: the charging and discharging control circuit comprises a current source, a threshold voltage source, a comparator, a first inverter, a first energy storage assembly, a second energy storage assembly and a charging and discharging control circuit; the charging and discharging control circuit comprises a first switch, a second switch, a third switch and a fourth switch; the first energy storage component is connected with the positive input end of the comparator through the first switch; the first switch is used for realizing the conduction of the first energy storage component and the positive input end of the comparator when receiving a first signal with high level; the second energy storage assembly is connected with the negative input end of the comparator through the second switch; the second switch is used for realizing the conduction of the second energy storage component and the negative input end of the comparator when receiving a second signal with high level; the current source, the positive input end of the comparator and the negative input end of the comparator are respectively connected with three ports of the third switch, the third switch realizes the conduction of the current source and the positive input end of the comparator when receiving a first signal with high level, and the third switch realizes the conduction of the current source and the negative input end of the comparator when receiving a second signal with high level; the threshold voltage source, the positive input end of the comparator and the negative input end of the comparator are respectively connected with three ports of the fourth switch, the fourth switch realizes the conduction of the threshold voltage source and the negative input end of the comparator when receiving a first signal with high level, and the fourth switch realizes the conduction of the current source and the positive input end of the comparator when receiving a second signal with high level; the first phase inverter is connected with the output end of the comparator, the output end of the comparator outputs the second signal, and the first phase inverter outputs the first signal. The scheme has simple structure, does not need external elements and is flexible and convenient to apply.
In order to make the aforementioned and other objects, features and advantages of the present invention more comprehensible and obvious, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 shows a schematic structural diagram of a clock device according to an embodiment of the present invention;
fig. 2 shows a schematic structural diagram of a clock device according to an embodiment of the present invention in a case of a process one;
fig. 3 is a schematic structural diagram of a clock device according to an embodiment of the present invention in a second case;
fig. 4 is a schematic diagram illustrating a waveform structure generated by a clock device according to an embodiment of the present invention.
Description of the main element symbols:
1-a current source; 2-a threshold voltage source; 3-a comparator; 4-a first inverter;
5-a first energy storage assembly; 51-a first capacitance; 52-a fifth switch;
6-a second energy storage assembly; 61-a second capacitance; 62-a sixth switch;
71-a first switch; 72-a second switch; 73-a third switch; 74-a fourth switch;
8-second inverter.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for purposes of illustration only.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present invention can be understood according to specific situations by those of ordinary skill in the art.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the templates herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Example 1
The charge and discharge control circuit comprises a first switch 71, a second switch 72, a third switch 73 and a fourth switch 74;
the first energy storage component 5 is connected to the positive input end of the comparator 3 through the first switch 71; the first switch 71 receives the first signal (phi in FIG. 1) of high level 1 ) The conduction between the first energy storage component 5 and the positive input end of the comparator 3 is realized;
the second energy storage assembly 6 is connected with the negative input end of the comparator 3 through the second switch 72; the second switch 72 receives the second signal (phi in FIG. 1) of high level 2 ) The second energy storage assembly 6 is conducted with the negative input end of the comparator 3;
the current source 1, the positive input terminal of the comparator 3, and the negative input terminal of the comparator 3 are respectively connected to three ports of the third switch 73, the third switch 73 realizes the conduction between the current source 1 and the positive input terminal of the comparator 3 when receiving a first signal with a high level, and the third switch 73 realizes the conduction between the current source 1 and the negative input terminal of the comparator 3 when receiving a second signal with a high level;
the threshold voltage source 2, the positive input terminal of the comparator 3, and the negative input terminal of the comparator 3 are respectively connected to three ports of the fourth switch 74, the fourth switch 74 realizes the conduction between the threshold voltage source 2 and the negative input terminal of the comparator 3 when receiving a first signal with a high level, and the fourth switch 74 realizes the conduction between the current source 1 and the positive input terminal of the comparator 3 when receiving a second signal with a high level;
the first inverter 4 is connected to an output terminal of the comparator 3, an output terminal of the comparator 3 outputs the second signal, and the first inverter 4 outputs the first signal.
Specifically, as shown in fig. 2, a schematic structural diagram of the first process is shown.
In process one, when phi 1 ＝1，φ 2 When the charging voltage on the first energy storage component 5 is higher than VREF, the output state of the comparator 3 is reversed, and at this time, phi is 1 ＝0，φ 2 ＝1。
Referring to FIG. 3, a second charge/discharge process is shown.
In the second process, when phi 1 ＝0，φ 2 When the charging voltage on the second energy storage assembly 6 is higher than VREF, the output state of the comparator 3 is inverted, and at the moment, phi is output 1 ＝1，φ 2 ＝0。
In this process, process one and process two alternate, thereby generating a continuous stable clock signal. FIG. 4 shows waveforms generated in the first and second processes.
In addition, the second signal in the scheme is output by the comparator 3, and in this case, the second signal is converted into the first signal based on the first inverter 4, so that an additional signal source is not needed, power consumption is reduced, and the structure is simplified.
Further, the method also comprises the following steps: a second inverter 8, the second inverter 8 being connected to the first inverter 4.
In a specific embodiment, the first inverter 4 is identical to the second inverter 8.
In a specific embodiment, the first energy storage assembly 5 comprises: a first capacitor 51; a first end of the first capacitor 51 is connected to the first switch 71, and a second end of the first capacitor 51 is grounded.
In a specific embodiment, in order to rapidly discharge the first capacitor 51, the first energy storage assembly 5 further includes: a fifth switch 52; one end of the fifth switch 52 is connected to the first end of the first capacitor 51, and the other end of the fifth switch 52 is grounded; the fifth switch 52 connects the first terminal of the first capacitor 51 to ground when receiving the second signal of high level.
Further, the second energy storage assembly 6 includes: a second capacitor 61; a first terminal of the second capacitor 61 is connected to the second switch 72, and a second terminal of the second capacitor 61 is grounded.
Similarly, in order to rapidly discharge the second capacitor 61, the second energy storage assembly 6 further includes a sixth switch 62; one end of the sixth switch 62 is connected to the first end of the second capacitor 61, and the other end of the sixth switch 62 is grounded; the sixth switch 62 connects the first terminal of the second capacitor 61 to ground when receiving the first signal of high level.
Specifically, the capacitor is a time-dependent energy storage element and is conveniently integrated into the chip. By controlling the continuous charging and discharging of the capacitor, the clock with corresponding frequency can be obtained.
In a specific embodiment, the threshold voltage source 2 is a voltage source with adjustable voltage to adapt to various scene requirements.
In a specific embodiment, to realize fast switching, the first switch 71 and the second switch 72 are both MOS transistors.
In a specific embodiment, the third switch 73 is identical to the fourth switch 74.
Example 2
The embodiment of the utility model provides a clock device and microcontroller, clock device includes: the device comprises a current source 1, a threshold voltage source 2, a comparator 3, a first inverter 4, a first energy storage component 5, a second energy storage component 6 and a charge and discharge control circuit; the charge and discharge control circuit comprises a first switch 71, a second switch 72, a third switch 73 and a fourth switch 74; the first energy storage component 5 is connected to the positive input end of the comparator 3 through the first switch 71; the first switch 71 realizes conduction between the first energy storage element 5 and the positive input terminal of the comparator 3 when receiving a first signal with a high level; the second energy storage assembly 6 is connected with the negative input end of the comparator 3 through the second switch 72; the second switch 72 realizes the conduction between the second energy storage component 6 and the negative input end of the comparator 3 when receiving a second signal with a high level; the current source 1, the positive input terminal of the comparator 3, and the negative input terminal of the comparator 3 are respectively connected to three ports of the third switch 73, the third switch 73 realizes the conduction between the current source 1 and the positive input terminal of the comparator 3 when receiving a first signal with a high level, and the third switch 73 realizes the conduction between the current source 1 and the negative input terminal of the comparator 3 when receiving a second signal with a high level; the threshold voltage source 2, the positive input terminal of the comparator 3, and the negative input terminal of the comparator 3 are respectively connected to three ports of the fourth switch 74, the fourth switch 74 realizes the conduction between the threshold voltage source 2 and the negative input terminal of the comparator 3 when receiving a first signal with a high level, and the fourth switch 74 realizes the conduction between the current source 1 and the positive input terminal of the comparator 3 when receiving a second signal with a high level; the first inverter 4 is connected to an output terminal of the comparator 3, an output terminal of the comparator 3 outputs the second signal, and the first inverter 4 outputs the first signal. The scheme has simple structure, does not need external elements and is flexible and convenient to apply.
In all examples shown and described herein, any particular value should be construed as exemplary only and not as a limitation, and thus other examples of example embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above-described embodiments are merely illustrative of several embodiments of the present invention, which are described in detail and specific, but not intended to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention.
Claims (10)
1. A clock apparatus, comprising: the charging and discharging control circuit comprises a current source, a threshold voltage source, a comparator, a first inverter, a first energy storage assembly, a second energy storage assembly and a charging and discharging control circuit; wherein the content of the first and second substances,
the charge and discharge control circuit comprises a first switch, a second switch, a third switch and a fourth switch;
the first energy storage component is connected with the positive input end of the comparator through the first switch; the first switch is used for realizing the conduction of the first energy storage component and the positive input end of the comparator when receiving a first signal with high level;
the second energy storage assembly is connected with the negative input end of the comparator through the second switch; the second switch is used for realizing the conduction of the second energy storage component and the negative input end of the comparator when receiving a second signal with high level;
the current source, the positive input end of the comparator and the negative input end of the comparator are respectively connected with three ports of the third switch, the third switch realizes the conduction of the current source and the positive input end of the comparator when receiving a first signal with high level, and the third switch realizes the conduction of the current source and the negative input end of the comparator when receiving a second signal with high level;
the threshold voltage source, the positive input end of the comparator and the negative input end of the comparator are respectively connected with three ports of the fourth switch, the fourth switch realizes the conduction of the threshold voltage source and the negative input end of the comparator when receiving a first signal with high level, and the fourth switch realizes the conduction of the current source and the positive input end of the comparator when receiving a second signal with high level;
the first phase inverter is connected with the output end of the comparator, the output end of the comparator outputs the second signal, and the first phase inverter outputs the first signal.
2. The apparatus of claim 1, further comprising: a second inverter connected with the first inverter.
3. The apparatus of claim 2, wherein the first inverter is the same as the second inverter.
4. The apparatus of claim 1, wherein the first energy storage component comprises: a first capacitor; the first end of the first capacitor is connected with the first switch, and the second end of the first capacitor is grounded.
5. The apparatus of claim 4, wherein the first energy storage component further comprises: a fifth switch; one end of the fifth switch is connected with the first end of the first capacitor, and the other end of the fifth switch is grounded; the fifth switch enables the first end of the first capacitor to be grounded when receiving the second signal with high level.
6. The apparatus of claim 1, wherein the second energy storage component comprises: a second capacitor; and the first end of the second capacitor is connected with the second switch, and the second end of the second capacitor is grounded.
7. The apparatus of claim 6, wherein the second energy storage component further comprises a sixth switch; one end of the sixth switch is connected with the first end of the second capacitor, and the other end of the sixth switch is grounded; the sixth switch enables the first end of the second capacitor to be grounded when receiving the first signal with high level.
8. The apparatus of claim 1, wherein the threshold voltage source is a voltage source with an adjustable voltage.
9. The apparatus of claim 1, wherein the first switch and the second switch are both MOS transistors.
10. A microcontroller characterized by comprising a clock device according to any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220344218.9U CN217085612U (en) | 2022-02-21 | 2022-02-21 | Clock device and microcontroller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220344218.9U CN217085612U (en) | 2022-02-21 | 2022-02-21 | Clock device and microcontroller |
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| Publication Number | Publication Date |
|---|---|
| CN217085612U true CN217085612U (en) | 2022-07-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202220344218.9U Active CN217085612U (en) | 2022-02-21 | 2022-02-21 | Clock device and microcontroller |
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| CN (1) | CN217085612U (en) |
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- 2022-02-21 CN CN202220344218.9U patent/CN217085612U/en active Active
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