CN114629440A - Programmable oscillator circuit and power management chip - Google Patents
Programmable oscillator circuit and power management chip Download PDFInfo
- Publication number
- CN114629440A CN114629440A CN202210532734.9A CN202210532734A CN114629440A CN 114629440 A CN114629440 A CN 114629440A CN 202210532734 A CN202210532734 A CN 202210532734A CN 114629440 A CN114629440 A CN 114629440A
- Authority
- CN
- China
- Prior art keywords
- unit
- oscillation
- output
- comparator
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
- H03B5/1218—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the generator being of the balanced type
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from dc input or output
- H02M1/143—Arrangements for reducing ripples from dc input or output using compensating arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a programmable oscillator circuit and a power management chip, which comprise an operational amplifier clamping module, an oscillation frequency adjusting module and an oscillation generating module; the oscillation frequency adjusting module comprises an adjusting resistor, a current mirror unit and a charging/discharging unit, the oscillation generating module comprises a comparator unit, an oscillation mode selecting unit and an oscillation generating unit, the current mirror unit is used for mirroring the current output of the input branch circuit to the charging/discharging unit, and the adjusting resistor is used for controlling the current of the input branch circuit of the current mirror unit so as to control the charging speed of the charging/discharging unit; the oscillation mode selection unit is used for controlling the oscillation mode of the oscillation generation unit, the comparator unit samples the charge/discharge voltage of the charge/discharge unit, the oscillation frequency of the oscillation generation unit is controlled according to the comparison result of the charge/discharge voltage and the reference voltage, and the stable compensation of subharmonic oscillation in the control process of the switching converter of the power management chip is realized through the oscillation clock signal generated by the oscillator circuit.
Description
Technical Field
The invention relates to the technical field of power management, in particular to a programmable oscillator circuit and a power management chip comprising the same.
Background
The DC-DC switch converter has the advantages of small volume, high driving capability, high precision, flexible and adjustable output voltage and the like, and is a hot power management scheme. The DC-DC converter may be classified into a buck converter, a boost converter, and a buck-boost converter according to its output voltage range. In a buck converter, the duty cycle is adjusted to maintain the output voltage near the design value under the action of a feedback loop, and the loop is capable of self-adjusting for input voltage changes, output current changes, and the like. Pulse Width Modulation (PWM) is one of the control methods of a switching converter, and includes Voltage-mode (Voltage-mode) control and Current-mode (Current-mode) control. The peak current mode control is a typical current mode control mode and has the advantages of fast transient response, simple overcurrent protection scheme and the like. However, when the duty ratio of the current mode feedback loop is higher than 50%, sub-harmonic oscillation, inductance average current fluctuation and other phenomena can occur, and finally the problems of system runaway, weak power supply interference resistance and the like can be brought. In order to avoid the above phenomenon, slope compensation needs to be superimposed on the sampled inductor current, and a key module in the slope compensation technology is an oscillator circuit.
Disclosure of Invention
The invention mainly aims to provide a programmable oscillator circuit and a power management chip comprising the same so as to realize the stable compensation of subharmonic oscillation in the control process of a switch converter of the power management chip.
To achieve the above object, the present invention provides a programmable oscillator circuit, comprising: the operational amplifier comprises an operational amplifier clamping module for providing a stable level, an oscillation frequency adjusting module connected with the output end of the operational amplifier clamping module and an oscillation generating module connected with the oscillation frequency adjusting module;
the oscillation frequency adjusting module comprises an adjusting resistor, a current mirror unit and a charging/discharging unit, wherein the adjusting resistor is connected to an input branch of the current mirror unit, the output end of the current mirror unit is connected with the input end of the charging/discharging unit, and the control end of the charging/discharging unit is connected with the oscillation generating module;
the oscillation generation module comprises a comparator unit, an oscillation mode selection unit and an oscillation generation unit, wherein the input end of the comparator unit is connected with the input end of the charge/discharge unit, the output end of the comparator unit is connected with the oscillation generation unit through the oscillation mode selection unit, and the output feedback end of the oscillation generation unit is connected with the control end of the charge/discharge unit;
the current mirror unit is used for mirroring the current of the input branch circuit and outputting the current to the charging/discharging unit, and the adjusting resistor is used for controlling the current of the input branch circuit of the current mirror unit so as to control the charging speed of the charging/discharging unit;
the oscillation mode selection unit is used for controlling the oscillation mode of the oscillation generation unit, and the comparator unit samples the charge/discharge voltage of the charge/discharge unit and controls the oscillation frequency of the oscillation generation unit according to the comparison result with the reference voltage.
Optionally, the charge/discharge unit includes a first capacitor, a first NMOS transistor, a second capacitor, and a second NMOS transistor, where an anode of the first capacitor and/or an anode of the second capacitor are used as input terminals of the charge/discharge unit, and a gate of the first NMOS transistor and a gate of the second NMOS transistor are used as control terminals of the charge/discharge unit; the positive electrode of the first capacitor is connected with the output end of the current mirror unit and the drain electrode of the first NMOS tube, the negative electrode of the first capacitor is connected with the source electrode of the first NMOS tube and grounded, and the grid electrode of the first NMOS tube is connected with the first output feedback end of the oscillation generation unit; the positive electrode of the second capacitor is connected with the fixed current bias signal and the drain electrode of the second NMOS tube, the negative electrode of the second capacitor is connected with the source electrode of the second NMOS tube and grounded, and the grid electrode of the second NMOS tube is connected with the second output feedback end of the oscillation generating unit.
Optionally, the comparator unit includes a first comparator and a second comparator, a non-inverting input terminal of the first comparator and a non-inverting input terminal of the second comparator are used as input terminals of the comparator unit, and an output terminal of the first comparator and/or an output terminal of the second comparator are used as output terminals of the comparator unit; the non-inverting input end of the first comparator is connected with the positive electrode of the first capacitor, the inverting input end of the first comparator is connected with a reference voltage signal, the output end of the first comparator is connected with one input end of the oscillation mode selection unit, the non-inverting input end of the first comparator is connected with the positive electrode of the first capacitor, the inverting input end of the first comparator is connected with the reference voltage signal, and the output end of the second comparator is connected with one input end of the oscillation generation unit.
Optionally, the oscillation generating unit includes an RS latch, a first schmitt inverter, and a first inverter, an input R end and an input S end of the RS latch are used as input ends of the oscillation generating unit, and an output end of the first schmitt inverter and an output end of the first inverter are used as output ends of the oscillation generating unit; the input R end of the RS latch is connected with the output end of the oscillation mode selection unit, the input S end of the RS latch is connected with the output end of the second comparator, the output Q end of the RS latch is connected with the input end of the first Schmitt phase inverter, the output end of the first Schmitt phase inverter is connected with the grid electrode of the first NMOS tube and the input end of the first phase inverter, and the output end of the first phase inverter is connected with the grid electrode of the second NMOS tube.
Optionally, the oscillation mode of the oscillator circuit includes a self-oscillation mode and an external clock synchronous oscillation mode, the oscillator circuit further includes an external clock locking unit, the oscillation mode selection unit includes an or gate, one input end of the or gate is connected to the output end of the comparator unit, and the other input end of the or gate is connected to the output end of the external clock locking unit; the oscillator circuit is in a self-oscillation mode when the external clock locking unit outputs one of logic signals '0' or '1', and in an external clock-synchronized oscillation mode when the external clock locking unit outputs the other of logic signals '0' or '1'.
Optionally, the oscillator circuit further includes an external clock circuit and a third capacitor, and when the oscillation mode of the oscillator circuit is an external clock synchronous oscillation mode, the output terminal of the external clock circuit is coupled to the output terminal of the operational amplifier clamping module through the third capacitor.
Optionally, the external clock locking unit includes a second schmitt inverter, a second inverter, and a D flip-flop, an input end of the second schmitt inverter is connected to an output end of the operational amplifier clamping module, an output end of the second schmitt inverter is connected to an input end of the second inverter, an output end of the second inverter is connected to an input Clk end of the D flip-flop, an input D end of the D flip-flop is connected to a power supply, an input R end of the D flip-flop is connected to an output end of the oscillation generating unit, and an output Q end of the D flip-flop is connected to another input end of the or gate.
Optionally, the D flip-flop is triggered by a rising edge.
Optionally, the oscillation frequency of the external clock circuit is greater than the self-oscillation frequency of the oscillator circuit.
In order to solve the above problem, the present invention also provides a power management chip, which includes the programmable oscillator circuit as described in any one of the above.
By adopting the embodiment of the invention, the following beneficial effects are achieved:
through the implementation of the programmable oscillator circuit provided by the invention, the oscillation modes of the circuit are two, including a self-oscillation mode and an external clock synchronization oscillation mode, and the local oscillator circuit not only can realize programmable adjustment of the frequency of an output oscillation signal, but also has an external clock synchronization function. The resistance value of the adjusting resistor is adjusted by adopting an externally hung adjusting resistor, so that different input currents of the current mirror unit are realized, and the mirror image is mirrored to the output branch for charging the charging/discharging unit, so that the control of the charging speed is realized; the different charging speeds enable the duration of the comparison result between the charging/discharging voltage sampled by the comparator unit and the reference voltage to be different, so that the duration of the output high level or low level of the oscillation generating unit is controlled to be different, and finally the oscillation frequency of the oscillation generating unit is adjusted. The oscillation clock signal generated by the oscillator circuit is used for performing stable compensation on subharmonic oscillation in the control process of the switch converter of the power management chip.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Wherein:
fig. 1 is a block diagram of a programmable oscillator circuit according to an embodiment of the present invention;
fig. 2 is a specific circuit schematic diagram of a programmable oscillator circuit according to an embodiment of the present invention;
fig. 3 is a specific circuit schematic diagram of an external clock locking unit of a programmable oscillator circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
Please refer to fig. 1, which is a schematic structural diagram of a programmable oscillator circuit according to an embodiment of the present invention, the programmable oscillator circuit mainly includes three modules, namely, an operational amplifier clamping module 100 for providing a stable level, an oscillation frequency adjusting module 200 connected to an output end of the operational amplifier clamping module 100, and an oscillation generating module 300 connected to the oscillation frequency adjusting module 200. The programmable oscillator circuit of this embodiment is used for a power management chip, the operating voltage of each integrated circuit module in the chip is at a low voltage level, and the operational amplifier clamping module 100 of this embodiment clamps the level at about 2V as a reference level for oscillation starting of the oscillator and outputs the reference level to the oscillation frequency adjusting module 200.
Specifically, the oscillation frequency adjusting module 200 includes an adjusting resistor R1, a current mirror unit 210, and a charge/discharge unit 220, the oscillation generating module 300 includes a comparator unit 310, an oscillation mode selecting unit 320, and an oscillation generating unit 330, the adjusting resistor R1 is connected to an input branch of the current mirror unit 210, an output terminal of the current mirror unit 210 is connected to an input terminal of the charge/discharge unit 220, and a control terminal of the charge/discharge unit 220 is connected to the oscillation generating module 300; the input terminal of the comparator unit 310 is connected to the input terminal of the charge/discharge unit 220, the output terminal of the comparator unit 310 is connected to the oscillation generating unit 330 via the oscillation mode selecting unit 320, and the output feedback terminal of the oscillation generating unit 330 is connected to the control terminal of the charge/discharge unit 220.
The current mirror unit 210 is used for mirroring the current output of the input branch to the charging/discharging unit 220, and the adjusting resistor R1 is used for controlling the current magnitude of the input branch of the current mirror unit 210, so as to control the charging speed of the charging/discharging unit 220; the oscillation mode selection unit 320 serves to control the oscillation mode of the oscillation generation unit 330, and the comparator unit 310 samples the charge/discharge voltage of the charge/discharge unit 220 and controls the oscillation frequency of the oscillation generation unit 330 according to the comparison result with the reference voltage.
The oscillation adjusting unit of this embodiment adopts an adjusting resistor R1 which is hung from the outside, the resistance value of the adjusting resistor R1 is adjustable, the level of the input branch of the current mirror unit 210 is constant, different input currents of the current mirror unit 210 are realized by hanging adjusting resistors R1 with different resistance values, and the input currents are mirrored to the output branch for charging the charging/discharging unit 220, so as to realize the control of the charging speed; the different charging speeds cause the charging/discharging voltage sampled by the comparator unit 310 to have different durations from the comparison result of the reference voltage, so as to control the oscillation generating unit 330 to output a high level or a low level for different durations, and finally realize the adjustment of the oscillation frequency of the oscillation generating unit 330.
In this embodiment, the oscillation mode of the oscillation generating unit 330 has two oscillation modes, including a self-oscillation mode and an external clock synchronous oscillation mode, the oscillation mode selecting unit 320 selects the oscillation mode according to actual requirements, generally, the oscillation signal generated in the self-oscillation mode is used to provide the oscillation clock signal for the oscillator circuit of the power management chip, and the oscillation signal generated in the external clock synchronous oscillation mode is used to provide the oscillation clock signal for other modules of the power management chip. Therefore, the local oscillator circuit not only can realize programmable adjustment of the frequency of the output oscillation signal, but also has the function of external clock synchronization.
Specifically, referring to fig. 2, the charge/discharge unit 220 includes a first capacitor C1, a first NMOS transistor MN1, a second capacitor C2, and a second NMOS transistor MN2, wherein the positive electrode of the first capacitor C1 and/or the positive electrode of the second capacitor C2 are used as input terminals of the charge/discharge unit 220, and the gate of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2 are used as control terminals of the charge/discharge unit 220; the positive electrode of the first capacitor C1 is connected with the output end of the current mirror unit 210 and the drain electrode of the first NMOS transistor MN1, the negative electrode of the first capacitor C1 is connected with the source electrode of the first NMOS transistor MN1 and grounded, and the gate electrode of the first NMOS transistor MN1 is connected with the first output feedback end CLK of the oscillation generation unit 330; the positive electrode of the second capacitor C2 is connected to the fixed current bias signal and the drain of the second NMOS transistor MN2, the negative electrode of the second capacitor C2 is connected to the source of the second NMOS transistor MN2 and grounded, and the gate of the second NMOS transistor MN2 is connected to the second output feedback terminal CLK _ INV of the oscillation generating unit 330.
The level signals of the first output feedback terminal CLK and the second output feedback terminal CLK _ INV of the oscillation generating unit 330 are opposite, that is, when the first output feedback terminal CLK outputs a low level, the second output feedback terminal CLK _ INV outputs a high level; when the first output feedback terminal CLK outputs a high level, the second output feedback terminal CLK _ INV outputs a low level. Therefore, when the first output feedback terminal CLK outputs a low level and the second output feedback terminal CLK _ INV outputs a high level, the first NMOS transistor MN1 is turned off and the second NMOS transistor MN2 is turned on, and the current of the mirror input branch is initially charged to the first capacitor C1 by the output terminal of the current mirror unit 210; until the signals of the first output feedback end CLK and the second output feedback end CLK _ INV are inverted, after the first output feedback end CLK outputs a high level and the second output feedback end CLK _ INV outputs a low level, the first NMOS transistor MN1 is turned on and the second NMOS transistor MN2 is turned off, at this time, the second capacitor C2 is charged by the fixed current output by the fixed current bias signal, and the first capacitor C1 is communicated with the ground through the first NMOS transistor MN1 to form a discharge loop to discharge the ground. When the signals of the first output feedback terminal CLK and the second output feedback terminal CLK _ INV are inverted again, after the first output feedback terminal CLK outputs a low level and the second output feedback terminal CLK _ INV outputs a high level, the first NMOS transistor MN1 is turned off, the second NMOS transistor MN2 is turned on, the first capacitor C1 is recharged by the current output by the current mirror unit 210, and the second capacitor C2 is connected with the ground through the second NMOS transistor MN2 to form a discharge loop to discharge the ground; at this time, the next cycle is performed, so that the oscillation signal generated by the oscillation generating unit 330 is fed back to the charge/discharge unit 220 to control the charge/discharge process of the charge/discharge unit 220, and the frequency of the oscillation signal of the oscillation generating unit 330 is determined by the charging speed of the charge/discharge unit 220, and finally, the frequency of the cycle is adjusted by the resistance value of the adjusting resistor R1.
Specifically, the comparator unit 310 comprises a first comparator COMP1 and a second comparator COMP2, a non-inverting input terminal of the first comparator COMP1 and a non-inverting input terminal of the second comparator COMP2 being input terminals of the comparator unit 310, an output terminal of the first comparator COMP1 and/or an output terminal of the second comparator COMP2 being output terminals of the comparator unit 310; the non-inverting input end of the first comparator COMP1 is connected with the positive electrode of the first capacitor C1, the inverting input end of the first comparator COMP1 is connected with a reference voltage signal, an input end of the oscillation mode selection unit 320 at the output end of the first comparator COMP1 is connected, the non-inverting input end of the first comparator COMP1 is connected with the positive electrode of the first capacitor C1, the inverting input end of the first comparator COMP1 is connected with the reference voltage signal, and an input end of the oscillation generation unit 330 at the output end of the second comparator COMP 483 5 is connected.
In the present embodiment, the reference voltage signals of the first comparator COMP1 and the second comparator COMP2 are the same, that is, the comparison references of the first comparator COMP1 and the second comparator COMP2 are the same. The first comparator COMP1 compares the voltage value on the first capacitor C1 with a reference voltage signal, and the second comparator COMP2 compares the voltage value on the second capacitor C2 with the reference voltage signal, that is, how long the charging voltage on the first capacitor C1 or the second capacitor C2 reaches the reference voltage signal, so as to control the frequency of the clock oscillation signal generated by the oscillation generating unit 330.
Specifically, the oscillation generating unit 330 includes an RS Latch RS _ Latch1, a first schmitt inverter INV _ S1, and a first inverter INV1, an input R terminal and an input S terminal of the RS Latch RS _ Latch1 are input terminals of the oscillation generating unit 330, and an output terminal of the first schmitt inverter INV _ S1 and an output terminal of the first inverter INV1 are output terminals of the oscillation generating unit 330; an input R end of the RS Latch RS _ Latch1 is connected to an output end of the oscillation mode selecting unit 320, an input S end of the RS Latch RS _ Latch1 is connected to an output end of the second comparator COMP2, an output Q end of the RS Latch RS _ Latch1 is connected to an input end of the first schmitt inverter INV _ S1, an output end of the first schmitt inverter INV _ S1 is connected to a gate of the first NMOS transistor MN1 and an input end of the first inverter INV1, and an output end of the first inverter INV1 is connected to a gate of the second NMOS transistor MN 2.
In the initial state, when the first capacitor C1 is charged to the reference voltage, the first comparator COMP1 outputs a high level, and at this time, the R terminal of the RS Latch RS _ Latch1 is at a high level, the S terminal is at a low level, the Q terminal is at a "0" state, and a low level is output. Correspondingly, when the output end of the first schmitt inverter INV _ S1 outputs a high level, the output end of the first inverter INV1 outputs a low level, and the low level is applied to the gate of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2, respectively, the second capacitor C2 starts to charge, the first capacitor C1 starts to discharge, until the second capacitor C2 charges to the reference voltage, and the second comparator COMP2 outputs a high level, when the R end and the S end of the RS Latch RS _ Latch1 perform the first level conversion respectively to convert the R end into a low level and the S end into a high level, the Q end is set to "1" state, and outputs a high level. Accordingly, the output end of the first schmitt inverter INV _ S1 and the output end of the first inverter INV1 respectively output a low level and a high level to the gates of the first NMOS transistor MN1 and the second NMOS transistor MN2, and the first capacitor C1 charges and the second capacitor C2 discharges, so that the next cycle is performed. The oscillation generating unit 330 formed by the RS Latch RS _ Latch1, the first schmitt inverter INV _ S1, and the first inverter INV1 functions, so that the oscillation generating unit 330 forms a stable oscillation clock signal output.
Specifically, the oscillator circuit further includes an external clock locking unit 340, the oscillation mode selection unit 320 includes an OR gate OR1, one input terminal of the OR gate OR1 is connected to the output terminal of the comparator unit 310, and the other input terminal of the OR gate OR1 is connected to the output terminal CLK _ OUT of the external clock locking unit 340; the oscillator circuit is in a self-oscillation mode when the external clock locking unit 340 outputs one of logic signals "0" or "1", and in an external clock-synchronized oscillation mode when the external clock locking unit 340 outputs the other of logic signals "0" or "1"; the following logic is employed in this embodiment: the oscillator circuit is in a self-oscillation mode when the external clock locking unit 340 outputs a logic signal "0", and in an external clock synchronous oscillation mode when the external clock locking unit 340 outputs a logic signal "1".
The selection of the oscillation mode, which is determined according to the output signal of the external clock locking unit 340, is realized by the OR gate OR 1. The oscillator circuit can select various oscillation modes according to practical application scenes, and the application range of the power management chip is widened.
Further, referring to fig. 2 and fig. 3, the oscillator circuit further includes an external clock circuit and a third capacitor C1, when the oscillation mode of the oscillator circuit is an external clock synchronous oscillation mode, the output terminal of the external clock circuit is coupled to the output terminal of the operational amplifier clamping module 100 through the third capacitor C1; the external clock locking unit 340 includes a second schmitt inverter INV _ S2, a second inverter INV2, and a D flip-flop DFF1, an input end of the second schmitt inverter INV _ S2 is connected to an output end of the operational amplifier clamping module 100, an output end of the second schmitt inverter INV _ S2 is connected to an input end of the second inverter INV2, an output end of the second inverter INV2 is connected to an input Clk end of the D flip-flop DFF1, an input D end of the D flip-flop DFF1 is connected to a power supply, an input R end of the D flip-flop DFF1 is connected to an output end Clk of the oscillation generating unit 330, and an output Q end of the D flip-flop DFF1 is connected to another input end of the OR 1.
In this embodiment, the D flip-flop DFF1 is rising edge triggered and the oscillation frequency of the external clock circuit is greater than the self-oscillation frequency of the oscillator circuit. Through the external clock locking unit 340, not only the external clock synchronous oscillation mode can be locked, but also the oscillation signal generated by the local oscillator circuit can be changed along with the external clock frequency in the synchronous oscillation mode.
With reference to fig. 2 and 3, the overall principle of the oscillator circuit of this embodiment is described as follows: the RT Pin voltage is clamped to 2V by the operational amplifier, so that the user can control the current on the input branch of the current mirror unit 210 by hooking the adjusting resistor R1 externally, and mirror the input branch current through the current mirror to charge the first capacitor C1, i.e. the speed of charging the internal first capacitor C1 can be set by the adjusting resistor R1. When the first capacitor C1 is charged to 2V, the first comparator COMP1 outputs a logic signal "1" to the subsequent circuit, and outputs a logic "1" signal to the R terminal of the RS Latch RS _ Latch1 through the OR gate OR1, wherein the CLK _ OUT signal is "1" only in the case of the clock synchronization mode, and is always "0" in the self-oscillation mode, the RS Latch RS _ Latch1Q outputs a logic signal "0" at the terminal, and outputs a CLK signal through the first schmitt inverter INV _ S1, and the logic is "1", and outputs an inverted signal of the CLK signal through the first inverter INV1, and the CLK _ INV signal is logically "0". At this time, since the first NMOS transistor MN1 is turned on, the first capacitor C1 is discharged to GND, the second NMOS transistor MN2 is turned off, the second capacitor C2 starts to be charged by a fixed current, when the voltage drop on the second capacitor C2 reaches 2V, the second comparator COMP2 outputs a logic signal "1" to the RS Latch RS _ Latch1S, the RS Latch RS _ Latch1Q outputs a logic signal "1", and the CLK signal is output as logic "0" through the first schmitt inverter INV _ S1, and the CLK signal is output as logic "1" through the first inverter INV1, and the inverse signal of the CLK signal is output as logic "1". At this time, the first NMOS transistor MN1 is turned off, the first capacitor C1 starts to charge the current set by the adjusting resistor R1 at the RT terminal, and the second capacitor C2 is discharged to GND since the second NMOS transistor MN2 is turned on. The previous actions are repeated to obtain a CLK square wave signal to realize a self-oscillation function, the resistance value of the resistor mounted on the RT Pin Pin changes the charging speed of the first capacitor C1 by controlling the current, the charging time of the first capacitor C1 determines the low level time of the CLK signal, the charging time of the second capacitor C2 determines the high level time of the CLK signal, and the high level time of the CLK signal is controlled by the fixed current in the chip.
When the oscillator circuit is in an external clock synchronization mode, an external clock square wave signal is coupled into an RT Pin through a third capacitor C1, and the voltage of the RT Pin is superposed into the amplitude value of the square wave signal above the original 2V level clamped by the operational amplifier. The high level time of the external clock signal cannot be too long, and the potential on the RT pin is prevented from being adjusted back to 2V by the action of the operational amplifier after being superposed into the high level signal. The RT Pin signal passes through the second schmitt inverter INV _ S2 and the second inverter INV2INV2 to the Clk terminal of the D flip-flop DFF1, since the D flip-flop DFF1 is triggered by the rising edge, the terminal of the D flip-flop DFF1Q outputs the Clk _ OUT signal with logic "1", and outputs logic "1" to the terminal of the RS Latch RS _ Latch1R by the OR gate OR1, and the terminal of the RS Latch RS _ Latch1Q outputs the logic signal "0", and outputs the Clk signal with logic "1" and the Clk _ INV signal with logic "0" respectively by the actions of the first schmitt inverter INV _ S1INV _ S2 and the first inverter INV1INV 1. At this time, the first capacitor C1 is discharged to GND, the second capacitor C2 starts to be charged, the terminal of the D flip-flop DFF1R receives the CLK signal with logic "1", the terminal Q outputs a logic signal "0", and the OR gate OR1 outputs a logic "0", thereby releasing the RS Latch RS _ Latch 1. When the voltage drop across the second capacitor C2 reaches 2V, the CLK signal is "0" and the CLK _ INV signal is "1" as a result of the logic circuit. At this time, the first capacitor C1 begins to charge, and the second capacitor C2 is discharged to GND. However, before the first capacitor C1 is charged to 2V, the RT Pin receives the next rising edge of the external clock signal, because it has been previously defined that the external clock oscillation frequency is greater than the internal self-oscillation frequency, so that the CLK signal becomes logic "1" under the action of the external clock rising edge, so that the internal CLK oscillation frequency is synchronized with the external clock, and the external clock synchronous oscillation function is realized.
Further, the present application also provides a power management chip, which includes the programmable oscillator circuit provided in the above embodiment, and through which a self-oscillating clock signal with adjustable frequency or an oscillating clock signal capable of synchronizing an external clock signal can be generated.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A programmable oscillator circuit, the programmable oscillator circuit comprising: the operational amplifier comprises an operational amplifier clamping module, an oscillation frequency adjusting module and an oscillation generating module, wherein the operational amplifier clamping module is used for providing a stable level, the oscillation frequency adjusting module is connected with the output end of the operational amplifier clamping module, and the oscillation generating module is connected with the oscillation frequency adjusting module;
the oscillation frequency adjusting module comprises an adjusting resistor, a current mirror unit and a charging/discharging unit, wherein the adjusting resistor is connected to an input branch of the current mirror unit, the output end of the current mirror unit is connected with the input end of the charging/discharging unit, and the control end of the charging/discharging unit is connected with the oscillation generating module;
the oscillation generation module comprises a comparator unit, an oscillation mode selection unit and an oscillation generation unit, wherein the input end of the comparator unit is connected with the input end of the charge/discharge unit, the output end of the comparator unit is connected with the oscillation generation unit through the oscillation mode selection unit, and the output feedback end of the oscillation generation unit is connected with the control end of the charge/discharge unit;
the current mirror unit is used for mirroring the current of the input branch circuit and outputting the current to the charging/discharging unit, and the adjusting resistor is used for controlling the current of the input branch circuit of the current mirror unit so as to control the charging speed of the charging/discharging unit;
the oscillation mode selection unit is used for controlling the oscillation mode of the oscillation generation unit, and the comparator unit samples the charge/discharge voltage of the charge/discharge unit and controls the oscillation frequency of the oscillation generation unit according to the comparison result with the reference voltage.
2. The programmable oscillator circuit according to claim 1, wherein the charge/discharge unit comprises a first capacitor, a first NMOS transistor, a second capacitor and a second NMOS transistor, wherein an anode of the first capacitor and/or an anode of the second capacitor is/are used as the input terminal of the charge/discharge unit, and a gate of the first NMOS transistor and a gate of the second NMOS transistor are used as the control terminal of the charge/discharge unit; the positive electrode of the first capacitor is connected with the output end of the current mirror unit and the drain electrode of the first NMOS tube, the negative electrode of the first capacitor is connected with the source electrode of the first NMOS tube and grounded, and the grid electrode of the first NMOS tube is connected with the first output feedback end of the oscillation generation unit; the positive electrode of the second capacitor is connected with the fixed current bias signal and the drain electrode of the second NMOS tube, the negative electrode of the second capacitor is connected with the source electrode of the second NMOS tube and grounded, and the grid electrode of the second NMOS tube is connected with the second output feedback end of the oscillation generating unit.
3. The programmable oscillator circuit according to claim 2, wherein the comparator unit comprises a first comparator and a second comparator, a non-inverting input of the first comparator and a non-inverting input of the second comparator being input to the comparator unit, an output of the first comparator and/or an output of the second comparator being output to the comparator unit; the non-inverting input end of the first comparator is connected with the positive electrode of the first capacitor, the inverting input end of the first comparator is connected with a reference voltage signal, the output end of the first comparator is connected with one input end of the oscillation mode selection unit, the non-inverting input end of the first comparator is connected with the positive electrode of the first capacitor, the inverting input end of the first comparator is connected with the reference voltage signal, and the output end of the second comparator is connected with one input end of the oscillation generation unit.
4. The programmable oscillator circuit according to claim 3, wherein the oscillation generating unit includes an RS latch, a first schmitt inverter, and a first inverter, wherein an input R terminal and an input S terminal of the RS latch serve as input terminals of the oscillation generating unit, and an output terminal of the first schmitt inverter and an output terminal of the first inverter serve as output terminals of the oscillation generating unit; the input R end of the RS latch is connected with the output end of the oscillation mode selection unit, the input S end of the RS latch is connected with the output end of the second comparator, the output Q end of the RS latch is connected with the input end of the first Schmitt phase inverter, the output end of the first Schmitt phase inverter is connected with the grid electrode of the first NMOS tube and the input end of the first phase inverter, and the output end of the first phase inverter is connected with the grid electrode of the second NMOS tube.
5. The programmable oscillator circuit according to any of claims 1 to 4, wherein the oscillation mode of the oscillator circuit comprises a self-oscillation mode and an external clock-synchronous oscillation mode, the oscillator circuit further comprising an external clock-locking unit, the oscillation mode selection unit comprising an OR gate, one input of the OR gate being connected to the output of the comparator unit, the other input of the OR gate being connected to the output of the external clock-locking unit; the oscillator circuit is in a self-oscillation mode when the external clock locking unit outputs one of logic signals '0' or '1', and in an external clock-synchronized oscillation mode when the external clock locking unit outputs the other of logic signals '0' or '1'.
6. The programmable oscillator circuit of claim 5, further comprising an external clock circuit and a third capacitor, wherein an output of the external clock circuit is coupled to the output of the operational amplifier clamping module via the third capacitor when the oscillation mode of the oscillator circuit is an external clock synchronous oscillation mode.
7. The programmable oscillator circuit of claim 6, wherein the external clock locking unit comprises a second Schmitt inverter, a second inverter and a D flip-flop, an input terminal of the second Schmitt inverter is connected to the output terminal of the operational amplifier clamping module, an output terminal of the second Schmitt inverter is connected to an input terminal of the second inverter, an output terminal of the second inverter is connected to an input Clk terminal of the D flip-flop, an input D terminal of the D flip-flop is connected to a power supply, an input R terminal of the D flip-flop is connected to an output terminal of the oscillation generating unit, and an output Q terminal of the D flip-flop is connected to another input terminal of the OR gate.
8. The programmable oscillator circuit of claim 7, wherein the D flip-flop is a rising edge flip-flop.
9. The programmable oscillator circuit of claim 8, wherein the oscillation frequency of the external clock circuit is greater than a self-oscillation frequency of the oscillator circuit.
10. A power management chip, characterized in that it comprises a programmable oscillator circuit according to any of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210532734.9A CN114629440B (en) | 2022-05-17 | 2022-05-17 | Programmable oscillator circuit and power management chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210532734.9A CN114629440B (en) | 2022-05-17 | 2022-05-17 | Programmable oscillator circuit and power management chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114629440A true CN114629440A (en) | 2022-06-14 |
| CN114629440B CN114629440B (en) | 2022-09-13 |
Family
ID=81907202
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210532734.9A Active CN114629440B (en) | 2022-05-17 | 2022-05-17 | Programmable oscillator circuit and power management chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114629440B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114785131A (en) * | 2022-06-20 | 2022-07-22 | 深圳市泰德半导体有限公司 | Frequency control circuit and power management chip |
| CN115051686A (en) * | 2022-08-15 | 2022-09-13 | 苏州萨沙迈半导体有限公司 | Low-power consumption oscillator circuit and chip |
| CN115149905A (en) * | 2022-08-31 | 2022-10-04 | 苏州贝克微电子股份有限公司 | Oscillation circuit capable of reducing subharmonic |
| CN116248048A (en) * | 2023-05-10 | 2023-06-09 | 深圳市微源半导体股份有限公司 | Oscillator circuit, oscillator and switching power supply |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106374881A (en) * | 2016-10-21 | 2017-02-01 | 深圳市汇春科技股份有限公司 | Quick-starting low-power-consumption clock oscillator |
| CN107276587A (en) * | 2017-08-16 | 2017-10-20 | 电子科技大学 | A kind of pierce circuit with external sync function |
| US20200021258A1 (en) * | 2017-10-16 | 2020-01-16 | Fuji Electric Co., Ltd. | Oscillator circuit using comparator |
| CN113452353A (en) * | 2021-06-29 | 2021-09-28 | 深圳市长运通半导体技术有限公司 | Frequency-adjustable oscillator capable of providing external synchronous clock function |
-
2022
- 2022-05-17 CN CN202210532734.9A patent/CN114629440B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106374881A (en) * | 2016-10-21 | 2017-02-01 | 深圳市汇春科技股份有限公司 | Quick-starting low-power-consumption clock oscillator |
| CN107276587A (en) * | 2017-08-16 | 2017-10-20 | 电子科技大学 | A kind of pierce circuit with external sync function |
| US20200021258A1 (en) * | 2017-10-16 | 2020-01-16 | Fuji Electric Co., Ltd. | Oscillator circuit using comparator |
| CN113452353A (en) * | 2021-06-29 | 2021-09-28 | 深圳市长运通半导体技术有限公司 | Frequency-adjustable oscillator capable of providing external synchronous clock function |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114785131A (en) * | 2022-06-20 | 2022-07-22 | 深圳市泰德半导体有限公司 | Frequency control circuit and power management chip |
| CN115051686A (en) * | 2022-08-15 | 2022-09-13 | 苏州萨沙迈半导体有限公司 | Low-power consumption oscillator circuit and chip |
| CN115051686B (en) * | 2022-08-15 | 2022-12-16 | 苏州萨沙迈半导体有限公司 | Low-power consumption oscillator circuit and chip |
| CN115149905A (en) * | 2022-08-31 | 2022-10-04 | 苏州贝克微电子股份有限公司 | Oscillation circuit capable of reducing subharmonic |
| CN116248048A (en) * | 2023-05-10 | 2023-06-09 | 深圳市微源半导体股份有限公司 | Oscillator circuit, oscillator and switching power supply |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114629440B (en) | 2022-09-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114629440B (en) | Programmable oscillator circuit and power management chip | |
| US7106130B2 (en) | Variable frequency PWM controller circuit | |
| US7268448B2 (en) | Plural output switching regulator with phase comparison and delay means | |
| KR100718905B1 (en) | Control circuit and control method for dc-dc converter | |
| US11177738B1 (en) | Digital on-time generation for buck converter | |
| US11824443B2 (en) | Single-inductor multiple-output DC-DC buck converter | |
| TWI578679B (en) | A control circuit for switching converter | |
| CN103066823A (en) | Controller and control method of switch power source | |
| CN113659815B (en) | Control circuit for switching converter | |
| CN112104203B (en) | Switch current-limiting circuit and power chip | |
| KR100239601B1 (en) | Charge pump | |
| CN111884507B (en) | Control circuit for power converter and control method thereof | |
| CN206211846U (en) | DC buck voltage-stablizer and its pulse frequency modulated control circuit | |
| US20220247318A1 (en) | Synchronization of an electronic device | |
| US10128737B1 (en) | Constant on-time switching converter and clock synchronization circuit | |
| US11558042B2 (en) | Multi-phase signal control circuit and method | |
| CN111082657A (en) | Buck-boost converter and control method | |
| CN106533172B (en) | DC voltage-reducing voltage stabilizer and pulse frequency modulation control circuit and method thereof | |
| CN115549469A (en) | Switch converter and control circuit thereof | |
| CN108429464B (en) | Power supply system with stable loop | |
| Agarwal et al. | A 10-MHz Current-Mode Fixed-Frequency Hysteretic Controlled DC-DC Converter With Fast Transient Response | |
| CN107394998B (en) | Control circuit, control method and switching power supply | |
| CN115149905B (en) | Oscillation circuit for reducing subharmonic | |
| Liu et al. | A dynamic buck converter with ultra fast response and low voltage ripples designed for DVS systems | |
| CN114400895B (en) | Integrated circuit and power supply device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |