CN107394998B

CN107394998B - Control circuit, control method and switching power supply

Info

Publication number: CN107394998B
Application number: CN201710437719.5A
Authority: CN
Inventors: 陈君
Original assignee: Hangzhou Silergy Semiconductor Technology Ltd
Current assignee: Hangzhou Silergy Semiconductor Technology Ltd
Priority date: 2017-06-12
Filing date: 2017-06-12
Publication date: 2020-04-17
Anticipated expiration: 2037-06-12
Also published as: CN107394998A

Abstract

The invention provides a control circuit, a control method and a switching power supply, wherein the frequency of a conducting signal for controlling the conduction of a main switching tube is a preset frequency during the period that the off time required by the main switching tube is longer than the minimum off time, and is a frequency positively correlated with the off time required by the main switching tube when the off time required by the main switching tube is shorter than the minimum off time, so that the smooth switching between a fixed-frequency working mode and a variable-frequency fixed-off working mode can be realized, and a special mode judgment circuit is not required for providing a mode switching signal, so that the realization mode is simple, and the expansion of the duty ratio of the switching control signal of the main switching tube can be stably and continuously realized. In addition, the power supply is in a constant off time working mode in the frequency conversion process, so that the problem of subharmonic oscillation caused by insufficient subharmonic compensation due to frequency conversion is solved.

Description

Control circuit, control method and switching power supply

Technical Field

The invention relates to the technical field of power electronics, in particular to a control circuit, a control method and a switching power supply.

Background

In a wide range of applications of the switching power supply to the portable electronic device, the switching power supply is mainly composed of a power stage circuit and a control circuit. The control circuit controls the switching power supply to convert the input voltage into the corresponding output voltage by controlling the duty ratio of the driving signal of the main switching tube in the power stage circuit.

Based on the inherent delays of the logic and driver circuits in the switching power supply, and to prevent false triggering of the main switching tube, it is generally desirable to have a minimum off-time for the main switching tube of the switching power supply. Due to the existence of the minimum turn-off time, in the switching power supply controlled by the fixed frequency, the duty ratio of the driving signal of the main switching tube is limited, and the limitation is more obvious when the switching frequency of the main switching tube is higher. For example, in the case of a step-down switching power supply, when the output voltage is required to be relatively close to the input voltage, the duty ratio of the driving signal of the main switching tube needs to be as close to 1 as possible, however, in the conventional fixed frequency control method, due to the existence of the minimum off time, the maximum duty ratio of the driving signal of the main switch is limited and cannot be further expanded, so that the switching power supply is difficult to maintain the required output voltage.

Disclosure of Invention

In view of this, the present invention provides a control circuit, a control method and a switching power supply, so as to overcome the problem that the switching power supply is difficult to maintain a required output voltage due to the limitation of the minimum turn-off time of a main switching tube of the switching power supply, which causes the duty ratio of a switching signal of the main switching tube to be expanded and limited.

A control circuit for a switching power supply including a main switching tube having a minimum off-time, comprising:

a conducting signal generating circuit for generating a conducting signal for controlling the conducting time of the main switching tube, wherein,

when the required turn-off time of the main switch tube is greater than the minimum turn-off time, the frequency of the conducting signal is a preset frequency, and when the required turn-off time of the main switch tube is less than the minimum turn-off time, the frequency of the conducting signal and the required turn-off time of the main switch tube form a positively correlated frequency.

Preferably, the control circuit further comprises:

a turn-off signal generating circuit for generating a turn-off signal for controlling the turn-off time of the main switching tube,

the conducting signal generating circuit generates the conducting signal according to the turn-off signal so as to control the turn-off time of the main switching tube in each switching period of the minimum turn-off period to be a preset value, wherein the turn-off time is less than the turn-off time required by the main switching tube,

and the first logic circuit is used for generating a switch control signal for controlling the switch state of the main switching tube according to the conducting signal and the switching-off signal.

Preferably, the on signal generating circuit includes:

a clock oscillation circuit for generating a clock signal according to a non-signal of the on signal,

a second logic circuit that generates the on signal based on the on signal, the off signal, and a first timing signal,

a first timing circuit generating the first timing signal according to the on signal,

wherein, in each switching cycle, the time when the clock signal jumps to the active state is a first time, the time when the off signal jumps to the active state is a second time, when the later one of the first time and the second time comes, the on signal jumps to the inactive state, and when a first preset time elapses, the first timing signal jumps to the active state to control the on signal jump to the active state,

the clock signal transitions to an inactive state after the turn-on signal transitions to an inactive state.

Preferably, the clock oscillation circuit comprises a charging circuit, a charging capacitor, a comparison circuit and a reset circuit,

the charging circuit is used for providing a charging current to charge the capacitor,

the comparison circuit is used for comparing the voltage at the charging end of the charging capacitor with a preset voltage, when the voltage at the charging end rises to the preset voltage, the clock signal jumps to an effective state,

and the reset circuit starts to reset the voltage at the charging end when the conducting signal jumps to an invalid state so as to control the clock signal to jump to the invalid state.

Preferably, the on signal generating circuit further includes:

the second timing circuit is used for generating a second timing signal according to the clock signal, the second logic circuit also generates the conducting signal according to the second timing signal,

and after the clock signal jumps to be in the effective state, when a second preset time passes, the second timing signal jumps to be in the effective state so as to control the conduction signal to jump to be in the ineffective state.

Preferably, the second logic circuit includes:

a first RS trigger, a set end of the first RS trigger receives the turn-off signal, a reset end of the first RS trigger receives a non-signal which is opposite to the state of the turn-on signal,

an OR gate, the input end of which respectively receives the output signal of the first RS trigger and the second timing signal,

an AND gate having inputs receiving the clock signal and an output signal of the OR gate, respectively,

a second RS trigger, a set end of which receives the output signal of the AND gate, a reset end of which receives the first timing signal, and an output end of which outputs the non-signal for respectively controlling the clock oscillation circuit and the first timing circuit,

and the inverter receives the non-signal and outputs the conducting signal.

Preferably, the turn-off signal generating circuit generates the turn-off signal according to a magnitude relation between an error compensation signal and an inductor current sampling signal of the switching power supply,

the error compensation signal is an error compensation signal between an output voltage feedback signal and a reference signal of the switching power supply.

When the required turn-off time of main switch pipe is greater than minimum turn-off time, control the switching frequency of main switch pipe is for predetermineeing the frequency, when the required turn-off time of main switch pipe is greater than when minimum turn-off time, control the switching frequency of main switch pipe with the required turn-off time of main switch pipe becomes positive correlation's frequency.

Preferably, the off-time required for controlling the main switching tube to be less than the off-time in each switching cycle of the minimum off-period is a preset value.

A switching power supply comprising the control circuit of any one of the above.

As can be seen from the above, in the switching power supply controlled by the control circuit and the control method provided by the present invention, the frequency of the turn-on signal for controlling the turn-on of the main switching tube is the preset frequency during the period when the turn-off time required by the main switching tube is greater than the minimum turn-off time, and is the frequency positively correlated to the turn-off time required by the main switching tube during the period when the turn-off time required by the main switching tube is greater than the minimum turn-off time, so that the switching power supply can be smoothly switched between the fixed-frequency operating mode and the variable-frequency fixed-turn-off operating mode, and a special mode determining circuit is not required to provide the mode switching signal to indicate the switching. In addition, the power supply is in a constant off time working mode in the frequency conversion process, so that the problem of subharmonic oscillation caused by insufficient subharmonic compensation due to frequency conversion is solved.

Drawings

Fig. 1 is a schematic structural diagram of a switching power supply 100 according to an embodiment of the invention;

fig. 2 is a circuit diagram of an implementation of the turn-on signal generating circuit in fig. 1;

FIG. 3 is a circuit diagram of an embodiment of the clock oscillator circuit of FIG. 2;

fig. 4 is a waveform diagram illustrating operation of the switching power supply 100 at a first time;

FIG. 5 is a waveform illustrating operation of the power supply 100 at a second time;

fig. 6 is a waveform diagram illustrating the operation of the switching power supply 100 when the off signal does not jump all the time.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. It should be noted that "…" in this description of the preferred embodiment is only for technical attributes or features of the present invention.

Fig. 1 is a schematic structural diagram of a switching power supply 100 according to an embodiment of the invention. The switching power supply 100 is mainly composed of a power stage circuit 11 and a control circuit 12. The control circuit 12 controls the switching power supply 100 to convert the input voltage VIN into the output voltage VOUT required by the load by controlling the switching state of the main switching transistor M1 in the power stage circuit 11.

The topology of the power stage circuit 11 is not particularly limited in the present invention, and may be a buck type, a boost type, a buck-boost type, or the like. In this embodiment, the power stage circuit 11 may further include a synchronous rectifier M2 connected to the main switch M1 in addition to the main switch M1, a node of the main switch M1 connected to the synchronous rectifier M2 is connected to a first end of an inductor L, a second end of the inductor L is grounded through an output capacitor Co, and the second end of the inductor L serves as an output terminal of the output voltage VOUT. The switching state of the synchronous rectification switch tube M2 is opposite to the switching state of the main switch tube M1, which is also controlled by the control circuit 12. Based on the inherent delay of some circuits in the switching power supply 100 and to prevent false triggering of the main switch transistor, the main switch transistor M1 has a minimum off-time Toff _ min, which is the minimum off-time that the main switch transistor M1 can reach in each switching cycle during the control of the switching state of the main switch transistor M1 by the control circuit 12.

As shown in fig. 1, the control circuit 12 mainly includes an on signal generation circuit, an off signal generation circuit, and a first logic circuit. The ON signal generating circuit is used for generating an ON signal F _ ON for controlling the ON time of the main switch tube M1, the OFF signal generating circuit is used for generating an OFF signal F _ OFF for controlling the OFF time of the main switch tube M2, and the first logic circuit is used for generating a first switch signal D1 for controlling the switching state of the main switch tube M1 and generating a second switch signal D2 for controlling the switching state of the synchronous rectifier tube M2 according to the ON signal F _ ON and the OFF signal F _ OFF. The first logic circuit in this embodiment may include an RS flip-flop RS3, a set terminal of which receives the ON signal F _ ON, a reset terminal of which receives the OFF signal F _ OFF, and a signal output from the output terminal passes through a driving circuit composed of a buffer and an inverter to generate a first switching signal D1 and a second switching signal D2.

The frequency of the ON signal F _ ON is a preset frequency in a first state, and is a frequency positively correlated to the off time required by the main switch M1 in a second state, wherein the first state is a state in which the off time required by the main switch M1 is greater than the minimum off time Toff _ min, and the second state is a state in which the off time required by the main switch M1 is less than the minimum off time Toff _ min. It should be explained here that the off time required by the main switch transistor M1 refers to the off time required by the main switch transistor M1 when the switching frequency of the main switch transistor M1 is equal to the preset frequency and the switching power supply 100 converts the input voltage VIN into the output voltage VOUT required by the load.

When the switching frequency of the main switching tube M1 is fixed to the preset frequency, that is, when the switching power supply 100 operates in the fixed frequency mode, the smaller the off time of the main switching tube M1 is, the larger the on time is, the larger the duty ratio of the first switching signal D1 is. Therefore, in the fixed-frequency operation mode, the duty cycle of the first switching signal D1 can only be increased by continuously decreasing the off time of the main switching tube M1. Due to the limitation of the main switch tube M1 having the minimum off-time Toff _ min, the maximum duty cycle of the first switch signal D1 is limited by the minimum off-time Toff _ min in the fixed frequency operation mode.

However, in the present invention, the frequency of the ON signal F _ ON is made to be the preset frequency in the first state, so that the switching power supply 100 is in the constant frequency operation mode in the time period, and in the first state, the off time required by the main switch transistor M1 is greater than the minimum off time Toff _ min, so the control circuit 12 can adjust the duty ratio of the first switch signal D1 by adjusting the off time of the main switch transistor M1, so that the switching power supply 100 converts the input voltage VIN into the required output voltage VOUT. When the off time of the main switch transistor M1 is required to be less than the minimum off time Toff _ min, so that the switching power supply can convert the input voltage into the required output voltage VOUT, that is, in the second state, the ON signal F _ ON is at a frequency positively correlated to the off time required by the main switch transistor M1, that is, the smaller the off time required by the main switch transistor M1 is, the smaller the ON signal F _ ON is, and vice versa. Therefore, in the second state, the control circuit 12 adjusts the duty ratio of the first switching signal D1 by adjusting the frequency of the ON signal F _ ON, so that it can be further expanded without being limited by the minimum off time Toff _ min, thereby maintaining the output voltage VOUT of the switching power supply 100 at a desired value.

In the switching power supply 100 provided in this embodiment, the ON-signal generating circuit generates the ON-signal F _ ON according to the OFF-signal F _ OFF to control the OFF-time of the main switching tube M1 in each switching period in the second state to be a preset value. Therefore, the switching power supply 100 is in the variable frequency and constant off-time operation mode in the second state.

Fig. 2 is a circuit diagram of a specific implementation of the on signal generating circuit in fig. 1. The on signal generating circuit mainly includes: the clock oscillation circuit is used for generating a clock signal F _ OSC according to a non-signal F _ ONB of an ON signal F _ ON, a second logic circuit for generating the ON signal F _ ON according to the ON signal F _ ON, an OFF signal F _ OFF and a first timing signal F _ T1, and a first timing circuit for generating a first timing signal F _ T1 according to the ON signal F _ ON. In each switching cycle, a time when the clock signal F _ OSC transits to an active state is a first time, a time when the OFF signal F _ OFF transits to an active state is a second time, when a later time of the first time and the second time comes, the ON signal F _ ON transits to an inactive state, the clock signal F _ OSC also transits to an inactive state quickly after the ON signal F _ ON transits to the inactive state, and when a first preset time passes after the ON signal F _ ON transits to the inactive state, for example, when 100 to 200ns passes, the first timing signal F _ T1 transits to an active state to control the ON signal F _ ON to transit to the active state. In the present invention, the active state of each signal may be high or low, and in the present actual switching power supply 100, the active state of each signal is high.

Fig. 3 is a circuit diagram of an implementation of the clock oscillator circuit of fig. 2. The clock oscillation circuit comprises a charging circuit, a charging capacitor C, a comparison circuit and a reset circuit. As shown in fig. 3, the charging circuit includes a charging current source I for providing a charging current to charge the charging capacitor C, and the comparison circuit may specifically include a comparator CMP for comparing a voltage F-CAP at a charging end of the charging capacitor C with a predetermined voltage, where when the voltage F-CAP rises to the predetermined voltage, the clock signal F _ OSC transits to an active state. The reset circuit may specifically include a reset switch K, which may be controlled by a non-signal of the conducting signal F _ ON to conduct when the conducting signal F _ ON transitions to an inactive state, so as to discharge the charging capacitor C, to quickly reset the voltage F _ CAP to an initial voltage, and to transition the clock signal F _ OSC to an inactive state.

In the switching power supply 100, the shutdown signal generation circuit generates a shutdown signal F _ OFF according to a magnitude relationship between an error compensation signal and an inductor current sampling signal of the switching power supply, wherein the error compensation signal is an error compensation signal between an output voltage feedback signal of the switching power supply and a reference signal. Therefore, the OFF signal F _ OFF is usually a narrow pulse signal (the duration of the active state is very short) output by the PWM comparator, and in order to prevent the output of the PWM comparator outputting the OFF signal F _ OFF from having no transition, as shown in fig. 2, the ON signal generating circuit further includes a second timing circuit for generating a second timing signal F _ T2 according to the clock signal F _ OSC, and then the second logic circuit generates the ON signal F _ ON according to the second timing signal F _ T2. After the clock signal F _ OSC transitions to the active state and a second predetermined time elapses, the second timing signal F _ T2 transitions to the active state to control the conducting signal F _ ON to transition to the inactive state. The first timing signal F _ T1 and the second timing signal F _ T2 are both narrow pulse signals in the present embodiment.

With continued reference to fig. 2, the second logic circuit mainly includes a first RS flip-flop RS1, an or gate, an and gate, a second RS flip-flop RS2, and an inverter. The set end of the first RS trigger receives an OFF signal F _ OFF, and the reset end of the first RS trigger receives a non-signal F _ ONB opposite to the state of the ON signal F _ ON. Since the OFF signal F _ OFF is a narrow pulse signal, the duration of its active state is very short, and thus its active state is maintained for a while by the first RS flip-flop. The input ends of the OR gate respectively receive the output signal of the first RS flip-flop and the second timing signal F _ T2, the input ends of the AND gate respectively receive a clock signal F _ OSC and the output signal F _ LG2 of the OR gate, the set end of the second RS flip-flop receives the output signal F _ LG1 of the AND gate, the reset end receives the first timing signal F _ T1, and the output end outputs the non-signal F _ ONB which is respectively used for controlling the clock oscillation circuit and the first timing circuit,

the inverter receives the non-signal F _ ONB and outputs a conducting signal F _ ON.

Fig. 4 and 5 are waveform diagrams of the operation of the switching power supply 100 in the first time period and the second time period, respectively, and fig. 6 is a waveform diagram of the operation of the switching power supply 100 when the transition of the turn-off signal has not occurred. The control process of the switching power supply provided by the present invention will be specifically described below with reference to fig. 1 to 6.

As shown in fig. 4, in the first state, a first time when the clock signal F _ OSC transits to the active state is later than a second time when the OFF signal F _ OFF transits to the active state in each switching period, and therefore, in the second state, the second RS flip-flop is not immediately set, but the active state of the OFF signal F _ OFF is held by the first RS flip-flop to wait for the arrival of the first time, at which time, the output signal F _ Q of the first RS flip-flop transits to the active state. When the voltage F _ CAP reaches a preset voltage (shown by a dotted line), the clock signal F _ OSC transits to an active state, which indicates that the first time arrives, the output signal F _ LG1 of the and gate in fig. 2 transits to an active state to set the second RS flip-flop, so that the non-signal F _ ONB transits to an active state, and the conducting signal F _ ON transits to an inactive state, at this time, the first RS flip-flop is reset, and the output signal F _ Q1 transits to an inactive state, and at this time, the first timing circuit starts to time, after the first preset time is continued, the first timing signal F _ T1 transits to an active state to reset the second RS flip-flop, so that the non-signal F _ ONB transits to an inactive state, and the conducting signal F _ ON transits to an active state, so as to control the main switch tube M1 to conduct.

As shown in fig. 5, in the second state, in each switching cycle, a first time when the clock signal F _ OSC transits to the active state is earlier than a second time when the OFF signal F _ OFF transits to the active state, and therefore, at the first time, the second RS flip-flop is not set immediately to start the first timing circuit, but waits for the second time to arrive. During the period of waiting for the second time to arrive, the charging circuit in fig. 3 continues to charge the charging capacitor, so that the voltage F _ CAP is always greater than the preset voltage during this period, and the clock signal F _ OSC is always maintained in an active state during this period. When the second time arrives, the output signal F _ LG1 of the and gate in fig. 2 jumps to an active state to set the second RS flip-flop, so that the non-signal F _ ONB jumps to an active state, and the ON signal F _ ON jumps to an inactive state, at this time, the first RS flip-flop is reset, the output signal F _ Q1 jumps to an inactive state, and at this time, the first timing circuit starts to time, and after the first preset time is kept, the first timing signal F _ T1 jumps to an active state to reset the second RS flip-flop, so that the non-signal F _ ONB jumps to an inactive state, and the ON signal F _ ON jumps to an active state to control the main switch tube M1 to be turned ON at this time. It can be seen that in the second state, the smaller the off time required by the main switch M1, the longer the interval between the first time and the second time, the longer the duration of the active state of the clock signal F _ OSC, i.e. the longer the on time of the main switch M1, and the main switch M1 is turned on again after the first preset time has elapsed after being turned off, i.e. the off time thereof is a constant off time during the second time period. Therefore, in the second state, the smaller the off time required for the main switch M1, the longer the interval between the first time and the second time, the smaller the frequency of the ON signal F _ ON, and vice versa.

Continuing to refer to fig. 6, when the OFF signal F _ OFF does not transition all the time, after the clock signal F _ OSC transitions to the active state and continues for the second preset time, the second timing signal F _ T1 transitions to the active state, at this time, the output signal F _ LG1 of the and gate in fig. 2 transitions to the active state to set the second RS flip-flop, so that the non-signal F _ ONB transitions to the active state and the ON signal F _ ON transitions to the inactive state, at this time, the first RS flip-flop is reset, and its output signal F _ Q1 transitions to the inactive state, and at this time, the first timing circuit starts to count time, after the first preset time continues, the first timing signal F _ T1 transitions to the active state to reset the second RS flip-flop, so that the non-signal F _ ONB transitions to the inactive state and the ON signal F _ ON transitions to the active state, to control the main switch tube M1 to conduct at this time.

As can be seen from the waveform diagrams of fig. 4 and 5, the switching power supply 100 controlled by the control circuit provided in the present invention can implement smooth switching (automatic switching) between the fixed-frequency operating mode and the variable-frequency fixed-off operating mode, and does not need a special mode determining circuit to provide a mode switching signal to indicate the switching. In addition, the power supply is in a constant off time working mode in the frequency conversion process, so that the problem of subharmonic oscillation caused by insufficient subharmonic compensation due to frequency conversion is solved.

In addition, the invention also provides a control method of the switching power supply, the switching power supply comprises a main switching tube with the minimum turn-off time, and the control method mainly comprises the following steps: the required turn-off time of main switch pipe is greater than minimum turn-off time duration, control the switching frequency of main switch pipe is for predetermineeing the frequency, the required turn-off time of main switch pipe is less than during minimum turn-off time, control the switching frequency of main switch pipe with the required turn-off time of main switch pipe becomes positive correlation's frequency.

According to the control method provided by the invention, the turn-off time of the main switching tube in each switching period in which the turn-off time required by the main switching tube is less than the minimum turn-off time can be further controlled to be a preset value. And enabling the switching power supply to be in a variable-frequency and constant-off-time working mode during the period that the required off-time of the main switching tube is less than the minimum off-time.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A control circuit for a switching power supply including a main switching tube having a minimum off-time, comprising:

the conducting signal generating circuit is used for generating a conducting signal so as to control the conducting time of the main switching tube within a first preset time after the clock signal and the turn-off signal are effective; and

a turn-off signal generating circuit for generating the turn-off signal according to an error compensation signal between an output voltage feedback signal and a reference signal of the switching power supply and an inductive current sampling signal to control the turn-off time of the main switching tube, wherein,

2. The control circuit of claim 1, further comprising:

3. The control circuit of claim 2, wherein the turn-on signal generation circuit comprises:

a clock oscillation circuit for generating the clock signal according to a non-signal of the on signal,

wherein, in each switching period, the time when the clock signal jumps to the active state is a first time, the time when the off signal jumps to the active state is a second time, when the later one of the first time and the second time comes, the on signal jumps to the inactive state, and when the first preset time elapses, the first timing signal jumps to the active state to control the on signal to jump to the active state,

4. The control circuit of claim 3, wherein the clock oscillation circuit comprises a charging circuit, a charging capacitor, a comparison circuit, and a reset circuit,

5. The control circuit of claim 3, wherein the turn-on signal generation circuit further comprises:

6. The control circuit of claim 5, wherein the second logic circuit comprises:

and the inverter receives the non-signal and outputs the conducting signal.

7. A method for controlling a switching power supply including a main switching tube having a minimum off-time, comprising:

controlling the conduction time of the main switching tube by first preset time after the clock signal and the turn-off signal are both effective; and generating the turn-off signal according to an error compensation signal and an inductive current sampling signal between an output voltage feedback signal and a reference signal of the switching power supply to control the turn-off time of the main switching tube, wherein,

8. The control method according to claim 7, wherein an off time required for controlling the main switching tube is a preset value less than an off time in each switching period of the minimum off period.

9. A switching power supply comprising a control circuit as claimed in any one of claims 1 to 6.