CN217035616U - Small power semiconductor device - Google Patents
Small power semiconductor device Download PDFInfo
- Publication number
- CN217035616U CN217035616U CN202220671012.7U CN202220671012U CN217035616U CN 217035616 U CN217035616 U CN 217035616U CN 202220671012 U CN202220671012 U CN 202220671012U CN 217035616 U CN217035616 U CN 217035616U
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- CN
- China
- Prior art keywords
- chip
- packaging body
- left pin
- epoxy packaging
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Abstract
The utility model discloses a small power semiconductor device, comprising: by the chip base plate of epoxy packaging body cladding, 2 at least range upon range of chips and the connection piece that sets up, the other end that one end is located the right pin in the epoxy packaging body outside stretches into in the epoxy packaging body and is connected with the connection piece, and the other end that one end is located the left pin in the epoxy packaging body outside stretches into in the epoxy packaging body and is connected with the chip base plate, the chip base plate further includes: the level sets up the main part under the chip and the portion of bending that is located main part one end and downwardly extending, the lower extreme and the left pin of the portion of bending are connected and chip one end edge cover in the top of the junction of the portion of bending and left pin. The utility model can realize the packaging of a large chip with a small structure and can effectively avoid the risk caused by the contact of the chip substrate and the non-welding area at the edge of the chip.
Description
Technical Field
The utility model relates to the technical field of semiconductor packaging, in particular to a small power semiconductor device.
Background
With the rapid development of integrated circuits, especially ultra-large scale integrated circuits, in order to realize higher power applications, part of power devices need a product structure with stacked multiple layers of chips. However, the inside of the existing product is a structure of multiple layers of chip spacing copper sheets, so that the purposes of buffering stress between chips and increasing heat dissipation performance are achieved, and the problem caused by the fact that the thickness of the product is relatively thick is solved.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a small-sized power semiconductor device which can realize the packaging of a large chip with a small structure and can effectively avoid the risk caused by the contact of a chip substrate and a non-welding area at the edge of the chip.
In order to achieve the purpose, the utility model adopts the technical scheme that: a miniature power semiconductor device comprising: by the chip base plate of epoxy packaging body cladding, 2 at least range upon range of chips and the connection piece that sets up, the other end that one end is located the right pin in the epoxy packaging body outside stretches into in the epoxy packaging body and is connected with the connection piece, and the other end that one end is located the left pin in the epoxy packaging body outside stretches into in the epoxy packaging body and is connected with the chip base plate, the chip base plate further includes: the level sets up the main part under the chip and the portion of bending that is located main part one end and downwardly extending, the lower extreme and the left pin of the portion of bending are connected and chip one end edge cover in the top of the junction of the portion of bending and left pin.
The further improved scheme in the technical scheme is as follows:
1. in the above scheme, the main body part of the chip substrate is provided with a groove back to the upper surface of one end of the left pin, and the groove is positioned under the edge of the other end of the chip.
2. In the above scheme, the horizontally arranged left pin is flush with the bottom surface of the epoxy packaging body.
3. In the scheme, the right pin is connected with the connecting sheet through welding.
4. In the above scheme, the left pin and the chip substrate are in an integrally formed structure.
Due to the application of the technical scheme, compared with the prior art, the utility model has the following advantages and effects:
the chip substrate of the small power semiconductor device is provided with the main body part horizontally arranged right below the chip and the bending part which is positioned at one end of the main body part and extends downwards, the lower end of the bending part is connected with the left pin, and the edge of one end of the chip covers the upper part of the joint of the bending part and the left pin.
Drawings
FIG. 1 is a top view of a miniature power semiconductor device in accordance with the present invention;
FIG. 2 is a cross-sectional elevation view of a small power semiconductor device of the present invention;
fig. 3 is an enlarged view of fig. 2 a of the present invention.
In the above drawings: 1. an epoxy package; 2. a chip substrate; 3. a chip; 4. connecting sheets; 5. a right pin; 6. a left pin; 71. a main body portion; 72. a bending part; 73. and (4) a groove.
Detailed Description
The utility model is further described with reference to the following figures and examples:
example 1: a miniature power semiconductor device comprising: by chip substrate 2, 2 at least range upon range of chips 3 and the connection piece 4 that set up of epoxy packaging body 1 cladding, the other end that one end is located the right pin 5 in the epoxy packaging body 1 outside stretches into epoxy packaging body 1 and is connected with connection piece 4, and the other end that one end is located the left pin 6 in the epoxy packaging body 1 outside stretches into epoxy packaging body 1 and is connected with chip substrate 2, chip substrate 2 further includes: the chip comprises a main body part 71 horizontally arranged right below the chip 3 and a bending part 72 located at one end of the main body part 7 and extending downwards, wherein the lower end of the bending part 72 is connected with the left pin 6, and the edge of one end of the chip 3 covers the upper part of the joint of the bending part 72 and the left pin 6.
The main body 71 of the chip substrate 2 is provided with a groove 73 on the upper surface opposite to one end of the left lead 6, and the groove 73 is located right below the edge of the other end of the chip 3.
The left pin 6 and the chip substrate 2 are integrally formed.
Example 2: a miniature power semiconductor device comprising: by chip substrate 2, 2 at least range upon range of chips 3 and the connection piece 4 that set up of epoxy packaging body 1 cladding, the other end that one end is located the right pin 5 in the epoxy packaging body 1 outside stretches into epoxy packaging body 1 and is connected with connection piece 4, and the other end that one end is located the left pin 6 in the epoxy packaging body 1 outside stretches into epoxy packaging body 1 and is connected with chip substrate 2, chip substrate 2 further includes: the chip comprises a main body part 71 horizontally arranged right below the chip 3 and a bending part 72 located at one end of the main body part 7 and extending downwards, wherein the lower end of the bending part 72 is connected with the left pin 6, and the edge of one end of the chip 3 covers the upper part of the joint of the bending part 72 and the left pin 6.
The main body 71 of the chip substrate 2 is provided with a groove 73 on the upper surface opposite to one end of the left lead 6, and the groove 73 is located right below the edge of the other end of the chip 3.
The horizontally arranged left pin 6 is flush with the bottom surface of the epoxy package 1.
The right pin 5 is connected with the connecting sheet 4 through welding.
When adopting above-mentioned small-size power semiconductor device, the other end of its one end position in the right pin in the epoxy packaging body outside stretches into in the epoxy packaging body and is connected with the connection piece, and the other end that one end position in the left pin in the epoxy packaging body outside stretches into in the epoxy packaging body and is connected with the chip substrate, and the chip substrate further includes: the level sets up in the main part under the chip and the portion of bending that is located main part one end and downwardly extending, the lower extreme and the left pin of the portion of bending are connected and chip one end edge cover in the top of the junction of the portion of bending and left pin, adopt the chip substrate similar with chip area, both can realize the big chip of small-structure encapsulation, can effectively avoid the risk that chip substrate and chip edge non-welding area contact lead to again, can also guarantee the thickness of chip edge epoxy and the mechanical stress that the buffer product produced the chip in the muscle separating process of cutting when reducing packaging structure, guarantee to produce the stability of performance.
The above embodiments are only for illustrating the technical idea and features of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the content of the present invention and implement the present invention, and not to limit the protection scope of the present invention by this means. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (5)
1. A miniature power semiconductor device comprising: by chip substrate (2) of epoxy packaging body (1) cladding, chip (3) and connection piece (4) of 2 at least range upon range of settings, the other end that one end is located right pin (5) in epoxy packaging body (1) outside stretches into epoxy packaging body (1) and is connected with connection piece (4), the other end that one end is located left pin (6) in epoxy packaging body (1) outside stretches into epoxy packaging body (1) and is connected with chip substrate (2), its characterized in that: the chip substrate (2) further comprises: the chip comprises a main body part (71) horizontally arranged under the chip (3) and a bending part (72) located at one end of the main body part (71) and extending downwards, wherein the lower end of the bending part (72) is connected with the left pin (6), and the edge of one end of the chip (3) covers the upper part of the joint of the bending part (72) and the left pin (6).
2. The miniature power semiconductor device of claim 1, wherein: a groove (73) is formed in the upper surface, back to one end of the left pin (6), of the main body portion (71) of the chip substrate (2), and the groove (73) is located right below the edge of the other end of the chip (3).
3. A miniature power semiconductor device according to claim 1, wherein: the horizontally arranged left pin (6) is flush with the bottom surface of the epoxy packaging body (1).
4. A miniature power semiconductor device according to claim 1, wherein: the right pin (5) is connected with the connecting sheet (4) through welding.
5. The miniature power semiconductor device of claim 1, wherein: the left pin (6) and the chip substrate (2) are of an integrated structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220671012.7U CN217035616U (en) | 2022-03-25 | 2022-03-25 | Small power semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220671012.7U CN217035616U (en) | 2022-03-25 | 2022-03-25 | Small power semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217035616U true CN217035616U (en) | 2022-07-22 |
Family
ID=82413474
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220671012.7U Active CN217035616U (en) | 2022-03-25 | 2022-03-25 | Small power semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217035616U (en) |
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2022
- 2022-03-25 CN CN202220671012.7U patent/CN217035616U/en active Active
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