CN216848052U - Power chip rapid test substrate structure - Google Patents
Power chip rapid test substrate structure Download PDFInfo
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- CN216848052U CN216848052U CN202220215213.6U CN202220215213U CN216848052U CN 216848052 U CN216848052 U CN 216848052U CN 202220215213 U CN202220215213 U CN 202220215213U CN 216848052 U CN216848052 U CN 216848052U
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Abstract
The utility model discloses a power chip rapid test substrate structure, which comprises an insulating substrate, wherein a welding area and a metal area are arranged on the insulating substrate; the welding area is used for installing a chip to be tested in the chip testing process; the metal area comprises a first metal area, a second metal area and a third metal area, the first metal area, the second metal area and the third metal area are insulated and isolated from each other, a welding area is connected with the second metal area, and the welding area is insulated and isolated from the first metal area and the third metal area; the first metal area and the second metal area both comprise a first connecting portion and a second connecting portion, the first connecting portion are arranged on the insulating substrate and used for being connected with a testing electrode of a chip to be tested in the chip testing process, and the second connecting portion are arranged outside the insulating substrate and used for being connected with a testing circuit in the chip testing process. The utility model discloses can assess fast and await measuring power chip, shorten chip aassessment verification cycle.
Description
Technical Field
The utility model relates to a semiconductor power device technical field, in particular to power chip tests base plate structure fast.
Background
At present, for power device products such as IGBTs, MOSFETs and the like, it is generally necessary to package a die (chip) on a wafer after the wafer is produced, and perform test evaluation of parameter performance after the package. Because chip packaging needs a certain period, the packaging form can limit the size of a chip to be packaged, and parasitic parameters of a test circuit for testing the chip can influence the test precision in the process of packaging the chip into a three-terminal device.
Therefore, a package substrate structure suitable for rapidly and precisely evaluating a power chip is needed at present, so that the power chip to be tested can be rapidly evaluated, and the evaluation and verification period of the chip can be shortened.
SUMMERY OF THE UTILITY MODEL
For the current packaging process who solves can extend research and development cycle's technical problem, the utility model provides a power chip tests substrate structure fast, specific technical scheme as follows:
the utility model provides a power chip tests base plate structure fast, include:
the circuit board comprises an insulating substrate, wherein a welding area and a metal area are arranged on the insulating substrate;
the welding area is used for installing a chip to be tested in the chip testing process;
the metal region comprises a first metal region, a second metal region and a third metal region, the first metal region, the second metal region and the third metal region are insulated and isolated from each other, the welding region is connected with the second metal region, and the welding region is insulated and isolated from the first metal region and the third metal region;
the first metal area and the second metal area comprise first connecting parts and second connecting parts, the first connecting parts are arranged on the insulating substrate and used for being connected with testing electrodes of chips to be tested in the chip testing process, and the second connecting parts are arranged outside the insulating substrate and used for being connected with a testing circuit in the chip testing process.
The utility model provides a chip and test circuit that await measuring can be connected to power chip test substrate structure fast, realizes need not to encapsulate the chip and can test, realizes assessing the technological effect that awaits measuring power chip fast, shortens chip assessment verification cycle.
In some embodiments, the metal region comprises a first metal region, a second metal region, and a third metal region;
the first connecting part of the first metal area is used for being connected with the grid electrode of the chip to be tested through a routing in the test process, the first connecting part of the second metal area is used for being connected with the back electrode of the chip to be tested in the test process, and the first connecting part of the third metal area is used for being connected with the source electrode or the emitting electrode of the chip to be tested through the routing in the test process.
The utility model provides a power chip tests substrate structure fast sets up three metal area and space of a whole page structure, improves chip test process's accuracy and efficiency of software testing.
In some embodiments, the third metal region further comprises a third connection for connecting with a kelvin test terminal during testing.
The utility model provides a power chip tests base plate structure fast connects kelvin test end through setting up third connecting portion, carries out the kelvin test, further improves the accuracy that need not the in-process test that the encapsulation process carried out the chip test.
In some embodiments, the width of the first connection portion in the third metal region is greater than the width of the first connection portion in the first metal region.
The utility model provides a power chip tests base plate structure fast can make and be connected many metal wires between chip source electrode or projecting pole and the third metal area, and then improves the degree of accuracy of chip test process.
In some embodiments, the width of the second connection portions is less than the width of the first connection portions.
In some embodiments, the first metal region and the third metal region are disposed on the same side of the weld region.
The utility model provides a power chip tests substrate structure fast sets up first metal area and third metal area in the homonymy of weld zone, reserves out the bigger weld zone of size on the same size's insulating substrate.
In some embodiments, the first metal region and the third metal region are disposed on opposite sides of the bonding region, a position of the first connection portion in the first metal region corresponds to a gate of the chip to be tested, and a position of the first connection portion in the third metal region corresponds to a source or an emitter of the chip to be tested.
The utility model provides a power chip tests substrate structure fast sets up first metal area and third metal area in the heteroscedasia of weld zone to according to the position of the first metal area of electrode position adjustment and third metal area in the chip, reduce the length of routing between electrode and the metal area in the chip, and then reduce parasitic inductance, improve the accuracy of chip test.
In some embodiments, the second connection portion of the metal region is provided with a plug-in connection key matched with the test circuit.
The utility model provides a power chip tests base plate structure fast can be directly be connected with test circuit with the mode of the second connecting portion of metal area through the plug, and then improves test speed.
The utility model provides a power chip tests base plate structure fast includes a following technological effect at least:
(1) the chip to be tested and the test circuit are connected, so that the chip can be tested without being packaged, the technical effect of quickly evaluating the power chip to be tested is realized, and the evaluation and verification period of the chip is shortened;
(2) the third connecting part is arranged to be connected with the Kelvin test end to carry out Kelvin test, so that the test accuracy in the process of carrying out chip test without a packaging process is further improved;
(3) a plurality of metal wires are connected between the chip source electrode or the emitting electrode and the third metal area, so that the accuracy of the chip testing process is improved;
(4) the first metal area and the third metal area are arranged on the same side of the welding area, and the welding area with larger size is reserved on the insulating substrate with the same size;
(5) the first metal area and the third metal area are arranged on different sides of the welding area, and the positions of the first metal area and the third metal area are adjusted according to the positions of the electrodes in the chip, so that the length of routing between the electrodes and the metal areas in the chip is reduced, the parasitic inductance is further reduced, and the accuracy of chip testing is improved;
(6) through setting up plug-in connection key can be directly be connected the second connecting portion of metal zone with test circuit through the mode of plug, and then improve test speed.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive effort.
Fig. 1 is an exemplary diagram of a power chip rapid test substrate structure according to the present invention;
FIG. 2 is an illustration of a substrate during a test process of a fast test substrate structure for a power chip according to the present invention;
fig. 3 is another exemplary diagram of a power chip rapid test substrate structure according to the present invention;
fig. 4 is another exemplary diagram of a substrate during a test process of a power chip rapid test substrate structure according to the present invention.
Reference numbers in the figures: the structure comprises an insulating substrate-1, a welding area-2, a first metal area-3, a first connecting part-3.1 of the first metal area 3, a second connecting part-3.2 of the first metal area 3, a second metal area-4, a first connecting part-4.1 of the second metal area 4, a second connecting part-4.2 of the second metal area 4, a third metal area-5, a first connecting part-5.1 of the third metal area 5, a second connecting part-5.2 of the third metal area 5 and a third connecting part-5.3 of the third metal area 5.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
For the sake of simplicity, only the parts relevant to the present invention are schematically shown in the drawings, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically depicted, or only one of them is labeled. In this document, "one" means not only "only one" but also a case of "more than one".
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
In addition, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not intended to indicate or imply relative importance.
In order to more clearly illustrate embodiments of the present invention or technical solutions in the prior art, specific embodiments of the present invention will be described below with reference to the accompanying drawings. It is obvious that the drawings in the following description are only examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be obtained from these drawings without inventive effort.
The utility model discloses an embodiment, as shown in FIG. 1, the utility model provides a power chip tests base plate structure fast, include:
be provided with bonding pad 2 and metal area on insulating substrate 1, bonding pad 2 is used for installing the chip that awaits measuring in chip test process, the metal area includes first metal area 3, second metal area 4 and third metal area 5, first metal area 3, second metal area 4 and third metal area 5 are insulating isolation each other, bonding pad 2 is connected with second metal area 4, bonding pad 2 is insulating isolation with first metal area 3 and third metal area 5, the metal area all includes first connecting portion and second connecting portion, first connecting portion all set up on insulating substrate 1, be used for being connected with the test electrode of the chip that awaits measuring in the chip test process, the second connecting portion all set up outside insulating substrate 1, be used for being connected with test circuit in the chip test process.
In one embodiment, as shown in fig. 1, the first metal region 3 is used for connecting with a gate of a chip to be tested through a wire bonding during a test process, the second metal region 4 is used for connecting with a back electrode of the chip to be tested during the test process, and the third metal region 5 is used for connecting with a source or an emitter of the chip to be tested through a wire bonding during the test process.
Specifically, the first metal area 3 includes a first connection portion 3.1 of the first metal area 3 and a second connection portion 3.2 of the first metal area 3, and a width of the second connection portion 3.2 of the first metal area 3 is smaller than a width of the first connection portion 3.1 of the first metal area 3.
The second metal area 4 comprises a first connection portion 4.1 of the second metal area 4 and a second connection portion 4.2 of the second metal area 4, and the width of the second connection portion 4.2 of the second metal area 4 is smaller than the width of the first connection portion 4.1 of the second metal area 4.
The third metal area 5 comprises a first connection portion 5.1 of the third metal area 5 and a second connection portion 5.2 of the third metal area 5, and the width of the second connection portion 5.2 of the third metal area 5 is smaller than the width of the first connection portion 5.1 of the third metal area 5.
The power chip rapid test substrate structure provided by the embodiment can be used for connecting the power chip to be tested and the test circuit through the substrate, so that the power chip to be tested can be rapidly evaluated, and the chip evaluation verification period is shortened.
In one embodiment, as shown in fig. 1, the third metal region 5 further comprises a third connection portion 5.3 of the third metal region 5, wherein the third connection portion 5.3 of the third metal region 5 is used for connecting with a kelvin test terminal during a test to perform a kelvin test, thereby ensuring accuracy of the test.
In one embodiment, the third connecting portion 5.3 of the third metal area 5 is provided with a plug-in connector key for mating with the kelvin test terminal, and the width of the plug-in connector key of the third connecting portion 5.3 of the third metal area 5 is adjusted according to the size of the kelvin test terminal.
In one embodiment, the second connection portions 3.2, 4.2 and 5.2 of the first metal area 3, the second metal area 4 and the third metal area 5 are all provided with plug-in connection keys matched with the test electrodes of the test circuit, and the width of the plug-in connection keys is adjusted according to the size of the test electrodes of the test circuit.
In one embodiment, as shown in fig. 1, the first metal area 3 and the third metal area 5 are arranged on the same side of the welding area 2. For example, the first metal region 3 and the third metal region 5 are both provided on the lower side of the land 2.
In one embodiment, as shown in fig. 1, the second connection portion 3.2 of the first metal area 3, the second connection portion 4.2 of the second metal area 4, the second connection portion 5.2 of the third metal area 5 and the third connection portion 5.3 of the third metal area 5 are arranged in parallel with each other, so that the pins of the second connection portion 3.2 of the first metal area 3, the second connection portion 4.2 of the second metal area 4, the second connection portion 5.2 of the third metal area 5 and the third connection portion 5.3 of the third metal area 5 can be found intuitively in the process of testing the circuit connection.
In an embodiment, the relative positions of the second connection portion 3.2 of the first metal area 3, the second connection portion 4.2 of the second metal area 4, the second connection portion 5.2 of the third metal area 5 and the third connection portion 5.3 of the third metal area 5 may not be limited.
In one embodiment, as shown in fig. 1, the second connection portions 3.2 of the first metal region 3, the second connection portions 4.2 of the second metal region 4, the second connection portions 5.2 of the third metal region 5 and the third connection portions 5.3 of the third metal region 5 have the same width, and the width of the first connection portions 5.1 of the third metal region 5 is greater than the width of the first connection portions 3.1 of the first metal region 3. And a plurality of metal wires are connected between the source electrode or the emitter of the chip and the first connecting part of the third metal area 5, so that the accuracy of the test parameters is improved conveniently.
In one embodiment, as shown in fig. 2, in the process of performing a chip test by using the substrate structure for rapidly testing a power chip provided by the present application, a chip to be tested is soldered on the soldering region 2, a back electrode of the chip is electrically connected to the second metal region 4, a front electrode of the chip is led out to the first metal region 3 and the third metal region 5 by a wire bonding method, and the substrate is subjected to test evaluation, such as a static test, a dynamic test, a tolerance test, and the like. In the process of testing the MOS chip, pins of the second connecting part 3.2 of the first metal region 3, the second connecting part 4.2 of the second metal region 4 and the second connecting part 5.2 of the third metal region 5 are respectively connected with a grid electrode, a drain electrode and a source electrode of a test circuit, and pins of the third connecting part 5.3 of the third metal region 5 are used for Kelvin test, so that the test accuracy is ensured. When the IGBT chip is tested, pins of the second connecting part 3.2 of the first metal area 3, the second connecting part 4.2 of the second metal area 4 and the second connecting part 5.2 of the third metal area 5 are respectively connected with a grid electrode, a collector electrode and an emitter electrode of a test circuit, and the pin of the third connecting part 5.3 of the third metal area 5 is used as a sense end of the emitter electrode of the chip to be tested for Kelvin test.
In one embodiment, as shown in fig. 3, the present invention further provides a substrate structure for fast testing a power chip, wherein the first metal region 3 and the third metal region 5 are disposed on opposite sides of the bonding pad 2, the first metal region 3 is disposed on the left side of the bonding pad 2, and the second metal region 4 and the third metal region 5 are both disposed on the lower side of the bonding pad.
In one embodiment, as shown in fig. 4, in the chip testing process using the power chip rapid test substrate structure shown in fig. 3, the first metal region 3 is disposed on the left side of the bonding region 2, so that the length of a wire bonding between the first connection portion 3.1 of the first metal region 3 and the gate of the chip to be tested can be reduced, parasitic inductance can be reduced, and the testing accuracy can be further improved. While the size of the bond pad 2 can be adjusted to accommodate different size chips.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or recited in detail in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed fast test substrate structure for power chips may be implemented in other manners. For example, the above-described embodiment of a power chip rapid test substrate structure is merely illustrative, and for example, the division of the module or unit is only a logical function division, and there may be other division ways in actual implementation, for example, a plurality of units or modules may be combined or may be integrated into another system, or some features may be omitted or not executed. In addition, the communication links shown or discussed may be through interfaces, devices or units, or integrated circuits, and may be electrical, mechanical or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
It should be noted that the above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, many modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (8)
1. A power chip fast test substrate structure is characterized by comprising:
the circuit board comprises an insulating substrate, wherein a welding area and a metal area are arranged on the insulating substrate;
the welding area is used for installing a chip to be tested in the chip testing process;
the metal region comprises a first metal region, a second metal region and a third metal region, the first metal region, the second metal region and the third metal region are insulated and isolated from each other, the welding region is connected with the second metal region, and the welding region is insulated and isolated from the first metal region and the third metal region;
the first metal area and the second metal area comprise first connecting parts and second connecting parts, the first connecting parts are arranged on the insulating substrate and used for being connected with testing electrodes of chips to be tested in the chip testing process, and the second connecting parts are arranged outside the insulating substrate and used for being connected with a testing circuit in the chip testing process.
2. The substrate structure for rapid test of power chips as claimed in claim 1,
the first connecting part of the first metal area is used for being connected with the grid electrode of the chip to be tested through a routing in the test process, the first connecting part of the second metal area is used for being connected with the back electrode of the chip to be tested in the test process, and the first connecting part of the third metal area is used for being connected with the source electrode or the emitting electrode of the chip to be tested through the routing in the test process.
3. The substrate structure for rapid test of power chips as claimed in claim 1,
the third metal region further comprises a third connection portion for connecting with a kelvin test terminal during a test process.
4. The substrate structure for rapid testing of power chips as defined in claim 1,
the width of the first connecting part in the third metal area is larger than that of the first connecting part in the first metal area.
5. The substrate structure for rapid test of power chips as claimed in claim 1,
the width of the second connecting portion is smaller than that of the first connecting portion.
6. The substrate structure for rapid testing of power chips as defined in claim 1,
the first metal region and the third metal region are disposed on the same side of the bonding region.
7. The substrate structure for rapid testing of power chips as defined in claim 1,
the first metal area and the third metal area are arranged on different sides of the welding area, the position of the first connecting portion in the first metal area corresponds to the grid electrode of the chip to be tested, and the position of the first connecting portion in the third metal area corresponds to the position of the source electrode or the emitting electrode of the chip to be tested.
8. The substrate structure for rapid testing of power chips as claimed in any one of claims 1 to 7,
and the second connecting part of the metal area is provided with a plug-in connecting key matched with the test circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220215213.6U CN216848052U (en) | 2022-01-26 | 2022-01-26 | Power chip rapid test substrate structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220215213.6U CN216848052U (en) | 2022-01-26 | 2022-01-26 | Power chip rapid test substrate structure |
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| CN216848052U true CN216848052U (en) | 2022-06-28 |
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| CN202220215213.6U Active CN216848052U (en) | 2022-01-26 | 2022-01-26 | Power chip rapid test substrate structure |
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