CN216794940U - Power amplification circuit based on Doherty high-gain high-final-stage efficiency - Google Patents
Power amplification circuit based on Doherty high-gain high-final-stage efficiency Download PDFInfo
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- CN216794940U CN216794940U CN202220100102.0U CN202220100102U CN216794940U CN 216794940 U CN216794940 U CN 216794940U CN 202220100102 U CN202220100102 U CN 202220100102U CN 216794940 U CN216794940 U CN 216794940U
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Abstract
The utility model provides a Doherty-based high-gain high-final-stage-efficiency power amplification circuit which comprises a preceding-stage small-signal amplification circuit, a carrier power amplification circuit, a peak power amplification circuit, a power divider and a combiner, wherein the input end of the preceding-stage small-signal amplification circuit is connected with the signal input end, the output end of the preceding-stage small-signal amplification circuit is respectively connected with the input end of the carrier power amplification circuit and the input end of the peak power amplification circuit through the power divider, and the output end of the carrier power amplification circuit and the output end of the peak power amplification circuit are connected with the signal output end through the combiner. When the input power can not meet the Doherty power amplifier, a small-signal power amplifier is added in front of the power divider, so that the output efficiency can meet the requirement, and the integral gain of the circuit can be improved; meanwhile, the final stage combines the two signals through the combiner, and finally outputs the amplified signal in the frequency band range, so that the efficiency of the final stage is kept high in the rollback region.
Description
Technical Field
The utility model relates to the technical field of radio frequency power amplification, in particular to a power amplification circuit based on Doherty high-gain high-final-stage efficiency.
Background
Radio frequency power amplifiers are an important component of communication systems, especially in transmission systems, where their importance is self evident. In a front-stage circuit of a transmitter, the power of a radio frequency signal generated by a modulator is very low, so that the radio frequency signal needs to be amplified by an amplifier to obtain enough radio frequency power, and then the radio frequency signal can be transmitted to an antenna to be radiated. In order to obtain a sufficiently large rf output power, an rf power amplifier must be used. The radio frequency modulated signal is amplified by the radio frequency power amplifier to meet the transmitted power, passes through the matching network and is transmitted by the antenna.
Because the traditional saturation high-efficiency power amplifier cannot meet the requirements of most of the existing transmitting systems, the applicable Doherty power amplifier can still maintain high efficiency in a certain output power back-off region. In the prior art, the circuit structure of the Doherty power amplifier is composed of two parts, namely a carrier power amplifier and a peak power amplifier. When the carrier power amplifier is saturated, the peak power amplifier is turned on, and finally the two paths of power amplifiers are saturated, and simulation shows that high efficiency can still be kept in a backspacing region. When the input power signal at the input terminal cannot satisfy the input power of the Doherty power amplifier, the Doherty power amplifier cannot satisfy the requirement of continuously maintaining high efficiency in the back-off region.
SUMMERY OF THE UTILITY MODEL
The technical problem to be solved by the utility model is as follows: a power amplifying circuit based on Doherty high-gain high-final-stage efficiency is provided to solve the problem that when the input power cannot meet the input power of a Doherty power amplifier, high efficiency and gain cannot be maintained in a back-off region.
The technical scheme adopted by the utility model for solving the problems is as follows: the input end of the pre-stage small signal amplifying circuit is connected with the signal input end, the output end of the pre-stage small signal amplifying circuit is respectively connected with the input end of the carrier power amplifying circuit and the input end of the peak power amplifying circuit through the power divider, and the output end of the carrier power amplifying circuit and the output end of the peak power amplifying circuit are connected with the signal output end through the combiner.
Compared with the prior art, the utility model has the advantages that: when the input power can not meet the input power of the Doherty power amplifier, a small-signal power amplifier is added in front of the power divider, so that the output efficiency can meet the requirement, and the overall gain of the circuit can be improved; meanwhile, the final stage combines the two signals through the combiner, and finally outputs an amplified signal in a frequency band range, so that the efficiency of the final stage is kept high in a backspacing region.
Preferably, the preceding-stage small-signal amplifying circuit comprises a first input matching network, a first field-effect transistor Q1 and a first output matching network, one end of the first input matching network is connected with the signal input end, the other end of the first input matching network is connected with the gate of the first field-effect transistor Q1, the source of the first field-effect transistor Q1 is grounded, the drain of the first field-effect transistor Q1 is connected with one end of the first output matching network, and the other end of the first output matching network is connected with the input end of the power divider. Therefore, the stability of the input signal is ensured and the interference is reduced through the first input matching network and the first output matching network.
Preferably, the carrier power amplifying circuit comprises a second input matching network, a second field effect transistor Q2 and a second output matching network, and the peak power amplifying circuit comprises a third input matching network, a third field effect transistor Q3 and a third output matching network; the first output end of the power divider is connected with the gate of a second field-effect tube Q2 through a second input matching network, the source of the second field-effect tube Q2 is grounded, and the drain of the second field-effect tube Q2 is connected with the first input end of the combiner through a second output matching network; the second output end of the power divider is connected with the gate of a third field-effect tube Q3 through a third input matching network, the source of the third field-effect tube Q3 is grounded, and the drain of the third field-effect tube Q3 is connected with the second input end of the combiner through a third output matching network.
Preferably, the carrier power amplifying circuit further includes a λ/4 compensation line circuit, and the second output matching network is connected to the first input terminal of the combiner through the λ/4 compensation line circuit; the peak power amplifying circuit further comprises a first phase compensation line circuit, and the second output end of the power divider is connected with the third input matching network through the first phase compensation line circuit. In this way, the adverse effect of oscillation can be reduced by the λ/4 compensation line circuit and the first phase compensation line circuit.
Preferably, the preceding-stage small-signal amplifying circuit further includes a first blocking capacitor C1 and a first RC circuit, one end of the first input matching network is connected to the signal input end through the first blocking capacitor C1, and the other end of the first input matching network is connected to the gate of the first field-effect transistor Q1 through the first RC circuit. Therefore, the two circuits are isolated through the blocking capacitor, and simultaneously, the function of transmitting signals is also borne, and the high capacity is favorable for the transmission of low-frequency signals; the RC circuit is capable of storing energy that oscillates when the circuit resonates.
Preferably, the carrier power amplifying circuit further includes a third dc blocking capacitor C3, a second RC circuit, and a fourth dc blocking capacitor C4, the first output terminal of the power divider is connected to one end of a second input matching network through the third dc blocking capacitor C3, the other end of the second input matching network is connected to the gate of the second fet Q2 through the second RC circuit, and the second output matching network is connected to the λ/4 compensation line circuit through the fourth dc blocking capacitor C4. Therefore, the two circuits are isolated through the blocking capacitor, and simultaneously, the function of transmitting signals is also borne, and the high capacity is favorable for the transmission of low-frequency signals; the RC circuit can enable the power amplifier tube to work in a stable area.
Preferably, the peak power amplifying circuit further includes a fifth dc blocking capacitor C5, a third RC circuit, a sixth dc blocking capacitor C6, and a second phase compensation line circuit, the first phase compensation line circuit is connected to one end of a third input matching network through the fifth dc blocking capacitor C5, the other end of the third input matching network is connected to the gate of the third fet Q3 through the third RC circuit, and the third output matching network is connected to the second input terminal of the combiner through the sixth dc blocking capacitor C6 and the second phase compensation line circuit in series. Therefore, the two circuits are isolated through the blocking capacitor, and simultaneously, the function of transmitting signals is also borne, and the high capacity is favorable for the transmission of low-frequency signals; the RC circuit can enable the power amplifier tube to work in a stable area.
Preferably, the gate and the drain of the first fet Q1, the gate and the drain of the second fet Q2, and the gate and the drain of the third fet Q3 are all respectively connected to a bias circuit, the bias circuit includes a plurality of capacitors and a resistor, the resistor is connected to a power supply, and the resistor is grounded through the plurality of capacitors. Thus, proper bias current is provided for each amplification stage through the bias circuit, and the static operating point of each stage is determined.
Preferably, the output end of the combiner is connected with the signal output end through a fourth output matching network. Therefore, the fourth output matching network enables the signal output to be stable, and interference is reduced.
Preferably, the first output matching network is connected with the input end of the power divider through a second dc blocking capacitor C2. Therefore, the two circuits are isolated by the blocking capacitor, and simultaneously, the function of transmitting signals is also played, and the high capacity is beneficial to the transmission of low-frequency signals.
Drawings
FIG. 1 is a system block diagram of a Doherty-based high-gain high-final-stage-efficiency power amplifier circuit according to the present invention;
FIG. 2 is a schematic structural diagram of a Doherty-based high-gain high-final-stage-efficiency power amplifier circuit of the present invention;
FIG. 3 is a detailed circuit diagram of a Doherty-based power amplifier circuit with high gain and high final efficiency according to the present invention;
FIG. 4 is a curve of the drain efficiency of the Doherty-based high-gain high-final-stage efficiency power amplifier circuit varying with the input power according to the present invention;
FIG. 5 is a curve of the gain variation with frequency of a Doherty-based high-gain high-final-stage-efficiency power amplifier circuit of the present invention;
fig. 6 is an analysis diagram of the input power and the gain of the power amplifier circuit based on the Doherty high-gain high-final-stage efficiency.
Description of reference numerals: 11. a first input matching network, 12, a first output matching network, 21, a second input matching network, 22, a second output matching network, 23, a lambda/4 compensation line circuit, 31, a third input matching network, 32, a third output matching network, 33, a first phase compensation line circuit, 34, a second phase compensation line circuit, 4, a fourth output matching network.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
As shown in fig. 1 to 6, the present embodiment relates to a power amplification circuit based on Doherty high-gain high-final-stage efficiency, which includes a preceding-stage small-signal amplification circuit, a carrier power amplification circuit, a peak power amplification circuit, a power divider, and a combiner.
The input end of the preceding stage small signal amplifying circuit is connected with the signal input end, the output end of the preceding stage small signal amplifying circuit is respectively connected with the input end of the carrier power amplifying circuit and the input end of the peak power amplifying circuit through the power divider, and the output end of the carrier power amplifying circuit and the output end of the peak power amplifying circuit are connected with the signal output end through the combiner.
Even if a small signal is input, the input signal can be amplified to proper input power by additionally arranging the front-stage small signal amplifying circuit, and the overall gain of the whole circuit is improved.
The front-stage small signal amplifying circuit comprises a first input matching network 11, a first field-effect tube Q1 and a first output matching network 12, one end of the first input matching network 11 is connected with a signal input end, the other end of the first input matching network is connected with a grid electrode of a first field-effect tube Q1, a source electrode of the first field-effect tube Q1 is grounded, a drain electrode of the first field-effect tube Q1 is connected with one end of the first output matching network 12, and the other end of the first output matching network 12 is connected with an input end of the power divider.
Through the first input matching network 11 and the first output matching network 12, the stability of the input signal is ensured, and the interference is reduced.
The carrier power amplifying circuit comprises a second input matching network 21, a second field-effect tube Q2 and a second output matching network 22, and the peak power amplifying circuit comprises a third input matching network 31, a third field-effect tube Q3 and a third output matching network 32;
the first output end of the power divider is connected with the gate of a second field-effect tube Q2 through a second input matching network 21, the source of the second field-effect tube Q2 is grounded, and the drain of the second field-effect tube Q2 is connected with the first input end of the combiner through a second output matching network 22;
the second output end of the power divider is connected with the gate of the third field effect transistor Q3 through the third input matching network 31, the source of the third field effect transistor Q3 is grounded, and the drain of the third field effect transistor Q3 is connected with the second input end of the combiner through the third output matching network 32.
In this embodiment, the signal input terminal is connected to the first input signal, the first input signal is converted into the first output signal by the preceding small-signal amplifying circuit, and the power divider outputs the first output signal to the second input signal and the third input signal through the first output terminal and the second output terminal, respectively. The carrier power amplifying circuit converts the second input signal into a second output signal to be output, and the peak power amplifying circuit converts the third input signal into a third output signal to be output. The combiner combines the two signals into one, and finally outputs a final output signal through a fourth output matching network 4, and the final output signal is connected with a signal output end. The power of the second input signal and the power of the third input signal may be the same or different.
The pre-stage small signal amplifying circuit works in class AB, the carrier power amplifying circuit works in class AB, and the peak power amplifying circuit works in class C.
In this embodiment, the carrier power amplifying circuit further includes a λ/4 compensation line circuit 23, and the second output matching network 22 is connected to the first input terminal of the combiner through the λ/4 compensation line circuit 23;
the peak power amplifying circuit further comprises a first phase compensation line circuit 33, and the second output of the power splitter is connected to the third input matching network 31 via the first phase compensation line circuit 33.
The adverse effect of oscillation can be reduced by the λ/4 compensation line circuit and the first phase compensation line circuit.
The front-stage small signal amplifying circuit further comprises a first blocking capacitor C1 and a first RC circuit, one end of the first input matching network 11 is connected with the signal input end through the first blocking capacitor C1, and the other end of the first input matching network 11 is connected with the grid electrode of the first field-effect transistor Q1 through the first RC circuit.
The carrier power amplifying circuit further comprises a third blocking capacitor C3, a second RC circuit and a fourth blocking capacitor C4, the first output end of the power divider is connected with one end of the second input matching network 21 through the third blocking capacitor C3, the other end of the second input matching network 21 is connected with the grid of the second field-effect transistor Q2 through the second RC circuit, and the second output matching network 22 is connected with the lambda/4 compensation line circuit 23 through the fourth blocking capacitor C4.
The peak power amplifying circuit further comprises a fifth blocking capacitor C5, a third RC circuit, a sixth blocking capacitor C6 and a second phase compensation line circuit 34, the first phase compensation line circuit 33 is connected with one end of the third input matching network 31 through the fifth blocking capacitor C5, the other end of the third input matching network 31 is connected with the gate of the third field effect transistor Q3 through the third RC circuit, and the third output matching network 32 is connected with the second input end of the combiner through the sixth blocking capacitor C6 and the second phase compensation line circuit 34 in series.
The two circuits are isolated through the blocking capacitor, and meanwhile, the function of transmitting signals is also borne, and the high capacity is favorable for the transmission of low-frequency signals; the RC circuit can enable the power amplifier tube to work in a stable area.
The grid and the drain of the first field-effect tube Q1, the grid and the drain of the second field-effect tube Q2 and the grid and the drain of the third field-effect tube Q3 are respectively connected with a bias circuit, the bias circuit comprises a plurality of capacitors and resistors, the resistors are connected with a power supply, and the resistors are grounded through the plurality of capacitors. And providing proper bias current for each amplification stage through a bias circuit to determine the static working point of each stage.
The output end of the combiner is connected with the signal output end through a fourth output matching network 4. And the fourth output matching network enables the signal output to be stable and reduces interference.
The first output matching network 12 is connected to the input of the power divider through a second dc blocking capacitor C2. The two circuits are isolated by the blocking capacitor, and simultaneously, the blocking capacitor also plays a role in transmitting signals, and the blocking capacitor is large in capacity and beneficial to transmission of low-frequency signals.
The embodiment is a front-stage power amplifying circuit and a Doherty power amplifying circuit designed based on a CREE radio frequency transistor CGH 40010. According to a data manual of a given CGH40010 chip, the grid voltage of a front-stage power amplification circuit is selected to be-2.8V, and the drain voltage end is selected to be 28V to serve as a static working point. In the Doherty power amplifying circuit, the grid voltage selected by the peak power amplifier is-4.5V, the drain voltage end is 33V, the grid voltage selected by the carrier power amplifier is-2.8V, and the drain voltage end is 28V.
As shown in fig. 4-6, the power of 10dBm is input to the front-stage power amplifier, the first output power after the front-stage amplification is 28dBm, the input power of 28dBm is divided by the power divider, the signals are respectively input to the main power amplifier and the auxiliary power amplifier, the two signals are combined and output by the combiner, finally, the total output power is about 40dBm in the frequency band range, the overall gain of the circuit is about 30dB, and the efficiency in the back-off region is kept at about 67% or more.
The utility model has the beneficial effects that: when the input power can not meet the input power of the Doherty power amplifier, a small-signal power amplifier is added in front of the power divider, so that the output efficiency can meet the requirement, and the overall gain of the circuit can be improved; meanwhile, the final stage combines the two signals through the combiner, and finally outputs an amplified signal in a frequency band range, so that the efficiency of the final stage is kept high in a backspacing region.
While the foregoing description shows and describes several preferred embodiments of the utility model, it is to be understood, as noted above, that the utility model is not limited to the forms disclosed herein, but is not intended to be exhaustive or to exclude other embodiments and may be used in various other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the utility model as defined by the appended claims.
Although the present disclosure has been described above, the scope of the present disclosure is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, and such changes and modifications will fall within the scope of the present invention.
Claims (10)
1. A power amplification circuit based on Doherty high-gain high-final-stage efficiency is characterized in that: the signal input end of the pre-stage small signal amplifying circuit is connected with the signal input end, the output end of the pre-stage small signal amplifying circuit is respectively connected with the input end of the carrier power amplifying circuit and the input end of the peak power amplifying circuit through the power divider, and the output end of the carrier power amplifying circuit and the output end of the peak power amplifying circuit are connected with the signal output end through the combiner.
2. The Doherty-based power amplifying circuit with high gain and high final efficiency as claimed in claim 1, wherein: the preceding stage small signal amplification circuit comprises a first input matching network (11), a first field effect transistor Q1 and a first output matching network (12), one end of the first input matching network (11) is connected with a signal input end, the other end of the first input matching network is connected with a grid electrode of a first field effect transistor Q1, a source electrode of the first field effect transistor Q1 is grounded, a drain electrode of the first field effect transistor Q1 is connected with one end of the first output matching network (12), and the other end of the first output matching network (12) is connected with an input end of a power divider.
3. The Doherty high-gain high-final-stage-efficiency-based power amplification circuit of claim 2, wherein: the carrier power amplifying circuit comprises a second input matching network (21), a second field effect transistor Q2 and a second output matching network (22), and the peak power amplifying circuit comprises a third input matching network (31), a third field effect transistor Q3 and a third output matching network (32);
the first output end of the power divider is connected with the grid electrode of a second field-effect tube Q2 through a second input matching network (21), the source electrode of the second field-effect tube Q2 is grounded, and the drain electrode of the second field-effect tube Q2 is connected with the first input end of the combiner through a second output matching network (22);
the second output end of the power divider is connected with the gate of a third field effect transistor Q3 through a third input matching network (31), the source of the third field effect transistor Q3 is grounded, and the drain of the third field effect transistor Q3 is connected with the second input end of the combiner through a third output matching network (32).
4. The Doherty high-gain high-final-stage-efficiency-based power amplification circuit of claim 3, wherein:
the carrier power amplifying circuit further comprises a lambda/4 compensation line circuit (23), and the second output matching network (22) is connected with the first input end of the combiner through the lambda/4 compensation line circuit (23);
the peak power amplifying circuit further comprises a first phase compensation line circuit (33), and the second output terminal of the power divider is connected to the third input matching network (31) through the first phase compensation line circuit (33).
5. The Doherty high-gain high-final-stage-efficiency-based power amplification circuit of claim 4, wherein: the preceding-stage small signal amplifying circuit further comprises a first blocking capacitor C1 and a first RC circuit, one end of the first input matching network (11) is connected with a signal input end through a first blocking capacitor C1, and the other end of the first input matching network (11) is connected with a grid electrode of the first field-effect transistor Q1 through the first RC circuit.
6. The Doherty-based power amplifying circuit with high gain and high final efficiency as claimed in claim 5, wherein: the carrier power amplifying circuit further comprises a third blocking capacitor C3, a second RC circuit and a fourth blocking capacitor C4, the first output end of the power divider is connected with one end of a second input matching network (21) through a third blocking capacitor C3, the other end of the second input matching network (21) is connected with the grid electrode of a second field-effect tube Q2 through a second RC circuit, and the second output matching network (22) is connected with a lambda/4 compensation line circuit (23) through a fourth blocking capacitor C4.
7. The Doherty-based power amplifying circuit with high gain and high final efficiency as claimed in claim 6, wherein: the peak power amplifying circuit further comprises a fifth blocking capacitor C5, a third RC circuit, a sixth blocking capacitor C6 and a second phase compensation line circuit (34), the first phase compensation line circuit (33) is connected with one end of a third input matching network (31) through a fifth blocking capacitor C5, the other end of the third input matching network (31) is connected with a grid electrode of a third field effect transistor Q3 through the third RC circuit, and the third output matching network (32) is connected with a second input end of the combiner through the sixth blocking capacitor C6 and the second phase compensation line circuit (34) in series.
8. The Doherty-based power amplifying circuit with high gain and high final stage efficiency according to any of claims 3-7, wherein: the grid and the drain of the first field effect transistor Q1, the grid and the drain of the second field effect transistor Q2 and the grid and the drain of the third field effect transistor Q3 are respectively connected with a bias circuit, the bias circuit comprises a plurality of capacitors and resistors, the resistors are connected with a power supply, and the resistors are grounded through the plurality of capacitors.
9. The Doherty high-gain high-final-stage-efficiency-based power amplification circuit of claim 8, wherein: the output end of the combiner is connected with the signal output end through a fourth output matching network (4).
10. The Doherty-based power amplifying circuit with high gain and high final efficiency as claimed in claim 9, wherein: the first output matching network (12) is connected with the input end of the power divider through a second DC blocking capacitor C2.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202220100102.0U CN216794940U (en) | 2022-01-13 | 2022-01-13 | Power amplification circuit based on Doherty high-gain high-final-stage efficiency |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202220100102.0U CN216794940U (en) | 2022-01-13 | 2022-01-13 | Power amplification circuit based on Doherty high-gain high-final-stage efficiency |
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