CN216774327U

CN216774327U - Battery protection chip and battery system

Info

Publication number: CN216774327U
Application number: CN202123051143.XU
Authority: CN
Inventors: 齐正坤; 罗丙寅; 尤勇
Original assignee: CRM ICBG Wuxi Co Ltd
Current assignee: CRM ICBG Wuxi Co Ltd
Priority date: 2021-12-07
Filing date: 2021-12-07
Publication date: 2022-06-17
Anticipated expiration: 2031-12-07

Abstract

The utility model provides a battery protection chip and a battery system, wherein the battery protection chip comprises: the discharge voltage limiting detection circuit is used for detecting a discharge driving signal output by a previous-stage battery protection chip, identifying the level of the discharge driving signal according to the current flow direction of the discharge detection signal, and reducing the high-low level conversion window voltage of the discharge driving signal; the charging voltage limiting detection circuit is used for detecting a charging driving signal output by a previous-stage battery protection chip, identifying the level of the charging driving signal according to the current flow direction of the charging detection signal, and reducing the high-low level conversion window voltage of the charging driving signal. The battery protection chip and the battery system provided by the utility model solve the problems that the cost is high in the scheme 1 and the resistance voltage division ratio is difficult to determine and the power consumption is large in the scheme 2 when the existing cascade battery protection chip is used for protecting the battery.

Description

Battery protection chip and battery system

Technical Field

The utility model belongs to the field of electronic circuit design, and particularly relates to a battery protection chip and a battery system.

Background

Lithium batteries are widely used in various electrical appliances, and since the problems of overcharge/overdischarge of voltage, over-high temperature, over-high current and the like may occur during the charging and discharging processes of the lithium batteries, a battery protection chip is required. The voltage of a single lithium battery is about 4V, and the damage or the service life of the battery can be shortened due to the overhigh or overlow voltage. When the working voltage of the electrical appliance is higher than 4V, a plurality of lithium batteries can be connected in series to increase the voltage (for example, when the working voltage of the electrical appliance is 16V, 4 lithium batteries are connected in series to reach the working voltage), and the series of batteries is called a battery pack (pack). However, since there may be an imbalance between the batteries, not only the total voltage of the battery pack but also the voltage of each battery is monitored.

FIG. 1 is a simplified circuit of a 4-section lithium battery protection chip, which is used for explaining the basic working principle of the protection chip and only comprises the battery overcharge/overdischarge protection function; the charging MOS tube comprises a charging MOS tube, a discharging MOS tube, a charging MOS tube, a discharging MOS tube, a charging MOS tube, a discharging driving port, a charging driving port, a discharging driving port and a charging driving port, wherein VCC is high potential of a power supply, VSS is low potential of the power supply, VC1, VC2, VC3 and VCC monitor battery voltage, the discharging driving port and the charging driving port, CDRV (charging driving port) are respectively connected to the discharging MOS tube, the discharging MOS tube and the charging MOS tube. When the monitored voltage of the battery is in a normal range, the circuit is in a normal working state, the output of the discharge driving port DDRV and the output of the charge driving port CDRV are both high potential, and the discharge MOS transistor DFET and the charge MOS transistor CFET are conducted. When a load (an electric appliance) is connected between the PCK + and the PCK-, the battery discharges; when any battery is monitored to be over-discharged and the voltage is too low, the circuit enters a low-voltage protection mode, the DDRV outputs low potential at the discharge driving port, the DFET of the discharge MOS tube is turned off, and the battery stops discharging. When a charger is connected between the PCK + and the PCK-, the battery is charged; when the situation that any battery is overcharged and the voltage is overhigh is monitored, the circuit enters a high-voltage protection mode, the CDRV at the charging driving end outputs low potential, the charging MOS tube CFET is turned off, and the battery stops charging. After the abnormal state occurs, the circuit can be recovered to the normal working mode only by waiting for the battery to recover to the normal voltage range.

In order to support higher operating voltages, it is sometimes necessary to cascade battery protection chips. Fig. 2 shows a battery pack comprising two 4 batteries connected in series for a total of 8 batteries. In order to support the cascade function, the chip is additionally provided with a discharge control port DCTL (discharge control) and a charge control port CCTL (charge control), and the following logic is realized through circuit design:

(1) if the discharging control port DCTL and the charging control port CCTL are input at high potential, the operation of the chip 1 is the same as that in fig. 1; only when the battery pack corresponding to the chip has overvoltage/undervoltage, the output of the CDRV/DDRV of the discharge driving port is changed into low potential.

(2) If the discharge control port DCTL input is low potential, the discharge drive port DDRV becomes low potential; if the charge control port CCTL input is low potential, the charge-driving port CDRV becomes low potential.

According to the logic, although the chip 2 in fig. 2 is not directly connected to the gates of the discharge MOS transistor DFET and the charge MOS transistor CFET, if an overvoltage/undervoltage is detected in the cell5-cell8, a signal for turning off the discharge MOS transistor DFET or the charge MOS transistor CFET can be transmitted through the chip 1 to achieve the purpose of protecting the battery, which is the working principle of battery protection chip cascade.

The MOSFET is a basic unit of the circuit, and the MOSFET process is different according to different circuit functions; in the case of power MOSFET, it needs to pass large current and bear high voltage V_GSAnd V_DS(e.g., V of 60V)_GS) Therefore, the thick gate oxide is adopted, the cost is high, and the area is large. And if the logic MOSFET is used, large current does not need to be passed, only relatively low voltage difference (such as voltage 1.2V and 0V) is needed to represent logic '1' and '0', thin gate oxide can be adopted, the cost is low, and the area is small. The main problems here are: when the chip 2 is used independently, the discharge driving port DDRV and the charge driving port CDRV are connected to an NMOS power tube on a drive charge-discharge line, so that the voltage difference between high and low potentials of the drive output is large; however, when the discharging driving port DDRV and the charging driving port CDRV of the chip 2 are to be input into the logic circuit of the chip 1 when used in cascade, a high voltage may break down the thin gate oxide MOSFET used in the logic circuit.

One existing scheme is: level signals of a discharge driving port DDRV and a charge driving port CDRV in the chip 2 are directly connected to corresponding logic circuits in the chip 1 without processing, and then a thick gate oxide MOSFET (as shown in fig. 3) is used in the logic circuit portion. However, this scheme has the disadvantage that it is costly to use thick gate oxide MOSFETs.

Another existing scheme is as follows: the high input voltage is divided by the resistor to lower the potential input to the logic circuit, so that it is not necessary to use a thick gate oxide MOSFET in the logic circuit (as shown in fig. 4). However, the disadvantages of this solution are: 1) the number of battery sections connected in series with the power protection chip is not fixed, and the potential of the battery is not fixed, so that the output potential when the discharge driving port DDRV and the charge driving port CDRV are high is not fixed, and the ratio of resistance voltage division is difficult to accurately determine; 2) a leakage channel from the discharging driving port DDRV to the ground and from the charging driving port CDRV to the ground is added, and the resistance is limited by the chip area and cannot be made to be large, so that the current is large, and the power consumption is high.

SUMMERY OF THE UTILITY MODEL

In view of the above drawbacks of the prior art, an object of the present invention is to provide a battery protection chip and a battery system, which are used to solve the problem that the cost is high in the case of performing battery protection on the existing cascade battery protection chip in scheme 1, and the problem that the resistance voltage division ratio and the power consumption are not easy to determine in scheme 2.

To achieve the above and other related objects, the present invention provides a battery protection chip, which at least includes: a discharge voltage limit detection circuit and a charge voltage limit detection circuit, wherein,

the discharge voltage limiting detection circuit is used for detecting a discharge driving signal output by a previous-stage battery protection chip, identifying the level of the discharge driving signal according to the current flow direction of the discharge detection signal, and reducing the high-low level conversion window voltage of the discharge driving signal;

the charging voltage-limiting detection circuit is used for detecting a charging driving signal output by a previous-stage battery protection chip, identifying the level of the charging driving signal according to the current flow direction of the charging detection signal, and reducing the high-low level conversion window voltage of the charging driving signal.

Optionally, the discharge voltage limit detection circuit and the charge voltage limit detection circuit have the same circuit structure, and at least include: a detection module, a clamping module and an identification voltage limiting module, wherein,

the detection module is used for detecting a corresponding driving signal output by the previous-stage battery protection chip and generating a corresponding detection signal;

the clamping module is connected between a power supply end of the chip and the output end of the detection module and is used for carrying out bidirectional voltage clamping according to the current flow direction of a corresponding detection signal so that the voltage of a current inflow port is higher than that of a current outflow port by a clamping voltage;

the identification voltage limiting module is connected with the output end of the clamping module and used for identifying the level of the corresponding driving signal according to the output voltage of the clamping module and reducing the high-low level conversion window voltage of the corresponding driving signal based on the reference voltage.

Optionally, the method further comprises: a bias voltage generation module and/or a deglitch module; the bias voltage generation module is used for providing bias voltage for the identification voltage limiting module; the anti-spike pulse module is connected with the output end of the identification voltage limiting module and is used for filtering the spike voltage.

Optionally, the detection module includes: and the first end of the current-limiting resistor is connected with a corresponding driving signal output by the previous-stage battery protection chip, and the second end of the current-limiting resistor is used as the output end of the detection module.

Optionally, the detection module further includes: and the short-circuit protection resistor is connected in series with the second end of the current-limiting resistor.

Optionally, the clamping module comprises: a first diode and a second diode; the anode of the first diode is connected with the cathode of the second diode and the power supply end of the chip, and the cathode of the first diode is connected with the anode of the second diode and the output end of the detection module and serves as the output end of the clamping module.

Optionally, the clamping module comprises: at least one first PMOS tube, wherein,

when the number of the first PMOS tubes is 1, the grid electrode of each first PMOS tube is connected with the drain electrode of each first PMOS tube and the power supply end of the chip, and the source electrode of each first PMOS tube is connected with the output end of the detection module and serves as the output end of the clamping module;

when the number of the first PMOS tubes is more than or equal to 2, the grid electrode of each first PMOS tube is connected with the drain electrode of the first PMOS tube, the source electrode of the previous first PMOS tube is connected with the drain electrode of the next first PMOS tube, the drain electrode of the first PMOS tube is connected with the power supply end of the chip, and the source electrode of the last first PMOS tube is connected with the output end of the detection module and serves as the output end of the clamping module.

Optionally, the identification voltage limiting module comprises: the second PMOS tube, the first resistor, the first NMOS tube and the first current source; the grid electrode of the second PMOS tube is connected with bias voltage, the source electrode of the second PMOS tube is connected with the output end of the clamping module, and the drain electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube through the first resistor; the grid electrode of the first NMOS tube is connected with a reference voltage, and the source electrode of the first NMOS tube is connected with the reference end of the chip through the first current source and serves as the output end of the identification voltage limiting module.

Optionally, the bias voltage generating module includes: the third PMOS tube, the second resistor and the second current source; the grid electrode of the third PMOS tube is connected with the drain electrode of the third PMOS tube, the source electrode of the third PMOS tube is connected with the power supply end of the chip, and the drain electrode of the third PMOS tube is connected with the first end of the second resistor; and the second end of the second resistor is connected with a chip reference end through the second current source and is used as the output end of the bias voltage generation module.

Optionally, the battery protection chip further includes: a discharge logic circuit, a charge logic circuit, a discharge driving circuit and a charge driving circuit, wherein,

the discharge logic circuit is connected with the output end of the discharge voltage limiting detection circuit and is used for generating corresponding control logic according to the discharge monitoring result of the battery protection chip when the discharge voltage limiting detection circuit outputs a high level and generating control logic with abnormal discharge when the discharge voltage limiting detection circuit outputs a low level;

the discharge driving circuit is connected with the output end of the discharge logic circuit and used for generating a corresponding discharge driving signal according to the control logic output by the discharge logic circuit;

the charging logic circuit is connected with the output end of the charging voltage limiting detection circuit and is used for generating corresponding control logic according to a charging monitoring result of the battery protection chip when the charging voltage limiting detection circuit outputs a high level and generating abnormal charging control logic when the charging voltage limiting detection circuit outputs a low level;

the charging driving circuit is connected with the output end of the charging logic circuit and used for generating corresponding charging driving signals according to the control logic output by the charging logic circuit.

Optionally, the discharge driving circuit and the charge driving circuit are both implemented by an open-drain structure or a push-pull structure.

The present invention also provides a battery system, including: the battery protection device comprises at least two battery packs and at least two battery protection chips, wherein the battery protection chips correspond to the battery packs one to one; the discharging driving signal output by the last stage battery protection chip is connected to the discharging voltage limiting detection circuit of the next stage battery protection chip, the charging driving signal output by the last stage battery protection chip is connected to the charging voltage limiting detection circuit of the next stage battery protection chip, the discharging driving signal output by the last stage battery protection chip controls the discharging MOS tube, and the charging driving signal output by the last stage battery protection chip controls the charging MOS tube.

As described above, according to the battery protection chip and the battery system of the present invention, by designing the discharge voltage limit detection circuit and the charge voltage limit detection circuit, the high-low level conversion window voltage of the previous stage discharge/charge driving signal is reduced, so that the chip is suitable for the logic circuit formed by the thin gate oxygen MOSFET device, thereby reducing the chip cost. In addition, the level of the discharging/charging driving signal of the upper stage is judged according to the current flow direction, and the discharging/charging driving signal is sensitive to the current flow direction and insensitive to the size, so that the discharging/charging driving circuit can normally work in a wider voltage range, and the problem of resistance voltage division is avoided; in addition, the current is controlled through the MOSFET, the circuit area is small, the current is small, and the power consumption is low.

Drawings

Fig. 1 is a schematic circuit diagram illustrating a conventional single battery protection chip during battery protection.

Fig. 2 is a schematic circuit diagram illustrating a conventional cascade battery protection chip for battery protection.

Fig. 3 is a schematic diagram illustrating a cascade transmission manner of the driving signal in the battery protection chip shown in fig. 2.

Fig. 4 is a schematic diagram illustrating another cascade transmission manner of the driving signal in the battery protection chip shown in fig. 2.

Fig. 5 is a schematic diagram of a discharge voltage limit detection circuit in the battery protection chip according to the present invention.

FIG. 6 is a schematic diagram of a charging voltage limiting detection circuit in the battery protection chip according to the present invention

Fig. 7 is a first schematic diagram of a clamp circuit in the battery protection chip according to the present invention.

Fig. 8 is a second schematic diagram of a clamping circuit in the battery protection chip according to the present invention.

Fig. 9 is a third schematic diagram of a clamping circuit in the battery protection chip according to the present invention.

Fig. 10 is a waveform diagram of related signals in the battery protection chip according to the present invention.

Description of the element reference numerals

10 battery protection chip

11 discharge voltage limiting detection circuit

12 charging voltage-limiting detection circuit

111. 121 detection module

112. 122 clamp module

113. 123 identification voltage limiting module

114. 124 bias voltage generation module

115. 125 deglitch module

13 discharge logic circuit

14 charging logic circuit

15 discharge driving circuit

16 charging driving circuit

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The utility model is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 5-10. It should be noted that the drawings provided in the present embodiment are only for schematically illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.

As shown in fig. 5 and 6, the present embodiment provides a battery protection chip, where the battery protection chip 10 at least includes: a discharge voltage limit detection circuit 11 and a charge voltage limit detection circuit 12. Further, the battery protection chip 10 further includes: a discharge logic circuit 13, a charge logic circuit 14, a discharge drive circuit 15, and a charge drive circuit 16. It should be noted that the battery protection chip 10 described in this embodiment is suitable for the case of cascading a plurality of chips, and certainly, the same applies to the case of a single chip, but the superiority of this solution cannot be demonstrated.

As shown in fig. 5, the discharge voltage-limiting detection circuit 11 is configured to detect a previous-stage discharge driving signal output by a previous-stage battery protection chip, identify a level of the previous-stage discharge driving signal according to a current flow direction of the discharge detection signal, and reduce a high-low level conversion window voltage of the previous-stage discharge driving signal, so that the reduced level of the previous-stage discharge driving signal is suitable for driving a thin-gate oxygen MOSFET device, which is beneficial to reducing chip cost. In this embodiment, the discharge voltage limiting detection circuit 11 identifies the level of the previous stage discharge driving signal through the current flow direction of the discharge detection signal, is only sensitive to the current flow direction and is not sensitive to the magnitude, avoids the problem of resistance voltage division, and has low power consumption.

Specifically, the discharge voltage limit detection circuit 11 at least includes: the detection module 111, the clamping module 112, and the identification voltage limiting module 113. Further, the discharge voltage limit detection circuit 11 further includes a bias voltage generation module 114 and/or a deglitch module 115. In this embodiment, the discharge voltage limit detection circuit 11 includes: detection module 111, clamping module 112, identification voltage limiting module 113, bias voltage generation module 114, and deglitch module 115.

The detection module 111 is configured to detect the previous stage discharge driving signal and generate the discharge detection signal.

As an example, the detection module 111 comprises: a current limiting resistor Rcl 1; a first end of the current limiting resistor Rcl1 is connected to the previous stage discharge driving signal, and a second end of the current limiting resistor Rcl1 is used as an output end of the detection module 111 to output the discharge detection signal. Further, the detection module 111 further includes: and the short-circuit protection resistor Rsp1 is connected in series with the second end of the current-limiting resistor Rcl1 and is used for preventing the chip from being damaged by overcurrent when the current-limiting resistor Rcl1 is short-circuited. It should be noted that, when the detection module 111 includes both the current-limiting resistor Rcl1 and the short-circuit protection resistor Rsp1, the first end of the short-circuit protection resistor Rsp1 is connected to the second end of the current-limiting resistor Rcl1, and the second end of the short-circuit protection resistor Rsp1 serves as the output end of the detection module 111, at this time, the second end of the current-limiting resistor Rcl1 will no longer serve as the output end of the detection module 111. In practical applications, the current limiting resistor Rcl1 may be disposed inside the battery protection chip 10, or may be disposed outside the battery protection chip 10, which has no influence on the present embodiment; optionally, the current limiting resistor Rcl1 is disposed outside the battery protection chip 10 to adjust the resistance.

The clamping module 112 is connected between the chip power terminal VCC and the output terminal of the detection module 111, and is configured to perform bidirectional voltage clamping according to the current flow direction of the discharge detection signal, so that the voltage of the current flowing into the port is higher than the voltage of the current flowing out of the port by a clamping voltage Vclamp.

In this embodiment, the current magnitude of the discharge detection signal corresponds to the level of the previous stage discharge driving signal, and determines the current direction in the clamping module 112, so as to obtain a voltage value related to the level of the previous stage discharge driving signal at an output end (i.e., at the node a 11); if the previous stage discharge driving signal is at a low level, the current of the discharge detection signal is less than I11 or even 0, and at this time, the current in the clamping module 112 flows from VCC to a11, and the voltage at the node a11 is clamped at VCC-Vclamp; if the previous stage discharge driving signal is at a high level, the current of the discharge detection signal is greater than I11, and at this time, the current flowing in the clamping module 112 is a11 to VCC, then the voltage at the node a11 is clamped at VCC + Vclamp.

As an example, the clamping module 112 includes: a first diode D11 and a second diode D21; the anode of the first diode D11 is connected to the cathode of the second diode D21 and the chip power terminal VCC, and the cathode of the first diode D11 is connected to the anode of the second diode D21 and the output terminal of the detection module 111, and is used as the output terminal of the clamping module 112 (as shown in fig. 7). This example utilizes two diodes to achieve a bi-directional voltage clamp and causes the current flowing into the port to be one diode's turn-on voltage higher than the voltage of the current flowing out of the port.

As another example, the clamping module 112 includes: at least one first PMOS transistor P11; when the number of the first PMOS transistors P11 is 1, the gate of the first PMOS transistor P11 is connected to the drain thereof and the chip power terminal VCC, and the source thereof is connected to the output terminal of the detection module 111 and serves as the output terminal of the clamping module 112 (as shown in fig. 8); when the number of the first PMOS transistors P11 is greater than or equal to 2, the gate of each first PMOS transistor P11 is connected to the drain thereof, the source of the previous first PMOS transistor P11 is connected to the drain of the next first PMOS transistor P11, the drain of the first PMOS transistor P11 is connected to the chip power source VCC, and the source of the last first PMOS transistor P11 is connected to the output terminal of the detection module 111 and serves as the output terminal of the clamp module 112 (as shown in fig. 9). In this example, diode-connected PMOS is used for bidirectional voltage clamping, in order to obtain a higher clamping voltage Vclamp, the PMOS transistor in fig. 8 may be implemented by using a thick-gate oxide MOSFET device, and certainly, as shown in fig. 9, may also be implemented by using a plurality of thin-gate oxide MOSFET devices connected in series (for example, to obtain a clamping voltage of 2V, a series structure of 3 thin-gate oxide MOSFET devices may be used, and at a low current, a voltage drop from VCC to a11 is an on-state voltage of 3 parasitic diodes, which is about 2.1V, and a voltage drop from a11 to VCC is 3 × Vth, which is also about 2.1V, where Vth is an on-state threshold of the thin-gate oxide MOSFET device).

The identification voltage limiting module 113 is connected to the output end of the clamping module 112, and is configured to identify the level of the previous stage discharge driving signal according to the magnitude of the output voltage of the clamping module 112, and reduce the high-low level transition window voltage of the previous stage discharge driving signal based on the reference voltage Vref 1.

By way of example, the identification voltage limiting module 113 includes: a second PMOS transistor P21, a first resistor R11, a first NMOS transistor N11, and a first current source I11; the gate of the second PMOS transistor P21 is connected to a bias voltage, the source is connected to the output end of the clamping module 112, and the drain is connected to the drain of the first NMOS transistor N11 through the first resistor R11; the gate of the first NMOS transistor N11 is connected to a reference voltage Vref1, and the source is connected to a chip reference terminal VSS through the first current source I11, and is used as the output terminal of the identification voltage limiting module 113. Optionally, the current in the first current source I11 is provided by a current mirror.

In this embodiment, when the voltage at the node a11 is VCC-Vclamp, the second PMOS transistor P21 is turned off, and at this time, the first current source I11 still tries to draw current and pull the voltage at the node a21 down to 0V, that is, the identification voltage-limiting module 113 identifies that the previous stage discharge driving signal is at a low level and outputs the low level; when the voltage at the node a11 is VCC + Vclamp, the second PMOS transistor P21 is turned on, the first NMOS transistor N11 is turned on under the control of the reference voltage Vref1, and the voltage at the node a21 is raised to Vref1-Vth _ N11, where Vth _ N11 is the gate-source voltage of the first NMOS transistor N11 when the drain-source current of the first NMOS transistor N11 is equal to I11, that is, the identification voltage limiting module 113 identifies that the previous stage discharge driving signal is at a high level, and reduces the high level by using the reference voltage Vref1, so as to reduce the high-low level conversion window voltage of the previous stage discharge driving signal to a high-low level conversion window voltage suitable for driving a thin gate oxide MOSFET device; wherein, the reference voltage Vref1 is Vdda + Vth _ N11, and Vdda is high level suitable for driving the thin gate oxide MOSFET.

The bias voltage generating module 114 is configured to provide a bias voltage for the identification voltage limiting module 113, so that the second PMOS transistor P21 in the identification voltage limiting module 113 is turned off when the voltage at the node a11 is VCC-Vclamp, and is turned on when the voltage at the node a11 is VCC + Vclamp.

As an example, the bias voltage generating module 114 includes: a third PMOS transistor P31, a second resistor R21, and a second current source I21; the grid electrode of the third PMOS tube P31 is connected with the drain electrode thereof, the source electrode is connected with a chip power supply end VCC, and the drain electrode is connected with the first end of the second resistor R21; the second terminal of the second resistor R21 is connected to the chip reference terminal VSS through the second current source I21, and is used as the output terminal of the bias voltage generating module 114 for outputting the bias voltage. Optionally, the current in the second current source I21 is provided by a current mirror.

In this embodiment, the current provided by the second current source I21 passes through the third PMOS transistor P31 and the second resistor R21, and a voltage drop with a magnitude of | Vgs _ P31| + I21 × R21 is generated at a node a01 and is output as the bias voltage, where Vgs _ P31 is a gate-source voltage of the third PMOS transistor when a drain-source current of the third PMOS transistor is equal to I21, I21 is the current provided by the second current source, and R21 is a resistance value of the second resistor; by adjusting Vgs _ P31, I21, and R21, the bias voltage is made to satisfy: when the voltage at the node A11 is VCC-Vclamp, the second PMOS tube P21 is turned off, and when the voltage at the node A11 is VCC + Vclamp, the second PMOS tube P21 is turned on.

The anti-spike pulse module 115 is connected to the output end of the identification voltage limiting module 113, and is used for filtering out spike voltage and preventing false triggering.

The anti-spike module 115 is composed of a capacitor and a delay circuit, the capacitor has a function of filtering and stabilizing voltage, and the delay circuit is combined to prevent false triggering caused by a spike voltage. It should be noted that any circuit comprising a capacitor and a delay circuit and having a function of filtering a glitch voltage is suitable for this embodiment.

As shown in fig. 6, the charging voltage-limiting detection circuit 12 is configured to detect a previous-stage charging driving signal output by a previous-stage battery protection chip, identify a level of the previous-stage charging driving signal according to a current flow direction of the charging detection signal, and reduce a high-low level conversion window voltage of the previous-stage charging driving signal, so that the reduced level of the previous-stage charging driving signal is suitable for driving a thin-gate oxygen MOSFET device, which is beneficial to reducing chip cost. In this embodiment, the charging voltage-limiting detection circuit 12 identifies the level of the previous charging driving signal through the current flow direction of the charging detection signal, is only sensitive to the current flow direction and is not sensitive to the magnitude, avoids the problem of resistance voltage division, and has low power consumption.

Specifically, the charging voltage limiting detection circuit 12 at least includes: a detection module 121, a clamping module 122, and an identification voltage limiting module 123. Further, the charge voltage limit detection circuit 12 further includes a bias voltage generation module 124 and/or a deglitch module 125. In this embodiment, the charging voltage limiting detection circuit 12 includes: the system comprises a detection module 121, a clamping module 122, an identification voltage limiting module 123, a bias voltage generation module 124 and a deglitch module 125.

The detection module 121 is configured to detect the previous-stage charging driving signal and generate the charging detection signal.

As an example, the detection module 121 includes: a current limiting resistor Rcl 2; a first end of the current limiting resistor Rcl2 is connected to the previous stage charging driving signal, and a second end of the current limiting resistor Rcl2 is used as an output end of the detection module 121 to output the charging detection signal. Further, the detection module 121 further includes: and the short-circuit protection resistor Rsp2 is connected in series with the second end of the current-limiting resistor Rcl2 and is used for preventing the chip from being damaged by overcurrent when the current-limiting resistor Rcl2 is short-circuited. It should be noted that, when the detection module 121 includes both the current limiting resistor Rcl2 and the short-circuit protection resistor Rsp2, the first end of the short-circuit protection resistor Rsp2 is connected to the second end of the current limiting resistor Rcl2, and the second end of the short-circuit protection resistor Rsp2 serves as the output end of the detection module 121, at this time, the second end of the current limiting resistor Rcl2 will no longer serve as the output end of the detection module 121. In practical applications, the current limiting resistor Rcl2 may be disposed inside the battery protection chip 10, or may be disposed outside the battery protection chip 10, which has no influence on the present embodiment; optionally, the current limiting resistor Rcl2 is disposed outside the battery protection chip 10 to adjust the resistance.

The clamping module 122 is connected between a chip power supply terminal VCC and the output terminal of the detection module 121, and is configured to perform bidirectional voltage clamping according to the current flow direction of the charging detection signal, so that the voltage of the current flowing into the port is higher than the voltage of the current flowing out of the port by a clamping voltage Vclamp.

In this embodiment, the current magnitude of the charging detection signal corresponds to the level of the previous charging driving signal, and also determines the current direction of the clamping module 122, so as to obtain a voltage value at the output end (i.e. at the node a 12) related to the level of the previous charging driving signal; if the previous stage charge driving signal is at a low level, the current of the charge detection signal is less than I12 or even 0, and at this time, the current in the clamping module 122 flows from VCC to a12, then the voltage at the node a12 is clamped at VCC-Vclamp; if the previous stage charge driving signal is at a high level, the current of the charge detection signal is greater than I12, and at this time, the current in the clamping module 122 flows from a12 to VCC, then the voltage at the node a12 is clamped at VCC + Vclamp.

As an example, the clamping module 122 includes: a first diode D12 and a second diode D22; the anode of the first diode D12 is connected to the cathode of the second diode D22 and the chip power terminal VCC, and the cathode of the first diode D12 is connected to the anode of the second diode D22 and the output terminal of the detection module 121, and is used as the output terminal of the clamping module 122 (as shown in fig. 7). This example utilizes two diodes to achieve a bi-directional voltage clamp and causes the current flow into the port to be one diode conduction voltage higher than the voltage of the current flow out of the port.

As another example, the clamping module 122 includes: at least one first PMOS transistor P12; when the number of the first PMOS transistors P12 is 1, the gate of the first PMOS transistor P12 is connected to the drain thereof and the chip power terminal VCC, and the source thereof is connected to the output terminal of the detection module 121 and serves as the output terminal of the clamping module 122 (as shown in fig. 8); when the number of the first PMOS transistors P12 is greater than or equal to 2, the gate of each first PMOS transistor P12 is connected to the drain thereof, the source of the previous first PMOS transistor P12 is connected to the drain of the next first PMOS transistor P12, the drain of the first PMOS transistor P12 is connected to the chip power source VCC, and the source of the last first PMOS transistor P12 is connected to the output terminal of the detection module 121 and serves as the output terminal of the clamp module 122 (as shown in fig. 9). In this example, diode-connected PMOS is used for bidirectional voltage clamping, in order to obtain a higher clamping voltage Vclamp, the PMOS transistor in fig. 8 may be implemented by using a thick-gate oxide MOSFET device, and certainly, as shown in fig. 9, may also be implemented by using a plurality of thin-gate oxide MOSFET devices connected in series (for example, to obtain a clamping voltage of 2V, a series structure of 3 thin-gate oxide MOSFET devices may be used, and at a low current, a voltage drop from VCC to a12 is an on-state voltage of 3 parasitic diodes, which is about 2.1V, and a voltage drop from a12 to VCC is 3 × Vth, which is also about 2.1V, where Vth is an on-state threshold of the thin-gate oxide MOSFET device).

The identification voltage limiting module 123 is connected to the output end of the clamping module 122, and is configured to identify the level of the previous stage charging driving signal according to the magnitude of the output voltage of the clamping module 122, and reduce the high-low level transition window voltage of the previous stage charging driving signal based on the reference voltage Vref 2.

By way of example, the identification voltage limiting module 123 includes: a second PMOS transistor P22, a first resistor R12, a first NMOS transistor N12, and a first current source I12; the gate of the second PMOS transistor P22 is connected to a bias voltage, the source is connected to the output terminal of the clamp module 122, and the drain is connected to the drain of the first NMOS transistor N12 through the first resistor R12; the gate of the first NMOS transistor N12 is connected to a reference voltage Vref2, and the source is connected to a chip reference terminal VSS through the first current source I12 and serves as the output terminal of the identification voltage limiting module 123. Optionally, the current in the first current source I12 is provided by a current mirror.

In this embodiment, when the voltage at the node a12 is VCC-Vclamp, the second PMOS transistor P22 is turned off, and at this time, the first current source I12 still tries to draw current and pull the voltage at the node a22 down to 0V, that is, the identification voltage-limiting module 123 identifies that the previous stage charging driving signal is at a low level and performs low level output; when the voltage at the node a12 is VCC + Vclamp, the second PMOS transistor P22 is turned on, the first NMOS transistor N12 is turned on under the control of the reference voltage Vref2, and the voltage at the node a22 is raised to Vref2-Vth _ N12, where Vth _ N12 is the gate-source voltage of the first NMOS transistor N12 when the drain-source current of the first NMOS transistor N12 is equal to I12, that is, the identification voltage limiting module 123 identifies that the previous-stage charging driving signal is at a high level, and reduces the high level by using the reference voltage Vref2, so as to reduce the high-low level conversion window voltage of the previous-stage charging driving signal to a high-low level conversion window voltage suitable for driving a thin-gate oxide MOSFET device; the reference voltage Vref2 is Vdda + Vth _ N12, and Vdda is high level suitable for driving the thin gate oxide MOSFET.

The bias voltage generation module 124 is configured to provide a bias voltage for the identification voltage limiting module 123, so that the second PMOS transistor P22 in the identification voltage limiting module 123 is turned off when the voltage at the node a12 is VCC-Vclamp, and is turned on when the voltage at the node a12 is VCC + Vclamp.

As an example, the bias voltage generation module 124 includes: a third PMOS transistor P32, a second resistor R22, and a second current source I22; the grid electrode of the third PMOS tube P32 is connected with the drain electrode thereof, the source electrode is connected with a chip power supply end VCC, and the drain electrode is connected with the first end of the second resistor R22; the second terminal of the second resistor R22 is connected to the chip reference terminal VSS through the second current source I22, and is used as the output terminal of the bias voltage generating module 124 for outputting the bias voltage. Optionally, the current in the second current source I22 is provided by a current mirror.

In this embodiment, the current provided by the second current source I22 passes through the third PMOS transistor P32 and the second resistor R22, and a voltage drop with a magnitude of | Vgs _ P32| + I22 × R22 is generated at a node a02 and is output as the bias voltage, where Vgs _ P32 is a gate-source voltage of the third PMOS transistor when a drain-source current of the third PMOS transistor is equal to I22, I22 is the current provided by the second current source, and R22 is a resistance value of the second resistor; by adjusting Vgs _ P32, I22, and R22, the bias voltage is made to satisfy: when the voltage at the node A12 is VCC-Vclamp, the second PMOS tube P22 is turned off, and when the voltage at the node A12 is VCC + Vclamp, the second PMOS tube P22 is turned on.

The anti-spike module 125 is connected to the output end of the identification voltage limiting module 123, and is used for filtering the spike voltage and preventing false triggering.

The anti-spike module 125 is composed of a capacitor and a delay circuit, the capacitor has a function of filtering and stabilizing voltage, and the delay circuit is combined to prevent false triggering caused by a spike voltage. It should be noted that any circuit composed of a capacitor and a delay circuit and having a function of filtering the glitch voltage is suitable for this embodiment.

The discharge logic circuit 13 is connected to the output end of the discharge voltage limiting detection circuit 11, and is configured to generate a corresponding control logic according to a discharge monitoring result of the battery protection chip when the discharge voltage limiting detection circuit 11 outputs a high level, and generate a control logic for abnormal discharge when the discharge voltage limiting detection circuit 11 outputs a low level.

In this embodiment, the discharge voltage limiting detection circuit 11 outputs a high level, that is, a previous-stage discharge driving signal output by a previous-stage battery protection chip is a high level, that is, the previous-stage battery protection chip monitors that discharge is normal, at this time, the discharge logic circuit 13 generates a corresponding control logic according to a monitoring result of the current-stage battery protection chip, if the current-stage battery protection chip monitors that discharge is abnormal, the discharge logic circuit 13 generates a control logic of discharge abnormality, otherwise, a control logic of discharge normal is generated; the discharge voltage limiting detection circuit 11 outputs a low level, that is, the previous-stage discharge driving signal output by the previous-stage battery protection chip is a low level, that is, the previous-stage battery protection chip monitors discharge abnormality, and at this time, the discharge logic circuit 13 directly generates a control logic of discharge abnormality.

The charging logic circuit 14 is connected to the output end of the charging voltage limiting detection circuit 12, and is configured to generate a corresponding control logic according to a charging monitoring result of the battery protection chip when the charging voltage limiting detection circuit 12 outputs a high level, and generate a control logic of charging abnormality when the charging voltage limiting detection circuit 12 outputs a low level.

In this embodiment, the charging voltage-limiting detection circuit 12 outputs a high level, that is, the previous-stage charging driving signal output by the previous-stage battery protection chip is a high level, that is, the previous-stage battery protection chip monitors normal charging, at this time, the charging logic circuit 14 generates a corresponding control logic according to the monitoring result of the current-stage battery protection chip, if the current-stage battery protection chip monitors abnormal charging, the charging logic circuit 14 generates a control logic of abnormal charging, otherwise, a control logic of normal charging is generated; the charging voltage-limiting detection circuit 12 outputs a low level, that is, the previous-stage charging driving signal output by the previous-stage battery protection chip is a low level, that is, the previous-stage battery protection chip monitors charging abnormality, and at this time, the charging logic circuit 14 directly generates a control logic of the charging abnormality.

The discharge driving circuit 15 is connected to the output end of the discharge logic circuit 13, and is configured to generate a corresponding current-stage discharge driving signal according to the control logic output by the discharge logic circuit 13.

In this embodiment, when the discharge logic circuit 13 generates a control logic of abnormal discharge, the discharge driving circuit 15 generates a low-level present-stage discharge driving signal to control the discharge MOS transistor to turn off; when the discharge logic circuit 13 generates a control logic of normal discharge, the discharge driving circuit 15 generates a high-level present-stage discharge driving signal to control the conduction of the discharge MOS transistor.

As an example, the discharge driving circuit 15 is implemented by an open-drain structure or a push-pull structure; for the open-drain structure, when the chip is subjected to abnormal discharge protection, no current flows out of the circuit, and when the chip works normally, a large current flows out of the circuit; for the push-pull structure, when the chip has abnormal discharge protection, a small current flows out of the circuit, and when the chip works normally, a large current flows out of the circuit; the small current is a current smaller than I11, and the large current is a current larger than I11. It should be noted that both the open-drain configuration and the push-pull configuration are well known in the art, and therefore, a detailed description thereof is omitted here.

The charging driving circuit 16 is connected to the output end of the charging logic circuit 14, and is configured to generate a corresponding current-stage charging driving signal according to the control logic output by the charging logic circuit 14.

In this embodiment, when the charging logic circuit 14 generates a control logic of charging abnormality, the charging driving circuit 16 generates a low-level present-stage charging driving signal to control the charging MOS transistor to turn off; when the charging logic circuit 14 generates a control logic of normal charging, the charging driving circuit 16 generates a high-level present-stage charging driving signal to control the conduction of the charging MOS.

As an example, the charge driving circuit 16 is implemented in an open-drain structure or a push-pull structure; for the open-drain structure, when the chip is subjected to abnormal charging protection, no current flows out of the circuit, and when the chip works normally, a large current flows out of the circuit; for the push-pull structure, when the chip is subjected to abnormal charging protection, a small current flows out of the circuit, and when the chip works normally, a large current flows out of the circuit; the small current is a current smaller than I12, and the large current is a current larger than I12. It should be noted that both the open-drain configuration and the push-pull configuration are well known in the art, and therefore, a detailed description thereof is omitted here.

Correspondingly, this embodiment also provides a battery system, the battery system includes: the battery protection device comprises at least two battery packs and at least two battery protection chips 10, wherein the battery protection chips 10 correspond to the battery packs one to one; the discharging driving signal output by the last stage battery protection chip is connected to the discharging voltage limiting detection circuit 11 of the next stage battery protection chip, the charging driving signal output by the last stage battery protection chip is connected to the charging voltage limiting detection circuit 12 of the next stage battery protection chip, the discharging driving signal output by the last stage battery protection chip controls the discharging MOS tube, and the charging driving signal output by the last stage battery protection chip controls the charging MOS tube.

The operation principle of the battery system according to the present embodiment will be described with reference to the cascade structure shown in fig. 5 and 6, and since the principle of the discharging process and the charging process is the same, the discharging process will be described only as an example.

As shown in fig. 5, two battery packs are cascaded, and two battery protection chips are cascaded and connected to the corresponding battery packs; the battery pack voltages Vpack1 and Vpack2 both range from 18V to 40V, and the chip power supply terminal voltage VCC1 of the battery protection chip 1 and the chip reference terminal voltage VSS2 of the battery protection chip 2 are at the same potential. For the battery protection chip 2, the low potential of the discharge driving signal output by the discharge driving circuit is VSS2, the high potential is VSS2+ Vhigh, Vhigh ≈ Vpack 2; the difference of the discharge driving signal potential can reach 40V, so that the working range of the ultrathin gate oxide MOSFET device is far (generally about 5V).

For the discharge driving circuit, the structure is an open-drain structure:

when the battery protection chip 2 is abnormal in discharge, the current source of the discharge driving circuit is closed, and no current is output from the battery protection chip 2; since there is a current I11 in the battery protection chip 1, the current can only flow from VCC1, i.e. from left to right through the clamping module 112, and at this time, the potential at the node A11 is VCC1-Vclamp, the second PMOS transistor P21 is turned off, the first current source I11 still tries to draw current, and pulls the voltage at the node A21 down to 0V (as shown in FIG. 10). At this time, the discharge logic circuit 13 directly generates a control logic of discharge abnormality, and the discharge driving signal 15 generates a low-level discharge driving signal to control the discharge MOS transistor to be turned off, thereby realizing discharge abnormality protection.

When the battery protection chip 2 monitors that the discharge is normal, a current output larger than I11 exists in the discharge driving circuit, and at this time, a current flows through the clamping module 112 from right to left, the potential at the node a11 is VCC1+ Vclamp, the second PMOS transistor P21 is turned on, and the voltage at the node a21 is raised to Vref1-Vth _ N11, that is, Vdda (as shown in fig. 10) by using the first NMOS transistor N11. At this time, the discharge logic circuit 13 generates a corresponding control logic according to the monitoring result of the battery protection chip 1, and the discharge driving signal 15 generates a corresponding discharge driving signal according to the control logic of the discharge logic circuit 13 to control the discharge MOS transistor to be turned on or off.

The discharge driving circuit has a push-pull structure:

when the battery protection chip 2 has abnormal discharge, the discharge driving circuit has a current output smaller than I11, and at this time, a current flows through the clamping module 112 from left to right, the potential at the node a11 is VCC1-Vclamp, the second PMOS transistor P21 is turned off, the first current source I11 still tries to draw a current, and the voltage at the node a21 is pulled down to 0V (as shown in fig. 10). At this time, the discharge logic circuit 13 directly generates a control logic of discharge abnormality, and the discharge driving signal 15 generates a low-level discharge driving signal to control the discharge MOS transistor to be turned off, thereby realizing discharge abnormality protection.

Correspondingly, the present embodiment further provides a method for implementing battery protection by cascading battery protection chips, where the method includes:

1) the battery protection chip monitors the battery voltage of each battery in the corresponding battery pack in the charging and discharging process. It should be noted that the battery voltage monitoring by using the battery protection chip is a well-known technique in the art, and is not described herein.

2) The next-stage battery protection chip detects the previous-stage driving signal output by the previous-stage battery protection chip, identifies the level of the previous-stage driving signal according to the current flow direction of the detection signal, and reduces the high-low level conversion window voltage of the previous-stage driving signal, so that the next-stage battery protection chip is suitable for driving a thin gate oxide MOSFET device.

In particular, the circuit shown in fig. 5 and 6 can be used for implementation; when the discharging/charging driving signal of the previous stage is at a low level, the current of the discharging/charging detection signal is less than I11/I12, at this time, a current flows through the clamping module 112/122 from left to right, the voltage at the node a11/a12 is VCC-Vclamp, the second PMOS transistor P21/P22 is turned off, the first current source I11/I12 tries to draw a current, and pulls the voltage at the node a21/a22 down to 0V; when the discharging/charging driving signal of the previous stage is at a high level, the current of the discharging/charging detection signal is greater than I11/I12, at this time, a current from right to left flows through the clamping module 112/122, the voltage at the node a11/a12 is VCC + Vclamp, the second PMOS transistor P21/P22 is turned on, and the voltage at the node a21/a22 is raised to Vref1-Vth _ N11, that is, Vdda, by using the first NMOS transistor N11.

3) And the next-stage battery protection chip generates a next-stage driving signal according to the level of the reduced signal and the monitoring result of the reduced signal.

Specifically, when the level of the reduced signal is a low level, it indicates that the discharging/charging abnormality occurs in the previous-stage battery protection chip, and at this time, the next-stage battery protection chip directly generates a next-stage driving signal of the low level to control the discharging/charging MOS transistor to be turned off, thereby implementing the discharging/charging abnormality protection; when the level of the reduced signal is high level, the discharging/charging of the previous-stage battery protection chip is normal, at the moment, the next-stage battery protection chip generates a next-stage driving signal according to a self monitoring result, if the discharging/charging of the next-stage battery protection chip is abnormal, the next-stage driving signal with low level is generated to control the discharging/charging MOS tube to be switched off, the discharging/charging abnormal protection is realized, otherwise, the next-stage driving signal with high level is generated to control the discharging/charging MOS tube to be switched on.

In summary, according to the battery protection chip and the battery system of the present invention, through the design of the discharge voltage limiting detection circuit and the charge voltage limiting detection circuit, the high-low level conversion window voltage of the previous stage discharge/charge driving signal is reduced, so that the chip is suitable for the logic circuit formed by the thin gate oxide MOSFET device, thereby reducing the chip cost. In addition, the level of the discharging/charging driving signal of the upper stage is judged according to the current flow direction, and the discharging/charging driving signal is sensitive to the current flow direction and insensitive to the size, so that the discharging/charging driving circuit can normally work in a wider voltage range, and the problem of resistance voltage division is avoided; in addition, the current is controlled through the MOSFET, the circuit area is small, the current is small, and the power consumption is low. Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the utility model. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A battery protection chip, comprising at least: a discharge voltage limit detection circuit and a charge voltage limit detection circuit, wherein,

2. The battery protection chip of claim 1, wherein the discharge voltage limit detection circuit and the charge voltage limit detection circuit have the same circuit structure, and at least comprise: a detection module, a clamping module and an identification voltage limiting module, wherein,

3. The battery protection chip of claim 2, further comprising: a bias voltage generation module and/or a deglitch module; the bias voltage generation module is used for providing bias voltage for the identification voltage limiting module; the anti-spike pulse module is connected with the output end of the identification voltage limiting module and is used for filtering the spike voltage.

4. The battery protection chip according to claim 2 or 3, wherein the detection module comprises: and the first end of the current-limiting resistor is connected to a corresponding driving signal output by the previous-stage battery protection chip, and the second end of the current-limiting resistor is used as the output end of the detection module.

5. The battery protection chip of claim 4, wherein the detection module further comprises: and the short-circuit protection resistor is connected in series with the second end of the current-limiting resistor.

6. The battery protection chip of claim 2 or 3, wherein the clamping module comprises: a first diode and a second diode; the anode of the first diode is connected with the cathode of the second diode and the power supply end of the chip, and the cathode of the first diode is connected with the anode of the second diode and the output end of the detection module and serves as the output end of the clamping module.

7. The battery protection chip of claim 2 or 3, wherein the clamping module comprises: at least one first PMOS tube, wherein,

8. The battery protection chip according to claim 2 or 3, wherein the identification voltage limiting module comprises: the second PMOS tube, the first resistor, the first NMOS tube and the first current source; the grid electrode of the second PMOS tube is connected with bias voltage, the source electrode of the second PMOS tube is connected with the output end of the clamping module, and the drain electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube through the first resistor; the grid electrode of the first NMOS tube is connected with a reference voltage, and the source electrode of the first NMOS tube is connected with the reference end of the chip through the first current source and serves as the output end of the identification voltage limiting module.

9. The battery protection chip of claim 3, wherein the bias voltage generation module comprises: the third PMOS tube, the second resistor and the second current source; the grid electrode of the third PMOS tube is connected with the drain electrode of the third PMOS tube, the source electrode of the third PMOS tube is connected with the power end of the chip, and the drain electrode of the third PMOS tube is connected with the first end of the second resistor; and the second end of the second resistor is connected with a chip reference end through the second current source and is used as the output end of the bias voltage generation module.

10. The battery protection chip of claim 1, further comprising: a discharge logic circuit, a charge logic circuit, a discharge drive circuit and a charge drive circuit, wherein,

11. The battery protection chip of claim 10, wherein the discharge driving circuit and the charge driving circuit are implemented by an open-drain structure or a push-pull structure.

12. A battery system, comprising: at least two battery packs and at least two battery protection chips according to any one of claims 1 to 11, the battery protection chips corresponding to the battery packs one to one; the discharging driving signal output by the last stage battery protection chip is connected to the discharging voltage limiting detection circuit of the next stage battery protection chip, the charging driving signal output by the last stage battery protection chip is connected to the charging voltage limiting detection circuit of the next stage battery protection chip, the discharging driving signal output by the last stage battery protection chip controls the discharging MOS tube, and the charging driving signal output by the last stage battery protection chip controls the charging MOS tube.