CN216721331U

CN216721331U - Micro control circuit of satellite ground receiving station

Info

Publication number: CN216721331U
Application number: CN202121829265.4U
Authority: CN
Inventors: 杨焕强; 王晓亮; 王玖珍
Original assignee: Hebei Vste Technology Co ltd
Current assignee: Hebei Vste Technology Co ltd
Priority date: 2021-08-06
Filing date: 2021-08-06
Publication date: 2022-06-10
Anticipated expiration: 2031-08-06

Abstract

The utility model relates to the field of circuit design and provides a microcontroller circuit and a microcontroller device for a satellite ground receiving station. The above-mentioned satellite ground receiving station micro-control circuit includes: the device comprises an input isolation module, a main control module, an output isolation module, a communication isolation module, a power isolation module and a voltage stabilizing module; the input end of the power isolation module is connected with the first power end of the input isolation module and the output isolation module respectively, the output end of the power isolation module is connected with the communication isolation module and the input end of the voltage stabilizing module respectively, and the output end of the voltage stabilizing module is connected with the second power end of the input isolation module. The input isolation module sends the isolated limit signal to the main control module, the communication isolation module sends the isolated state signal and the first control signal to the main control module, the main control module generates a second control signal according to the limit signal, the state signal and the first control signal, and the main control module controls third-party equipment through the second control signal.

Description

Micro control circuit of satellite ground receiving station

Technical Field

The utility model relates to the technical field of circuit design, in particular to a micro-control circuit of a satellite ground receiving station.

Background

The satellite ground receiving station consists of a parabolic antenna, a feed network, a channel link, an antenna seat frame, a control cabinet, a baseband demodulation part and the like. An antenna mount is a device that supports an antenna structure and moves the antenna within a defined airspace. The satellite ground receiving station completes the actions of moving according to a preset rule, moving along with the target and the like through a micro-control system of the satellite receiving station, and monitors the position information of the target through a shaft foot detection device.

However, the existing micro-control system for the satellite ground receiving station has low reliability, stability and functionality, so that the task of receiving and transmitting data from and to the satellite by the satellite ground receiving station cannot be completed smoothly.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a micro control circuit of a satellite ground receiving station, which aims to solve the problems of low reliability, stability and functionality of the existing micro control system of the satellite ground receiving station.

In order to realize the purpose, the utility model adopts the technical scheme that:

the input end of the power isolation module is connected with the first power end of the input isolation module and the output isolation module respectively, the output end of the power isolation module is connected with the communication isolation module and the input end of the voltage stabilizing module respectively, and the output end of the voltage stabilizing module is connected with the second power end of the input isolation module.

The input isolation module receives a limit signal sent by the first signal acquisition equipment and sends the isolated limit signal to the main control module; the communication isolation module receives the state signal sent by the second signal acquisition equipment and sends the isolated state signal to the main control module; the communication isolation module receives a first control signal sent by the upper computer and sends the isolated first control signal to the main control module; the main control module generates a second control signal according to the limit signal, the state signal and the first control signal and sends the second control signal to the output isolation module; and the output isolation module sends the isolated second control signal to third-party equipment.

The beneficial effect of this application: the micro-control circuit of the satellite ground receiving station provided by the embodiment of the utility model comprises: the device comprises an input isolation module, an output isolation module, a main control module, a communication isolation module, a power isolation module and a voltage stabilizing module; the input isolation module sends the isolated limit signal to the main control module, the communication isolation module sends the isolated first control signal and the isolated state signal to the main control module, and the main control module generates a second control signal for controlling third-party equipment according to the isolated limit signal, the isolated first control signal and the isolated state signal, so that the signal accuracy of controlling and driving the third-party equipment is greatly improved, and the reliability, the stability and the functionality of the micro control system of the satellite ground receiving station are further ensured.

Drawings

Fig. 1 is a schematic diagram of a micro-control circuit of a satellite ground receiving station according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another micro-control circuit for a satellite ground receiving station according to an embodiment of the present invention;

FIG. 3 is a schematic circuit diagram of an input isolation module according to an embodiment of the present invention;

fig. 4 is a circuit schematic diagram of a main control module according to an embodiment of the present invention;

FIG. 5 is a circuit diagram of an output isolation module according to an embodiment of the present invention;

fig. 6 is a schematic circuit diagram of a communication isolation module according to an embodiment of the present invention;

fig. 7 is a schematic circuit diagram of a power isolation module according to an embodiment of the utility model;

fig. 8 is a schematic circuit diagram of a voltage regulator module according to an embodiment of the present invention;

fig. 9 is a schematic circuit diagram of a debug module according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

With reference to fig. 1, an embodiment of the present invention provides a micro-control circuit 100 for a satellite ground receiving station, including: the input isolation module 110, the output isolation module 130, the main control module 120, the communication isolation module 140, the power isolation module 150, and the voltage regulation module 160.

The input end of the power isolation module 150 is connected to the first power end of the input isolation module 110 and the output isolation module 130, the output end of the power isolation module 150 is connected to the communication isolation module 140 and the input end of the voltage stabilization module 160, and the output end of the voltage stabilization module 160 is connected to the second power end of the input isolation module 110.

The input isolation module 110 receives the limit signal sent by the first signal acquisition device, and sends the isolated limit signal to the main control module 120; the communication isolation module 140 receives the status signal sent by the second signal acquisition device, and sends the isolated status signal to the main control module 120; the communication isolation module 140 receives a first control signal sent by the upper computer, and sends the isolated first control signal to the main control module 120; the main control module 120 generates a second control signal according to the limit signal, the state signal and the first control signal, and sends the second control signal to the output isolation module 130; the output isolation module 130 sends the isolated second control signal to the third party device.

In this embodiment, the third party device may be a motor-equipped drive device. Such as the antenna mount of a satellite earth receiving station.

The embodiment of the utility model provides a satellite ground receiving station micro control circuit 100, the spacing signalling that the input isolation module 110 will be kept apart is given host system 120, communication isolation module 140 will be given host system 120 through the first control signal and the status signal transmission who keeps apart, host system 120 is according to the spacing signal after keeping apart, the second control signal of first control signal and the generation of status signal control third party's equipment, make the signal precision of control and drive third party's equipment improve greatly, and then satellite ground receiving station micro control system's reliability has been guaranteed, stability and functionality.

With reference to fig. 2, a specific implementation manner of the micro-control circuit 100 for a satellite ground receiving station provided as an embodiment of the present invention further includes: a debug module 170.

The debugging module 170 is connected to the main control module 120 and the debugging device, respectively.

With reference to fig. 3, as a specific implementation manner of the micro-control circuit 100 for a satellite ground receiving station provided in the embodiment of the present invention, a first input isolation unit 111, a second input isolation unit 112, and an input isolation interface 113 are provided;

the input isolation interface 113 unit is connected to the first input isolation unit 111, the second input isolation unit 112, the main control module 120, and the first signal acquisition device, respectively.

In the present embodiment, the first input isolation unit 111 includes: chip U16, resistance R50, resistance R55, resistance R56, resistance R57, resistance R58, resistance R59, resistance R60 and resistance R61.

Alternatively, the chip U16 may be a TLP521-4 chip.

TLP521-4 is a controllable photoelectric coupling device, and the photoelectric coupler is widely used in a terminal, a thyristor system device, a measuring instrument, a photocopier, an automatic ticket selling, and signal transmission between circuits of household appliances such as a fan and a heater, so that the front end is completely isolated from a load, and the purpose is to increase safety, reduce circuit interference and simplify circuit design, and TLP521-4 provides 16-pin plastic dip package in4 isolated optical couplers. The main characteristics of TLP 521-4: environmental suitability (-40 ℃ -100 ℃), storage temperature (-55 ℃ -125 ℃), soldering temperature (260 ℃/10s), input diode characteristics of TLP 521-4: forward current 50mA, reverse voltage 6V, power consumption 70mV, output transistor characteristics of TLP 521-4: collector emitter voltage BV_CEO55V and 150MW power consumption.

In the present embodiment, the second input isolation unit 112 includes: chip U17, resistance R51, resistance R52, resistance R53, resistance R54, resistance R62, resistance R63, resistance R64 and resistance R65.

Alternatively, the chip U17 may be a TLP521-4 chip.

In this embodiment, the input isolation interface 113 unit includes: an interface P4.

A resistor R50 is connected in series between the first power input terminal (pin 1) of the chip U16 and the input terminal of the power isolation module 150, a resistor R55 is connected in series between the second power input terminal (pin 3) of the chip U16 and the input terminal of the power isolation module 150, a resistor R56 is connected in series between the third power input terminal (pin 5) of the chip U16 and the input terminal of the power isolation module 150, a resistor R57 is connected in series between the fourth power input terminal (pin 7) of the chip U16 and the input terminal of the power isolation module 150, a resistor R58 is connected in series between the fifth power input terminal (pin 16) of the chip U16 and the input terminal of the power isolation module 150, a resistor R59 is connected in series between the sixth power input terminal (pin 14) of the chip U16 and the input terminal of the power isolation module 150, a resistor R60 is connected in series between the seventh power input terminal (pin 12) of the chip U16 and the input terminal of the power isolation module 150, the resistor R60 is connected in series between the eighth power input (pin 10) of the chip U16 and the input of the power isolation module 150. A first signal input end (pin 2) of the chip U16 is connected with the interface P4, a second signal input end (pin 4) of the chip U16 is connected with the interface P4, a third signal input end (pin 6) of the chip U16 is connected with the interface P4, a fourth signal input end (pin 8) of the chip U16 is connected with the interface P4, a first signal output end (pin 15) of the chip U16 is connected with the main control module 120, a second signal output end (pin 13) of the chip U16 is connected with the main control module 120, a third signal output end (pin 11) of the chip U16 is connected with the main control module 120, and a fourth signal output end (pin 9) of the chip U16 is connected with the main control module 120.

A resistor R51 is connected in series between the first power input terminal (pin 1) of the chip U17 and the input terminal of the power isolation module 150, a resistor R52 is connected in series between the second power input terminal (pin 3) of the chip U17 and the input terminal of the power isolation module 150, a resistor R53 is connected in series between the third power input terminal (pin 5) of the chip U17 and the input terminal of the power isolation module 150, a resistor R54 is connected in series between the fourth power input terminal (pin 7) of the chip U17 and the input terminal of the power isolation module 150, a resistor R62 is connected in series between the fifth power input terminal (pin 16) of the chip U17 and the input terminal of the power isolation module 150, a resistor R63 is connected in series between the sixth power input terminal (pin 14) of the chip U17 and the input terminal of the power isolation module 150, a resistor R64 is connected in series between the seventh power input terminal (pin 12) of the chip U17 and the input terminal of the power isolation module 150, the resistor R65 is connected in series between the eighth power input (pin 10) of the chip U16 and the input of the power isolation module 150. A first signal input end (pin 2) of the chip U17 is connected with the interface P4, a second signal input end (pin 4) of the chip U17 is connected with the interface P4, a third signal input end (pin 6) of the chip U17 is connected with the interface P4, a fourth signal input end (pin 8) of the chip U17 is connected with the interface P4, a fifth signal input end (pin 15) of the chip U17 is connected with the main control module 120, a sixth signal input end (pin 13) of the chip U17 is connected with the main control module 120, a seventh signal input end (pin 11) of the chip U17 is connected with the main control module 120, and an eighth signal input end (pin 9) of the chip U17 is connected with the main control module 120.

The first signal acquisition device is respectively connected with a first signal input end ID0 (pin 1) of an interface P4, a second signal input end ID1 (pin 2) of an interface P4, a third signal input end ID2 (pin 3) of an interface P4, a fourth signal input end ID3 (pin 4) of the interface P4, a fifth signal input end ID4 (pin 5) of the interface P4, a sixth signal input end ID5 (pin 6) of the interface P4, a seventh signal input end ID6 (pin 7) of the interface P4 and an eighth signal input end ID7 (pin 8) of the interface P4, and a ninth signal input end of the interface P4 is connected with a tenth signal input end of the interface P4 and connected with a low level.

Referring to fig. 4, in an embodiment of the micro-control circuit 100 for a satellite ground receiving station provided in the embodiment of the present invention, the main control module 120 includes: a main control chip U5 and a main control chip peripheral circuit.

In the embodiment, the main control chip U5 is embedded with a computer program,

optionally, the main control chip U5 may adopt an STM32F407ZET6 chip.

The core of STM32F407ZET6 chip is FPU-bearing

32 bit

Adaptive real-time accelerator (ART accelerator) for realizing zero-wait state running performance in Flash memory^TM) The main frequency is up to 168MHz, the MPU can realize the performance of up to 210DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and has a DSP instruction set. The memory of the STM32F407ZET6 chip has up to 1MB Flash, up to 192+4KB of SRAM, including 64-KB of CCM (core coupled memory) data RAM, up to 32 external memory controllers (SRAM, PSRAM, NOR/NAND) as data bus. The timer of STM32F407ZET6 has 12 16-bit timers and 2 32-bit timers with frequencies up to 168 MHz. Where each timer has 4 inputs capture/output compare/PWM, or pulse counter and quadrature (incremental) encoder inputs. The STM32F407ZET6 chip has 140I/O ports with interrupt functionality, 136 fast I/Os (up to 84MHz), 138 5V tolerant I/Os. The communication interface of STM32F407ZET6 chip has 3I 2C interfaces (SMBus/PMBus), 4 USART/4 UARTs (10.5Mbit/s, ISO7816 interface, L IN, IrDA, modem control), 3 SPI (42 Mbit/s), 2 full duplex I2S with multiplexing, reach audio level precision through internal audio PLL or external clock, 2 CAN (2.0B initiative) and SDIO interface.

Optionally, as a specific implementation manner of the micro control circuit 100 for the satellite ground receiving station provided in the embodiment of the present invention, a Cortex-M4 tracking macro unit is embedded inside the main control chip.

Cortex-M4 tracks macro cells for use in assisting debug module 170.

Referring to fig. 5, as a specific implementation of the micro-control circuit 100 for a satellite ground receiving station provided as an embodiment of the present invention, a first output isolation unit 131, a second output isolation unit 132, a third output isolation unit 133, and an output isolation interface 134 are provided.

The output isolation interface 134 is connected to the first output isolation unit 131, the second output isolation unit 132, the third output isolation unit 133, the main control module 120, and a third-party device, respectively.

In this embodiment, the first output isolation unit 131 includes: chip U8, chip U9, chip U11, resistance R12, resistance R13, resistance R14, resistance R16, resistance R17, resistance R18, resistance R19, resistance R25, resistance R26, resistance R27, resistance R28, resistance R29, resistance R30, resistance R31 and resistance R32.

Alternatively, the chip U8 may be a TLP521-4 chip.

Alternatively, the chip U9 may be a TLP521-4 chip.

Alternatively, the chip U11 may be a ULN2803LW chip.

ULN2803LW has high working voltage, large working current, and the sink current can reach 500mA, and can bear 50V voltage when in off state, and the output can also run in parallel at high load current, and output voltage 50V and continuous current 500 mA; input voltage 30V, continuous base current 25 mA.

The resistor R12 is connected in series between the main control module 120 and the first signal input terminal (pin 1) of the chip U8, the resistor R13 is connected in series between the main control module 120 and the second signal input terminal (pin 3) of the chip U8, the resistor R14 is connected in series between the main control module 120 and the third signal input terminal (pin 5) of the chip U8, the resistor R15 is connected in series between the main control module 120 and the fourth signal input terminal (pin 7) of the chip U8, and the first ground terminal of the chip U8 is connected to and grounded to the second ground terminal of the chip U8, the third ground terminal of the chip U8, and the fourth ground terminal of the chip U8, respectively. A resistor R25 is connected IN series between the input terminal of the power isolation module 150 and the first power input terminal (pin 16) of the chip U8, a resistor R26 is connected IN series between the input terminal of the power isolation module 150 and the second power input terminal (pin 14) of the chip U8, a resistor R27 is connected IN series between the input terminal of the power isolation module 150 and the third power input terminal (pin 12) of the chip U8, a resistor R28 is connected IN series between the input terminal of the power isolation module 150 and the fourth power input terminal (pin 10) of the chip U8, the first signal output terminal (pin 15) of the chip U8 and the first signal input terminal IN1 (pin 1) of the chip U11, the second signal output terminal (pin 13) of the chip U8 and the second signal input terminal IN 84 (pin 2) of the chip U11, the third signal output terminal (pin 11) of the chip U8 and the third signal input terminal 3 (pin 3) of the chip U11, and the fourth signal output terminal (pin 9) of the chip U5 and the fourth signal input terminal (pin 594 IN 57342) of the chip U11. The resistor R16 is connected in series between the main control module 120 and the first signal input terminal (pin 1) of the chip U9, the resistor R17 is connected in series between the main control module 120 and the second signal input terminal (pin 3) of the chip U9, the resistor R18 is connected in series between the main control module 120 and the third signal input terminal (pin 5) of the chip U9, the resistor R19 is connected in series between the main control module 120 and the fourth signal input terminal (pin 7) of the chip U9, and the first ground terminal of the chip U9 is connected to and grounded to the second ground terminal of the chip U9, the third ground terminal of the chip U9, and the fourth ground terminal of the chip U9, respectively. A resistor R29 is connected IN series between the input terminal of the power isolation module 150 and the first power input terminal (pin 16) of the chip U9, a resistor R30 is connected IN series between the input terminal of the power isolation module 150 and the second power input terminal (pin 14) of the chip U9, a resistor R31 is connected IN series between the input terminal of the power isolation module 150 and the third power input terminal (pin 12) of the chip U9, a resistor R32 is connected between the input terminal of the power isolation module 150 and the fourth power input terminal (pin 10) of the chip U9, a first signal output terminal (pin 15) of the chip U9 and a fifth input terminal IN5 (pin 5) of the chip U11, a second signal output terminal (pin 13) of the chip U9 and a second signal input terminal IN6 (pin 6) of the chip U11, a third signal output terminal (pin 11) of the chip U9 and a third signal input terminal IN7 (pin 7) of the chip U11, a fourth signal output terminal (pin 9) of the chip U9 and a fourth signal input terminal (pin 598) of the chip U11. The first output end OUT1 (pin 18) of the chip U11 is connected to the output isolation interface 134, the second output end OUT2 (pin 17) of the chip U11 is connected to the output isolation interface 134, the third output end OUT3 (pin 16) of the chip U11 is connected to the output isolation interface 134, the fourth output end OUT4 (pin 15) of the chip U11 is connected to the output isolation interface 134, the fifth output end OUT5 (pin 14) of the chip U11 is connected to the output isolation interface 134, the sixth output end OUT6 (pin 13) of the chip U11 is connected to the output isolation interface 134, the seventh output end OUT7 (pin 12) of the chip U11 is connected to the output isolation interface 134, the second output end OUT8 (pin 11) of the chip U11 is connected to the output isolation interface 134, the power supply input end COMD of the chip U11 is connected to the input end of the power supply isolation module 150, and the ground terminal GND of the chip U11.

In this embodiment, the second output isolation unit 132 includes: chip U10, resistance R20, resistance R21, resistance R22, resistance R23, resistance R33, resistance R34, resistance R35, resistance R36.

Alternatively, the chip U10 may be a TLP521-4 chip.

The resistor R20 is connected in series between the main control module 120 and the first signal input terminal (pin 1) of the chip U10, the resistor R21 is connected in series between the main control module 120 and the second signal input terminal (pin 3) of the chip U10, the resistor R22 is connected in series between the main control module 120 and the third signal input terminal (pin 5) of the chip U10, and the resistor R23 is connected in series between the main control module 120 and the fourth signal input terminal (pin 7) of the chip U10. The first ground terminal (pin 2) of the chip U10 is connected to and grounded to the second ground terminal (pin 4) of the chip U10, the third ground terminal (pin 6) of the chip U10, and the fourth ground terminal (pin 8) of the chip U10, respectively. The first signal output end of the chip U10 is connected with the output isolation interface 134 through a resistor R33, the second signal output end of the chip U10 is connected with the output isolation interface 134 through a resistor R34, the third signal output end of the chip U10 is connected with the output isolation interface 134 through a resistor R35, and the first signal output end of the chip U10 is connected with the output isolation interface 134 through a resistor R36. The fifth ground terminal (pin 15) of the chip U10 is connected to and grounded to the sixth ground terminal (pin 13) of the chip U10, the seventh ground terminal (pin 11) of the chip U10, and the eighth ground terminal (pin 9) of the chip U10, respectively.

In the present embodiment, the third output isolation unit 133 includes: the circuit comprises a chip U13, a chip U14, a chip U15, a resistor R41, a resistor R42, a resistor R43, a resistor R44, a resistor R45, a resistor R46, a resistor R47, a resistor R48, a resistor R49, a capacitor C62, a capacitor C63 and a capacitor C64.

Alternatively, the chip U13 may be a TLP2438 chip.

Alternatively, the chip U14 may be a TLP2438 chip.

Alternatively, the chip U15 may be a TLP2438 chip.

TLP2348 is a high-speed opto-isolator chip with short response time, and mainly generates high-frequency counting pulses or PWW waves continuously in the circuit for controlling position pulses or speed regulation of the motor. TLP2438 is characterized by operating temperature (-40 ℃ to 110 ℃), supply voltage (4.5 to 30V), propagation delay time 120ns (max), pulse width distortion: 40ns (maximum), isolation voltage: 3750Vrms (min).

The positive phase input end (pin 1) of the chip U13 is connected with the main control module 120, the negative phase input end (pin 3) of the chip U13 is grounded through the resistor R47, the power input end VCC of the chip U13 is connected with the input end of the power isolation module 150, one end of the resistor R42 is respectively connected with the signal output end (pin 5) of the chip U13, one end of the resistor R44 is connected, the other end of the resistor R42 is connected with the input end of the power isolation module 150, one end of the capacitor C62 is connected with the input end of the power isolation module 150, the other end of the capacitor C62 is connected with the ground end GND of the chip U13 and grounded, and the other end of the resistor R44 is connected with the output isolation interface 134.

The positive phase input end (pin 1) of the chip U14 is connected with the main control module 120, the negative phase input end (pin 3) of the chip U14 is grounded through the resistor R48, the power input end VCC of the chip U14 is connected with the input end of the power isolation module 150, one end of the resistor R41 is respectively connected with the signal output end (pin 5) of the chip U14, one end of the resistor R45 is connected, the other end of the resistor R41 is connected with the input end of the power isolation module 150, one end of the capacitor C63 is connected with the input end of the power isolation module 150, the other end of the capacitor C63 is connected with the ground end GND of the chip U14 and grounded, and the other end of the resistor R45 is connected with the output isolation interface 134.

The positive phase input end (pin 1) of the chip U15 is connected with the main control module 120, the negative phase input end (pin 3) of the chip U15 is grounded through the resistor R49, the power input end VCC of the chip U15 is connected with the input end of the power isolation module 150, one end of the resistor R43 is respectively connected with the signal output end (pin 5) of the chip U15, one end of the resistor R46 is connected, the other end of the resistor R43 is connected with the input end of the power isolation module 150, one end of the capacitor C64 is connected with the input end of the power isolation module 150, the other end of the capacitor C64 is connected with the ground end GND of the chip U15 and grounded, and the other end of the resistor R46 is connected with the output isolation interface 134.

In this embodiment, the output isolation interface 134 includes: interface P5.

The first output end (pin 18) of the first communication isolation unit 141 signal of the interface P5 is connected with a third-party device, the second output end (pin 17) of the first communication isolation unit 141 signal of the interface P5 is connected with the third-party device, the third output end (pin 16) of the first communication isolation unit 141 signal of the interface P5 is connected with the third-party device, the fourth output end (pin 15) of the first communication isolation unit 141 signal of the interface P5 is connected with the third-party device, the fifth output end (pin 14) of the first communication isolation unit 141 signal of the interface P5 is connected with the third-party device, the sixth output end (pin 13) of the first communication isolation unit 141 signal of the interface P5 is connected with the third-party device, the seventh output end (pin 12) of the first communication isolation unit 141 signal of the interface P5 is connected with the third-party device, and the eighth output end (pin 11) of the first communication isolation unit 141 signal of the interface P5 is connected with the third-party device. The first output end (pin 8) of the second communication isolation unit 142 signal of the interface P5 is connected with a third-party device, the second output end (pin 6) of the second communication isolation unit 142 signal of the interface P5 is connected with the third-party device, the third output end (pin 4) of the second communication isolation unit 142 signal of the interface P5 is connected with the third-party device, and the fourth output end (pin 2) of the second communication isolation unit 142 signal of the interface P5 is connected with the third-party device. A first output end (pin 5) of a signal of the third communication isolation unit 143 of the interface P5 is connected with a third-party device, a second output end (pin 1) of the signal of the third communication isolation unit 143 of the interface P5 is connected with the third-party device, and a third output end (pin 3) of the signal of the third communication isolation unit 143 of the interface P5 is connected with the third-party device.

Referring to fig. 6, as a specific implementation of the micro-control circuit 100 for a satellite ground receiving station provided by the embodiment of the present invention, a first communication isolation unit 141, a second communication isolation unit 142, a third communication isolation unit 143, a fourth communication isolation unit 144, a fifth communication isolation unit 145, and a communication isolation interface 146 are provided.

The communication isolation interface 146 is connected to the first communication isolation unit 141, the second communication isolation unit 142, the third communication isolation unit 143, the fourth communication isolation unit 144, the fifth communication isolation unit 145, the main control module 120, the second signal acquisition device, and the upper computer respectively.

In the present embodiment, the first communication isolating unit 141 includes: chip U4, electric capacity C24, electric capacity C25, electric capacity C26, electric capacity C28, electric capacity C29, electric capacity C30, electric capacity C31, resistance R8.

Alternatively, the chip U4 may be an ADM2582E chip or an ADM2582F chip.

ADM2582E/ADM2587E is a high-integration data transceiver, supporting 15kVESD protection and signal and power isolation. The device is suitable for high-speed communication over a multi-drop transmission line. The internal integration isolated DC-DC power supply does not need to be additionally provided with a DC-DC isolation module. It is designed for balanced transmission lines and conforms to ANSI TIA/EIA-485-A-98 and ISO8482:1987(E) standards. ADM2582E/ADM 2587E: the isolated RS-485/RS-422 transceiver may be configured in half-duplex or full-duplex mode, integrated with an isolated DC/DC converter, a ± 15kV ESD protection function, an isolation voltage: 2500V, data rate: the power supply of 500Kbps/16Mbps, 5V or 3.3V can prevent output short circuit, 256 nodes are provided on a bus, the input of a real fault safe receiver is provided, and the high common-mode transient suppression capability is realized: (> 25 kV/. mu.s).

A capacitor C24 and a capacitor C25 are connected in parallel between an isolation power input end VIOIN (pin 19) and a ground terminal of a chip U4, a capacitor C26 and a capacitor C27 are connected in parallel between a first power input end (pin 2) of a chip U4 and an output end of a power isolation module 150, a capacitor C28 and a capacitor C29 are connected in parallel between a second power input end (pin 8) of the chip U4 and an output end of the power isolation module 150, a capacitor C30 and a capacitor C31 are connected in parallel between an isolation power output end VIOOUT (pin 12) and a ground terminal of a chip U4, the isolation power input end VIOIN of the chip U4 is connected with the isolation power output end VIOOUT of the chip U4, one end of a resistor R8 is respectively connected with a first signal output end A (pin 18) of the chip U4, a fourth signal output end Y (pin 13) of the chip U4 and a communication isolation interface 146, and the other end of the resistor R8 is respectively connected with a second signal output end B (pin 17) of the chip U4 and a fourth signal output end Z4, The communication isolation interface 146 is connected, a signal receiving end RXD (4 pin) of the chip U4 is connected with the main control module 120, a signal transmitting end TXD (7 pin) of the chip U4 is connected with the main control module 120, and a first enable control end RE (5 pin) of the chip U4, a second enable control end DE (4 pin) of the chip U4 and the main control module 120 are connected with each other pairwise.

In this embodiment, the second communication isolating unit 142 includes: chip U7, electric capacity C40, electric capacity C41, electric capacity C42, electric capacity C43, electric capacity C44, electric capacity C45, electric capacity C46, resistance R24.

A capacitor C40 and a capacitor C41 are connected in parallel between an isolation power input end VIOIN (pin 19) and a ground terminal of a chip U7, a capacitor C42 and a capacitor C43 are connected in parallel between a first power input end (pin 2) of a chip U7 and an output end of a power isolation module 150, a capacitor C44 and a capacitor C45 are connected in parallel between a second power input end (pin 8) of the chip U7 and an output end of the power isolation module 150, a capacitor C46 and a capacitor C47 are connected in parallel between an isolation power output end VIOOUT (pin 12) and a ground terminal of a chip U7, the isolation power input end VIOIN of the chip U7 is connected with the isolation power output end VIOOUT of the chip U7, one end of a resistor R24 is respectively connected with a first signal output end A (pin 18) of the chip U7, a fourth signal output end Y (pin 13) of the chip U7 and a communication isolation interface 146, and the other end of the resistor R24 is respectively connected with a second signal output end B (pin 17) of the chip U7 and a fourth signal output end Z7, The communication isolation interface 146 is connected, a signal receiving end RXD (4 pin) of the chip U7 is connected with the main control module 120, a signal transmitting end TXD (7 pin) of the chip U7 is connected with the main control module 120, and a first enable control end RE (5 pin) of the chip U7, a second enable control end DE (4 pin) of the chip U7 and the main control module 120 are connected with each other pairwise.

In the present embodiment, the third communication isolating unit 143 includes: chip U12, electric capacity C50, electric capacity C51, electric capacity C52, electric capacity C58, electric capacity C59, electric capacity C60, electric capacity C61, resistance R38.

A capacitor C50 and a capacitor C51 are connected in parallel between an isolation power input end VIOIN (pin 19) and a ground terminal of a chip U12, a capacitor C52 and a capacitor C53 are connected in parallel between a first power input end (pin 2) of a chip U12 and an output end of a power isolation module 150, a capacitor C58 and a capacitor C59 are connected in parallel between a second power input end (pin 8) of the chip U12 and an output end of the power isolation module 150, a capacitor C60 and a capacitor C61 are connected in parallel between an isolation power output end VIOOUT (pin 12) and a ground terminal of a chip U12, the isolation power input end VIOIN of the chip U12 is connected with the isolation power output end VIOOUT of the chip U12, one end of a resistor R24 is respectively connected with a first signal output end A (pin 18) of the chip U12, a fourth signal output end Y (pin 13) of the chip U12 and a communication isolation interface 146, and the other end of the resistor R24 is respectively connected with a second signal output end B (pin 17) of the chip U12 and a fourth signal output end Z12, The communication isolation interface 146 is connected, a signal receiving end RXD (4 pin) of the chip U12 is connected with the main control module 120, a signal transmitting end TXD (7 pin) of the chip U12 is connected with the main control module 120, and a first enable control end RE (5 pin) of the chip U12, a second enable control end DE (4 pin) of the chip U12 and the main control module 120 are connected with each other pairwise.

In this embodiment, the fourth communication isolating unit 144 includes: chip U1, electric capacity C1, electric capacity C2, electric capacity C3, electric capacity C4, electric capacity C5, electric capacity C11.

A power input end VCC (pin 2 and pin 3) of a chip U1 is connected with an output end of the power isolation module 150, the anode of a capacitor C1 is respectively connected with an auxiliary power supply end V/ISO (pin 20) of a chip U1 and the cathode of a capacitor C2, the cathode of a capacitor C1 is grounded, the positive phase power output end V + (pin 19) of a chip U1 is connected with the anode of the capacitor C2, a reference ground end GND/ISO (pin 11) of the chip U1 is connected with the inverted power output end V- (pin 12) of the chip U1 through the capacitor C11, the first charge pump capacitor anode C1+ (pin 18) of the chip U1 is connected with the anode of the capacitor C4, the first charge pump capacitor cathode C1+ (pin 17) of the chip U1 is connected with the cathode of the capacitor C4, the second charge pump capacitor anode C2+ (pin 14) of the chip U1 is connected with the anode of the capacitor C5, and the second charge pump capacitor C53936 + (pin 5) of the cathode of the capacitor C2 of the chip U1 is connected with the capacitor C53913, a first signal input terminal TIN (pin 9) of the chip U1 is connected with the main control module 120, a first signal output terminal ROUT (pin 9) of the chip U1 is connected with the main control module 120, a second signal input terminal RIN (pin 15) of the chip U1 is connected with an upper computer, a second signal output terminal TOUT (pin 16) of the chip U1 is connected with the upper computer, a capacitor C1 is connected between a power supply input terminal VCC of the chip U1 and a grounding terminal of the chip U1 in parallel,

in this embodiment, the fifth communication isolating unit 145 includes: chip U6, electric capacity C32, electric capacity C33, electric capacity C34, electric capacity C35, electric capacity C36, electric capacity C37, electric capacity C38, electric capacity C39, resistance R9.

A capacitor C34 and a capacitor C35 are connected in parallel between an isolated power input terminal VISOIN (pin 19) of the chip U6 and a ground terminal, a capacitor C32 and a capacitor C33 are connected in parallel between a first power input terminal (pin 2) of the chip U6 and an output terminal of the power isolation module 150, a capacitor C36 and a capacitor C37 are connected in parallel between a second power input terminal (pin 8) of the chip U6 and an output terminal of the power isolation module 150, a capacitor C38 and a capacitor C39 are connected in parallel between an isolated power output terminal VISOOUT (pin 12) of the chip U6 and a ground terminal, an isolated power input terminal VISOIN of the chip U6 is connected to the isolated power output terminal VISOOUT of the chip U6, a resistor R9 is connected in parallel between a first signal output terminal a (pin 18) of the chip U6 and a second signal output terminal B (pin 17) of the chip U6, a first signal output terminal a of the chip U6 is connected to the communication isolation interface 146, and a second signal output terminal B of the chip U6 is connected to the communication isolation interface 146, a third signal output end Z (pin 15) of the chip U6 is connected with the communication isolation interface 146, a fourth signal output end Y (pin 13) of the chip U6 is connected with the communication isolation interface 146, a signal receiving end RXD (pin 4) of the chip U6 is connected with the main control module 120, a signal transmitting end TXD (pin 7) of the chip U6 is connected with the main control module 120, a first enable control end RE (pin 5) of the chip U6, a second enable control end DE (pin 4) of the chip U6 and the main control module 120 are connected with each other pairwise.

In this embodiment, the communication isolation interface 146 includes: interface P3, resistance R10, resistance R11.

A first signal receiving end (pin 2) of an interface P3 is connected with an upper computer, a first signal transmitting end (pin 4) of an interface P3 is connected with the upper computer, a second signal positive phase receiving end (pin 10) of an interface P3 is connected with the upper computer, a second signal negative phase receiving end (pin 9) of an interface P3 is connected with the upper computer, a second signal positive phase transmitting end (pin 12) of an interface P3 is connected with the upper computer, a second signal negative phase transmitting end (pin 11) of an interface P3 is connected with the upper computer, a resistor R11 is connected between the second signal positive phase receiving end of the interface P3 and the second signal positive phase transmitting end of the interface P3 in parallel, a resistor R10 is connected between the second signal negative phase receiving end of the interface P3 and the second signal negative phase transmitting end of the interface P3 in parallel, a third signal positive phase transmitting and receiving end (pin 4) is connected with the second signal collecting device, and a third signal negative phase transmitting and receiving end (pin 6) is connected with the second signal collecting device, a fourth signal normal-phase transceiving end (pin 18) is connected with the second signal acquisition equipment, a third signal reverse-phase transceiving end (pin 20) is connected with the second signal acquisition equipment, a fourth signal normal-phase transceiving end (pin 14) is connected with the second signal acquisition equipment, and a fourth signal reverse-phase transceiving end (pin 16) is connected with the second signal acquisition equipment.

Referring to fig. 7, in an embodiment of the micro-control circuit 100 for a satellite ground receiving station provided as an embodiment of the present invention, the power isolation module 150 includes: a power interface 151 and a power isolation unit 152.

Optionally, the voltage input range of the power interface 151 may be 9-30V.

In this embodiment, the power interface 151 includes: interface P1.

The power input terminal of the interface P1 is connected to an external power source, and the power output terminal of the interface P1 is connected to the power isolation unit 152 of the power isolation unit 152.

In the present embodiment, the power isolation unit 152 includes: chip U2, electric capacity C6, electric capacity C8, diode D3.

The anode of the diode D3 is connected to the power output terminal of the interface P1, the cathode of the diode D3 is connected to the power input terminal Vin (pin 2) of the chip U2 and the anode of the capacitor C8, the cathode of the capacitor C8 is connected to the ground terminal (pin 1) of the chip U2, the power output terminal + V0 (pin 3) of the chip U2 is connected to the anode of the capacitor C6, and the equivalent ground terminal OV (pin 5) of the chip U2 is connected to the cathode of the capacitor C6.

In this embodiment, the capacitors C6 and C8 are filter capacitors.

Optionally, the chip U2 may be a DC/DC power module.

In the embodiment, the DC/DC power module can convert 9-30V voltage into stable 5V output voltage, and can also isolate and block external interference.

Referring to fig. 8, in an embodiment of the micro-control circuit 100 for a satellite ground receiving station provided by the embodiment of the present invention, the voltage stabilizing module 160 includes: voltage stabilizing chip and voltage stabilizing chip peripheral circuit.

In this embodiment, the voltage stabilization chip includes: chip U3.

In this embodiment, the voltage stabilization chip peripheral circuit includes: capacitor C7, capacitor C7, and capacitor C10.

The power input end IN (pin 3) of the chip U3, one end of the capacitor C9 and the output end of the power isolation module 150 are connected with each other pairwise, the power output end OUT (pin 2 and pin 4) of the chip U3 is respectively connected with the anode of the capacitor C7 and one end of the capacitor C10, and the cathode of the capacitor C7 is connected with the other end of the capacitor C10 and grounded.

Referring to fig. 9, in an embodiment of the micro-control circuit 100 for a satellite ground receiving station provided as an embodiment of the present invention, the debugging module 170 includes: a debugging unit 171 and a startup configuration unit 172.

The debugging unit 171 is connected to the main control module 120 and the debugging device, respectively.

The start configuration unit 172 is connected to the output terminals of the main control module 120 and the voltage stabilizing module 160, respectively.

In the present embodiment, the debugging unit 171 includes: interface P2, resistance R3, resistance R7.

The power output end (pin 1) of the interface P2 is connected with the debugging device, the first signal receiving end (pin 2) of the interface P2 is connected with the debugging device, the second signal receiving end (pin 3) of the interface P2 is connected with the debugging device, the grounding end (pin 4) of the interface P2 is connected with the debugging device, one end of the resistor R3 is connected with the output end of the voltage stabilizing module 160 and the power input end of the interface P2 respectively, the other end of the resistor R3 is connected with the first signal transmitting end of the interface P2 and the main control module 120 respectively, one end of the resistor R7 is connected with the second signal transmitting end of the interface P2 and the main control module 120, and the other end of the resistor R7 is connected with the grounding end of the interface P2 and grounded respectively.

Optionally, the debug unit 171 supports an SWD interface or a JTAG interface.

The characteristics of the SWD debugging interface: the SWD interface mode is more reliable than JTAG in the high-speed mode. The JTAG download procedure will fail in the case of large data volumes, but the chance of SWD occurrence will be much smaller. Under the condition of basically using a JTAG simulation mode, the SWD mode can be directly used, SWD interface simulation is carried out, fewer pins are supported, the SWD mode is recommended to be used when the size of a board is limited, the needed pins are few, and the needed PCB space is small.

In this embodiment, the start configuration unit 172 includes: resistance R1, resistance R2, resistance R6.

One end of the resistor R1 is connected with the main control module 120, the other end of the resistor R1 is connected with one end of the resistor R2 and grounded, the other end of the resistor R2 is connected with the main control module 120, one end of the resistor R6 is connected with the output end of the voltage stabilizing module 160, and the other end of the resistor R6 is connected with the main control module 120.

Optionally, the start configuration unit 172 implements different start modes by cooperating with the BOOT0 and BOOT1 pins of the main control module 120, and the circuit is configured to start from FLASH, that is, FLASH built in the STM32, and download a program to FLASH in an SWD mode, and directly start the program from FLASH after being restarted.

Corresponding to any one of the above-mentioned satellite ground receiving station micro-control circuits 100, an embodiment of the present invention further provides a satellite ground receiving station micro-control device, which includes any one of the above-mentioned satellite ground receiving station micro-control circuits 100 and has the advantages of the above-mentioned communication switching circuit, and details are not repeated herein.

While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and alterations can be made herein without departing from the principles and spirit of the utility model, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A satellite earth station micro-control circuit, comprising: the device comprises an input isolation module, a main control module, an output isolation module, a communication isolation module, a power isolation module and a voltage stabilizing module;

the input end of the power isolation module is respectively connected with the first power end of the input isolation module, the output isolation module and an external power supply, the output end of the power isolation module is respectively connected with the communication isolation module and the input end of the voltage stabilization module, and the output end of the voltage stabilization module is connected with the second power end of the input isolation module and the main control module;

the input isolation module receives a limit signal sent by first signal acquisition equipment and sends the isolated limit signal to the main control module; the communication isolation module receives the state signal sent by the second signal acquisition equipment and sends the isolated state signal to the main control module; the communication isolation module receives a first control signal sent by an upper computer and sends the isolated first control signal to the main control module; the main control module generates a second control signal according to the limit signal, the state signal and the first control signal and sends the second control signal to an output isolation module; and the output isolation module sends the isolated second control signal to third-party equipment.

2. The satellite earth station micro-control circuit as claimed in claim 1, further comprising: a debugging module;

the debugging module is respectively connected with the main control module and the debugging equipment.

3. The satellite earth station microcontroller circuit as claimed in claim 1 wherein the input isolation module comprises: the device comprises a first input isolation unit, a second input isolation unit and an input isolation interface;

the input isolation interface unit is respectively connected with the first input isolation unit, the second input isolation unit, the main control module and the first signal acquisition equipment.

4. The satellite earth station micro-control circuit of claim 1, wherein the master control module comprises: the device comprises a main control chip and a main control chip peripheral circuit.

5. The satellite earth station microcontroller circuit as claimed in claim 1 wherein the output isolation module comprises: the first output isolation unit, the second output isolation unit, the third output isolation unit and the output isolation interface;

the output isolation interface is respectively connected with the first output isolation unit, the second output isolation unit, the third output isolation unit, the main control module and the third-party equipment.

6. The satellite earth station micro-control circuit of claim 1, wherein the communication isolation module comprises: the first communication isolation unit 141, the second communication isolation unit, the third communication isolation unit, the fourth communication isolation unit, the fifth communication isolation unit and the communication isolation interface;

the communication isolation interface is connected with the first communication isolation unit 141, the second communication isolation unit, the third communication isolation unit, the fourth communication isolation module, the fifth communication isolation module, the main control module, the second signal acquisition device and the upper computer respectively.

7. The satellite earth station microcontroller circuit of claim 1 wherein the power isolation module comprises: a power interface and a power isolation unit;

the input end of the power interface is connected with the external power supply, and the output end of the power interface is connected with the input end of the power isolation unit.

8. The satellite earth station micro-control circuit of claim 1, wherein the voltage regulator module comprises: a voltage stabilizing chip and a peripheral circuit.

9. The satellite earth station micro-control circuit of claim 2, wherein the debug module comprises: the system comprises a debugging unit and a starting configuration unit;

the debugging unit is respectively connected with the main control module and the debugging equipment;

the starting configuration unit is respectively connected with the output ends of the main control module and the voltage stabilizing module.