CN216649668U

CN216649668U - Multi-key control circuit based on GPIO and ADC

Info

Publication number: CN216649668U
Application number: CN202220040432.5U
Authority: CN
Inventors: 赵凯
Original assignee: Zhejiang Qiyang Intelligent Technology Co ltd
Current assignee: Zhejiang Qiyang Intelligent Technology Co ltd
Priority date: 2022-01-04
Filing date: 2022-01-04
Publication date: 2022-05-31
Anticipated expiration: 2032-01-04

Abstract

The utility model relates to a multi-key control circuit based on a GPIO and an ADC (analog to digital converter). When the GPIO port is in a pull-up input interrupt mode, the ADC port is in a close mode; when one switch key is pressed down, the GPIO port interrupts response, the ADC port is opened and is switched into a high-resistance input mode, current data is read, which key is input is judged through the ADC data, the ADC is turned off after the current data is processed, the GPIO port is switched into a pull-up input mode, a manual button is generally about 10ms, and a processor is waken up for 3-5 ms, so that the reading function can be interrupted even in a dormant state. Therefore, the method and the device can solve the problems that the system overhead is high, the power consumption is high under low power consumption, and the key cannot be awakened.

Description

Multi-key control circuit based on GPIO and ADC

Technical Field

The utility model relates to the technical field of circuits, in particular to a multi-key control circuit based on GPIO and ADC.

Background

In the market, a plurality of paths of GPIOs or special keyboard control chips are commonly used for realizing the control of a plurality of paths of keys, and a scheme for realizing the control of a plurality of paths of keys by using one ADC is also available. But the prior scheme of independently using GPIO needs multiple paths of GPIOs, and has high requirement on hardware resources; the ADC is used for realizing the pure operation, the data of the ADC needs to be read in a polling mode, the system overhead is high, and the reading is not realized under the condition that a system is dormant. Therefore, the prior art has the problems that the system overhead is high, especially under the condition of low power consumption, the system power consumption is high, and the key-press wakeup cannot be realized.

In summary, a multi-key control circuit based on GPIO and ADC is needed to solve the above problems.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the problems in the prior art and provides a multi-key control circuit based on GPIO and ADC.

In order to realize the purpose of the utility model, the utility model adopts the following technical scheme: a multi-key control circuit based on GPIO and ADC comprises a processor provided with a GPIO port and an ADC port, and a plurality of switch keys, a voltage dividing resistor and a protection diode which are electrically connected with the GPIO port and the ADC port; the GPIO port has an interrupt function.

The working principle and the beneficial effects are as follows: 1. aiming at the existing mode realized by pure ADC, because the key is a trigger event and the time is short, the ADC can not realize interrupt reading, if the key is not read in an interrupt mode, the ADC data is required to be read every 1-3 ms to ensure that the key event is not lost, even if the key event does not exist, the system needs to continuously read the ADC, thereby causing the waste of system resources, and when the GPIO port is in a pull-up input interrupt mode, the circuit of the application is in a close mode; when one switch key is pressed down, the GPIO port interrupts response, the ADC port is opened and is switched into a high-resistance input mode, current data is read, which key is input is judged through ADC port data, the ADC port is closed and the GPIO port mode is switched into a pull-up input mode, a manual button is generally about 10ms after the processing is finished, and a processor is waken for 3-5 ms, so that the reading function can be interrupted in the same way even in a sleep state, and multiple paths of GPIOs are not needed, so that the problems that the system overhead is large, the power consumption is large and the keys cannot be waken up under low power consumption are solved;

2. meanwhile, because the power consumption of all the ADC function modules is in mA level, as described above, it is required to ensure that the key event of the system is not lost, and the ADC function cannot be turned off even if the system is in a dormant state, so that the power consumption of the system is large, and if the ADC function is turned off, the power consumption can be reduced, but the system cannot be awakened through the key. The method uses the GPIO interrupt function, closes the ADC in the sleep mode, triggers the GPIO interrupt firstly when a key event occurs, then opens the ADC function to read the key value, and simultaneously solves the problems of low power consumption and awakening.

Further, the voltage dividing resistor at least comprises a first voltage dividing resistor R0, a second voltage dividing resistor R1 and a third voltage dividing resistor R2, the protection diode at least comprises a first diode D1 for protecting the ADC port and a second diode D2 for isolating the ADC port and the GPIO port, and the switch key at least comprises a first switch S1 and a second switch S2.

Further, a first end of the first voltage-dividing resistor R0 is connected to a power supply voltage, second ends of the first voltage-dividing resistor R0 are respectively connected to the ADC port, the first end of the first diode D1, the second end of the second diode D2, the first end of the second voltage-dividing resistor R1, and the first end of the third voltage-dividing resistor R2, a second end of the first diode D1 is grounded, a second end of the second voltage-dividing resistor R1 is connected to the first end of the first switch S1, a second end of the first switch S1 is grounded, a second end of the third voltage-dividing resistor R2 is connected to the first end of the second switch S2, and a second end of the second switch S2 is grounded.

Further, the first switch S1 is a TVS transistor, and the second switch S2 is a schottky diode.

Further, the voltage divider further comprises a fourth voltage dividing resistor R3, a third switch S3, a fifth voltage dividing resistor R4, a fourth switch S4, a sixth voltage dividing resistor R5, a fifth switch S5, a seventh voltage dividing resistor R6 and a sixth switch S6, wherein the second end of each switch is grounded, the first end of each switch is connected with the second end of the corresponding switch, and the third voltage dividing resistor R2 to the seventh voltage dividing resistor R6 are sequentially connected.

Drawings

Fig. 1 is a schematic diagram of the circuit structure of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present invention.

It will be understood by those skilled in the art that in the present disclosure, the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in an orientation or positional relationship indicated in the drawings for ease of description and simplicity of description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus, the above terms should not be construed as limiting the present invention.

In the prior art, a plurality of paths of GPIOs or a special keyboard control chip is commonly used for realizing the control of a plurality of paths of keys, the GPIOs need a plurality of paths of GPIOs, and the requirement on hardware resources is high; the ADC is purely realized, the ADC data is required to be read in a polling mode, the system cost is high, reading is not realized under the condition of system dormancy, mainly because keys are trigger events and the time is short, the ADC cannot be read in an interruption mode, if reading is not carried out in an interruption mode, the ADC data is required to be read every 1-3 ms to ensure that key events are not lost, even if no key events exist, the system is required to continuously read the ADC, the waste of system resources is caused, the power consumption of all ADC function modules is in an mA level, as mentioned above, the system key events are required to be ensured not to be lost, even if the system is in a dormant state, the ADC function cannot be closed, the system power consumption is high, and if the ADC function is closed, the power consumption is reduced, but awakening is not carried out through keys.

The following embodiments are proposed for this purpose:

as shown in FIG. 1, the multi-key control circuit based on the GPIO and the ADC comprises a processor provided with a GPIO port and an ADC port, and a plurality of switch keys, voltage-dividing resistors and protection diodes which are electrically connected with the GPIO port and the ADC port. The voltage dividing resistor comprises a first voltage dividing resistor R0, a second voltage dividing resistor R1 and a third voltage dividing resistor R2, the diodes at least comprise a first diode D1 for protecting the ADC port and a second diode D2 for isolating the ADC port and the GPIO port, and the key switch at least comprises a first switch S1 and a second switch S2. Wherein the processor may be a CPU or MCU.

In this embodiment, a first end of the first voltage-dividing resistor R0 is connected to the power supply voltage VDD, second ends of the first voltage-dividing resistor R0 and the third voltage-dividing resistor R2 are respectively connected to the ADC port, a first end of the first diode D1, a second end of the second diode D2, a first end of the second voltage-dividing resistor R1, and a first end of the third voltage-dividing resistor R2, a second end of the first diode D1 is grounded, a second end of the second voltage-dividing resistor R1 is connected to the first end of the first switch S1, a second end of the first switch S1 is grounded, a second end of the third voltage-dividing resistor R2 is connected to the first end of the second switch S2, and a second end of the second switch S2 is grounded. The switch further comprises a fourth voltage-dividing resistor R3, a third switch S3, a fifth voltage-dividing resistor R4, a fourth switch S4, a sixth voltage-dividing resistor R5, a fifth switch S5, a seventh voltage-dividing resistor R6 and a sixth switch S6, the second end of each switch is grounded, the first end of each switch is connected with the second end of the corresponding switch, and the third voltage-dividing resistor R2 to the seventh voltage-dividing resistor R6 are sequentially connected.

In this embodiment, the GPIO includes a general GPIO with interrupt function, a 10-bit ADC port, a plurality of buttons, a protection diode, and voltage dividing resistors, such as voltage dividing resistors R0, R1, R2, R3, R4, R5, and R6, which mainly perform voltage dividing functions, and S1, S2, S3, S4, S5, and S6 are corresponding switch keys. Of course, R7, R8, and the like, S7, S8, and the like may be included.

Under the normal condition, GPIO work is in a pull-up input interrupt mode, ADC work is in a close mode, when a key is pressed outside, GPIO interrupt response is carried out, an ADC function is started in an interrupt program, the GPIO mode is switched to be a high-resistance input mode, when data are read, the switch key input is judged according to ADC data, after the processing is finished, the ADC is closed, the GPIO mode is switched to be a pull-up input mode, a manual button is generally about 10ms, and a CPU or an MPU is awakened to be 3-5 ms, so that the reading function can be interrupted in the dormant state. The first switch S1 is a TVS transistor for protecting the ADC port, and the second switch S2 is a schottky diode for isolating the ADC from the GPIO port and protecting the GPIO port. According to the method, the GPIO interruption function is used, the ADC is turned off in a sleep mode, the GPIO interruption is made, when a key event occurs, the GPIO interruption is triggered firstly, then the ADC function is turned on to read a key value, and meanwhile the problems of low power consumption and awakening are solved.

When the first switch S1 is pressed, the ADC port voltage is Vadc — R1/(R0+ R1) × VDD;

when the second switch S2 is pressed, the ADC port voltage is Vadc — R2/(R0+ R2) × VDD;

by analogy, when the nth switch Sn is pressed, the voltage at the ADC port is Vadc ═ Rn/(R0+ Rn) × VDD; rn is the n +1 th divider resistance.

The present invention is not described in detail in the prior art, and therefore, the present invention is not described in detail.

It is understood that the terms "a" and "an" should be interpreted as meaning that a number of one element or element is one in one embodiment, while a number of other elements is one in another embodiment, and the terms "a" and "an" should not be interpreted as limiting the number.

Although the use of the term in the present text is used more often, the possibility of using other terms is not excluded. These terms are used merely to more conveniently describe and explain the nature of the present invention; they are to be construed as being without limitation to any additional limitations that may be imposed by the spirit of the present invention.

The present invention is not limited to the above-mentioned preferred embodiments, and any other products in various forms can be obtained by anyone in the light of the present invention, but any changes in the shape or structure thereof, which have the same or similar technical solutions as the present application, fall within the protection scope of the present invention.

Claims

1. A multi-key control circuit based on a GPIO and an ADC is characterized by comprising a processor provided with a GPIO port and an ADC port, and a plurality of switch keys, a divider resistor and a protection diode which are electrically connected with the GPIO port and the ADC port; the GPIO port has an interrupt function.

2. The GPIO and ADC based multi-key control circuit of claim 1, wherein the voltage divider resistors comprise at least a first voltage divider resistor R0, a second voltage divider resistor R1 and a third voltage divider resistor R2, the protection diodes comprise at least a first diode D1 for protecting the ADC port and a second diode D2 for isolating the ADC port from the GPIO port, and the switch keys comprise at least a first switch S1 and a second switch S2.

3. The GPIO and ADC based multi-key control circuit as claimed in claim 2, wherein a first terminal of said first voltage dividing resistor R0 is connected to a power supply voltage, a second terminal is connected to said ADC port, a first terminal of said first diode D1, a second terminal of said second diode D2, a first terminal of said second voltage dividing resistor R1 and a first terminal of said third voltage dividing resistor R2, a second terminal of said first diode D1 is grounded, a second terminal of said second voltage dividing resistor R1 is connected to a first terminal of said first switch S1, a second terminal of said first switch S1 is grounded, a second terminal of said third voltage dividing resistor R2 is connected to a first terminal of said second switch S2, and a second terminal of said second switch S2 is grounded.

4. The GPIO and ADC based multi-key control circuit as claimed in claim 2 or 3, wherein the first switch S1 is a TVS transistor and the second switch S2 is a Schottky diode.

5. The multi-key control circuit based on GPIO and ADC as claimed in claim 4, further comprising a fourth voltage dividing resistor R3 and a third switch S3, a fifth voltage dividing resistor R4 and a fourth switch S4, a sixth voltage dividing resistor R5 and a fifth switch S5, and a seventh voltage dividing resistor R6 and a sixth switch S6, wherein a second end of each switch is grounded, a first end of each switch is connected with a second end of the corresponding switch, and the third voltage dividing resistor R2 to the seventh voltage dividing resistor R6 are connected in sequence.