CN216646740U - Test circuit and device of multi-channel digital isolator - Google Patents
Test circuit and device of multi-channel digital isolator Download PDFInfo
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- CN216646740U CN216646740U CN202123308469.6U CN202123308469U CN216646740U CN 216646740 U CN216646740 U CN 216646740U CN 202123308469 U CN202123308469 U CN 202123308469U CN 216646740 U CN216646740 U CN 216646740U
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Abstract
The utility model relates to the field of digital isolators, and provides a test circuit of a multi-channel digital isolator, which comprises: the multi-channel test seat is used for placing the multi-channel digital isolator; the PWM signal module is used for outputting a PWM signal to the multi-channel test seat and receiving a test signal; and the voltage division module comprises a resistor arranged on each channel of the multi-channel test seat, is connected with the PWM signal module and the multi-channel test seat, and is used for forming a bidirectional transmission channel of the PWM signal module and the multi-channel test seat so as to test the multi-channel digital isolators of different types. The utility model can realize the power-on test of the digital isolator and has the advantages of simple circuit, good compatibility, flexible application, less system test investment, wide application range and the like. Different test sockets can be adopted according to different product packaging sizes.
Description
Technical Field
The utility model relates to the field of digital isolators, in particular to a test circuit and a test device of a multi-channel digital isolator.
Background
The multi-channel digital isolator has a one-way and two-way difference, and in order to verify the reliability of a product, power-on aging tests are required to be carried out on each channel. In order to perform a comprehensive burn-in test on different products with the same package size, each product corresponds to one test board; or one test board corresponds to a plurality of models of products, and a relay or an electronic switch is added on the test board for switching, so that the compatibility of multiple models is realized.
The multi-channel digital isolators with the same packaging size have a plurality of models, and the directions of all channels of products with different models are different. When each product is subjected to a burn-in test or a reliability verification test, a corresponding test board is usually required to be designed. In order to improve the compatibility of the test board with the product model, a relay or an electronic switch is usually added on the test board for switching, and the test board has the disadvantages of complex circuit design, high cost and easy error.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a test circuit and a test device for a multi-channel digital isolator, which solve the problems of complex circuit, high cost and incompatibility when aging tests are carried out on different types of digital isolators.
The technical scheme provided by the utility model is as follows:
a test circuit for a multi-channel digital isolator, comprising:
the multi-channel test seat is used for placing the multi-channel digital isolator;
the PWM signal module is used for outputting a PWM signal to the multi-channel test seat and receiving a test signal;
and the voltage division module comprises a resistor arranged on each channel of the multi-channel test seat, is connected with the PWM signal module and the multi-channel test seat, and is used for forming a bidirectional transmission channel of the PWM signal module and the multi-channel test seat so as to test the multi-channel digital isolators of different types.
Further preferably, the PWM signal module includes:
the first PWM signal circuit is used for inputting a first PWM signal or outputting a second test signal;
and the second PWM signal circuit is used for inputting a second PWM signal or outputting a first test signal.
Further preferably, the voltage dividing module includes a first voltage dividing circuit and a second voltage dividing circuit;
the first voltage division circuit is connected with the multi-channel test socket and the first PWM signal circuit, is used for forming a first transmission channel of the multi-channel test chip and the first PWM signal circuit, and inputs the first PWM signal or outputs the second test signal;
the second voltage division circuit is connected with the multi-channel test socket and the second PWM signal circuit, is used for forming a second transmission channel of the multi-channel test chip and the second PWM signal circuit, and inputs the second PWM signal or outputs the first test signal.
Further preferably:
the first PWM signal circuit comprises a first PWM port and is used for inputting the first PWM signal;
the first voltage division circuit comprises a first resistor and a second resistor which are arranged on each channel of the multi-channel test socket, and the first resistor and the second resistor on each channel are connected with the first PWM port and used for isolating and inputting the first PWM signal to a plurality of channels of the multi-channel test socket;
the second voltage division circuit comprises a third resistor and a fourth resistor which are arranged on each channel of the multi-channel test socket, and the third resistor and the fourth resistor on each channel are connected with the second PWM port and used for isolating and outputting the first test signal to the second PWM signal circuit;
the second PWM signal circuit includes a second PWM port for outputting the first test signal.
Further preferably:
the second PWM signal circuit comprises a second PWM port and is used for inputting the second PWM signal;
the second voltage division circuit comprises a third resistor and a fourth resistor which are arranged on each channel of the multi-channel test socket, and the third resistor and the fourth resistor on each channel are connected with the second PWM port and used for isolating and inputting the second PWM signal to a plurality of channels of the multi-channel test socket;
the first PWM signal circuit comprises a first PWM port and is used for outputting the second test signal;
the first voltage division circuit comprises a first resistor and a second resistor which are arranged on each channel of the multi-channel test socket, and the first resistor and the second resistor on each channel are connected with the first PWM port and used for isolating and outputting the second test signal to the first PWM signal circuit.
Further preferably:
the first PWM signal circuit comprises a plurality of first PWM ports and is used for inputting a first PWM signal corresponding to each channel in the multi-channel test socket;
the first voltage division circuit comprises a first resistor and a second resistor which are arranged on each channel of the multi-channel test socket, and the first resistor and the second resistor on each channel are connected with the first PWM port corresponding to each channel and used for isolating and inputting the first PWM signal corresponding to each channel;
the second voltage division circuit comprises a third resistor and a fourth resistor which are arranged on each channel of the multi-channel test socket, and the third resistor and the fourth resistor on each channel are connected with the second PWM port corresponding to each channel and used for isolating and outputting the first test signal corresponding to each channel to the first PWM signal circuit;
the second PWM signal circuit includes a plurality of second PWM ports for outputting the first test signal corresponding to each channel in the multi-channel test socket.
Further preferably:
the second PWM signal circuit comprises a plurality of second PWM ports and is used for inputting a second PWM signal corresponding to each channel in the multi-channel test socket;
the second voltage division circuit comprises a third resistor and a fourth resistor which are arranged on each channel of the multi-channel test socket, and the third resistor and the fourth resistor on each channel are connected with the second PWM port corresponding to each channel and used for isolating and inputting the second PWM signal corresponding to each channel to the multi-channel test socket;
the first PWM signal circuit includes a plurality of first PWM ports, and is configured to output the second test signal corresponding to each channel;
the first voltage division circuit comprises a first resistor and a second resistor which are arranged on each channel of the multi-channel test socket, and the first resistor and the second resistor on each channel are connected with the first PWM port corresponding to each channel and used for isolating and outputting the second test signal corresponding to each channel to the first PWM signal circuit.
Further preferably, the method further comprises the following steps:
the first capacitor is connected with a first power supply end and a power supply of the multi-channel test socket;
and the second capacitor is connected with a second power supply end of the multichannel test socket and the power supply.
A testing device of a multi-channel digital isolator comprises a testing circuit of the multi-channel digital isolator.
The test circuit and the test device for the multi-channel digital isolator have the following beneficial effects that:
the utility model can realize the power-on test of the digital isolator and has the advantages of simple circuit, good compatibility, flexible application, less system test investment, wide application range and the like. Different test sockets can be adopted according to different product packaging sizes.
Drawings
The above features, technical features, advantages and implementations of a multi-channel digital isolator test circuit and apparatus are further described in the following detailed description of preferred embodiments in a clearly understandable manner, in conjunction with the accompanying drawings.
FIG. 1 is a schematic diagram of one embodiment of a test circuit for a multi-channel digital isolator in the present invention;
FIG. 2 is a prior art multi-channel digital isolator;
FIG. 3 is a schematic diagram of another embodiment of a test circuit for a multi-channel digital isolator in accordance with the present invention;
FIG. 4 is a schematic diagram of yet another embodiment of a test circuit for a multi-channel digital isolator in accordance with the present invention;
FIG. 5 is a schematic diagram of yet another embodiment of a test circuit for a multi-channel digital isolator according to the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
In addition, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not intended to indicate or imply relative importance.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will be made with reference to the accompanying drawings. It is obvious that the drawings in the following description are only some examples of the utility model, and that for a person skilled in the art, other drawings and embodiments can be derived from them without inventive effort.
Example one
In an embodiment of the present invention, a test circuit of a multi-channel digital isolator is shown in fig. 1, and includes:
and the multi-channel test seat 1 is used for placing the multi-channel digital isolator.
And the PWM signal module 2 is used for outputting PWM signals to the multi-channel test seat and receiving test signals.
And the voltage division module 3 comprises a resistor arranged on each channel of the multi-channel test seat, is connected with the PWM signal module and the multi-channel test seat, and is used for forming a bidirectional transmission channel of the PWM signal module and the multi-channel test seat so as to test multi-channel digital isolators of different types.
In this embodiment, the multi-channel test socket 1 can accommodate different types of digital isolators of the same package size.
In practical scenarios, multi-channel digital isolators with the same package size but different types often have the problem of opposite channel directions.
If the burn-in test or the reliability test is performed by using the conventional test method, a corresponding test board is usually designed for the different types of multi-channel digital isolator products. In order to improve the compatibility of the test board with the product model, a relay or an electronic switch is usually added on the test board for switching, and the test board has the disadvantages of complex circuit design, high cost and easy error.
By the test circuit of the multi-channel digital isolator, the aging test and the reliability test of different types of digital isolators with uniform packaging specifications, which are simple in circuit, low in cost, good in compatibility and flexible to use, can be realized.
Example two
Based on the foregoing embodiments, parts of the present embodiment that are the same as those of the foregoing embodiments are not repeated, and the present embodiment provides a test circuit for a multi-channel digital isolator, as shown in fig. 3, which specifically includes:
the PWM signal module 2 includes:
the first PWM signal circuit 21 is used for inputting the first PWM signal or outputting the second test signal.
And a second PWM signal circuit 22 for inputting the second PWM signal or outputting the first test signal.
The voltage dividing module 3 includes a first voltage dividing circuit and a second voltage dividing circuit.
The first voltage divider circuit 31 is connected to the multi-channel test socket and the first PWM signal circuit, and configured to form a first transmission channel between the multi-channel test chip and the first PWM signal circuit, and input the first PWM signal or output the second test signal.
The second voltage divider circuit 32 is connected to the multi-channel test socket and the second PWM signal circuit, and configured to form a second transmission channel between the multi-channel test chip and the second PWM signal circuit, and input the second PWM signal or output the first test signal.
Illustratively, two six-channel digital isolators (a and b) having the same package size but different types, and two four-channel digital isolators (c and d) having the same package size but different types, are shown in FIG. 2. Wherein the direction of the channel (A, B, C) of the six-channel digital isolator (a) is the same as that of the six-channel digital isolator (b), but the direction of the channel (D, E, F) is opposite. The channels (A, B) of the four-channel digital isolators (c and d) are identical, but the direction of the channels (C, D) is opposite.
When a burn-in test or a reliability test is performed by using a conventional test method, it is usually necessary to design corresponding test boards for the six-channel digital isolator (a) and the six-channel digital isolator (b) products. In order to improve the compatibility of the test board with the product model, a relay or an electronic switch is usually added on the test board for switching, and the test board has the disadvantages of complex circuit design, high cost and easy error.
The present embodiment provides the following circuit design, as shown in fig. 4:
illustratively, two different types of six-channel digital isolators (a and b) having the same package size as shown in FIG. 2 are placed on a multi-channel test socket that includes a chip (U1) when the six-channel digital isolators (a, b) are burn-in tested.
In this embodiment, the first PWM signal circuit 21 includes a first PWM port (PWM1) for inputting the first PWM signal.
The first voltage division circuit 31 comprises first resistors (R1-R6) and second resistors (R13-R18) arranged on each channel of the multi-channel test socket, wherein the first resistors (R1-R6) and the second resistors (R13-R18) on each channel are connected with the first PWM port (PWM1) and used for isolating and inputting the first PWM signal to the plurality of channels of the multi-channel test socket.
When the six-channel digital isolator (b) is tested, the plurality of channels of the multi-channel test socket are six channels (VIA-VIF).
When the six-channel digital isolator (a) is tested, the plurality of channels of the multi-channel test socket are six channels (VIA-VIF).
The second voltage division circuit 32 comprises third resistors (R7-R12) and fourth resistors (R19-R24) arranged on each channel of the multi-channel test socket, and the third resistors (R7-R12) and the fourth resistors (R19-R24) on each channel are connected with the second PWM port (PWM2) and used for isolating and outputting the first test signal to the second PWM signal circuit 22.
The second PWM signal circuit includes a second PWM port (PWM2) for outputting the first test signal.
In this embodiment, the second PWM signal circuit may be used as an input, and the first PWM signal circuit may be used as an output.
Illustratively, the second PWM signal circuit 22 includes a second PWM port (PWM2) for inputting the second PWM signal.
The second voltage division circuit 32 comprises third resistors (R7-R12) and fourth resistors (R19-R24) arranged on each channel of the multi-channel test socket, wherein the third resistors (R7-R12) and the fourth resistors (R19-R24) on each channel are connected with a port of the second PWM (PWM2) and used for isolating and inputting the second PWM signals to a plurality of channels of the multi-channel test socket (U1).
When the six-channel digital isolator (b) is tested, the plurality of channels of the multi-channel test socket are six channels (VIA-VIF).
When the six-channel digital isolator (a) is tested, the plurality of channels of the multi-channel test socket are six channels (VIA-VIF).
The first PWM signal circuit 21 includes a first PWM port (PWM1) for outputting the second test signal.
The first voltage division circuit 21 comprises first resistors (R1-R6) and second resistors (R13-R18) arranged on each channel of the multi-channel test socket, and the first resistors (R1-R6) and the second resistors (R13-R18) on each channel are connected with the first PWM port (PWM1) and used for isolating and outputting the second test signal to the first PWM signal circuit 21.
The first test signal and the second test signal refer to signals output after testing each channel of the digital isolator, and the aging result or the reliability result of the digital isolator is judged according to the first test signal and the second test signal.
FIG. 4 is a proposed multi-channel digital isolator burn-in test scheme, where U1 is a common six-channel test socket. The input/output port of each channel to the left of the six-channel test socket in fig. 4 is connected to port (PWM1 signal) and port (GND1) by a series resistor, and the input/output port of each channel to the right of the six-channel test socket in fig. 4 is connected to port (PWM2 signal) and port (GND2) by a series resistor.
In this embodiment, the method further includes:
and the first capacitor (C1) is connected with the first power supply end and the power supply of the multi-channel test socket.
And the second capacitor (C2) is connected with the second power supply end of the multi-channel test socket and the power supply.
In this embodiment, each port on the left and right sides of the multi-channel test socket (U1) can be used as both an input channel and an output channel, thereby realizing compatible sharing of digital isolators with the same package size and different types during burn-in test or reliability test.
EXAMPLE III
Based on the foregoing embodiments, the same parts as those in the foregoing embodiments are not repeated in detail in this embodiment, and this embodiment provides a test circuit for a multi-channel digital isolator, where:
FIG. 5 is another proposed multi-channel digital isolator burn-in test scheme, in which the device (U2) is a conventional six-channel test socket.
The input/output port of each channel on the left side of the six-channel test socket in fig. 5 is connected to the PWM signal port (PWM1) and the port (GND1) through a series resistor, and the input/output port of each channel on the right side of the six-channel test socket in fig. 5 is connected to the PWM signal port (PWM2) and the port (GND2) through a series resistor.
Specifically, each port on the left side and the right side of the multi-channel test socket (U2) can be used as an input channel and an output channel, so that the digital isolators with the same package size and different types can be compatible and shared during aging test or reliability test.
Illustratively, as shown in fig. 5, the first PWM signal circuit 21 includes a plurality of first PWM ports (PWM 11-PWM 16) for inputting the first PWM signals corresponding to each channel of the multi-channel test socket.
The first voltage division circuit 31 comprises first resistors (R25-R30) and second resistors (R37-R42) arranged on each channel of the multi-channel test socket, wherein the first resistors (R25-R30) and the second resistors (R37-R42) on each channel are connected with first PWM ports (PWM 11-PWM 16) corresponding to each channel, and are used for isolating and inputting first PWM signals corresponding to each channel.
The second voltage division circuit 32 comprises third resistors (R31-R36) and fourth resistors (R43-R48) arranged on each channel of the multi-channel test socket, wherein the third resistors (R31-R36) and the fourth resistors (R43-R48) on each channel are connected with the second PWM ports (PWM 21-PWM 26) corresponding to each channel, and are used for isolating and outputting the first test signal corresponding to each channel to the first PWM signal circuit 21.
The second PWM signal circuit 22 includes a plurality of second PWM ports (PWM 11-PWM 16) for outputting the first test signal corresponding to each channel of the multi-channel test socket.
The second PWM signal circuit 22 includes a plurality of second PWM ports (PWM 21-PWM 26) for inputting a second PWM signal corresponding to each channel of the multi-channel test socket (U2).
The second voltage division circuit 32 comprises third resistors (R31-R36) and fourth resistors (R43-R48) arranged on each channel of the multi-channel test socket, and the third resistors (R31-R36) and the fourth resistors (R43-R48) on each channel are connected with the corresponding second PWM port of each channel, so as to isolate and input the second PWM signal corresponding to each channel to the multi-channel test socket.
The first PWM signal circuit 21 includes a plurality of first PWM ports (PWM 11-PWM 16) for outputting the second test signal corresponding to each channel.
The first voltage division circuit 31 includes first resistors (R25-R30) and second resistors (R37-R42) disposed on each channel of the multi-channel test socket, and the first resistors (R25-R30) and the second resistors (R37-R42) on each channel are connected to the first PWM port corresponding to each channel, and are configured to separately output the second test signal corresponding to each channel to the first PWM signal circuit 21.
Any port of the first PWM signal circuit may be used as an input or an output, and any port of the second PWM signal circuit may also be used as an output or an input.
When the first PWM ports (PWM 11-PWM 13) of the first PWM signal circuit 21 are used as inputs, (PWM 14-PWM 16) are used as outputs, the second PWM ports (PWM 21-PWM 23) of the second PWM signal circuit 22 are used as outputs, (PWM 24-PWM 26) are used as inputs, the test circuit can be used for the aging test or the reliability test of the six-channel digital isolator (a) in fig. 2.
When the first PWM ports (PWM 11-PWM 16) of the first PWM signal circuit 21 are used as input and the second PWM ports (PWM 21-PWM 26) of the second PWM signal circuit 22 are used as output, the aging test or the reliability test of the six-channel digital isolator (b) in fig. 2 can be performed.
Specifically, the PWM signal may be sent according to the transmission direction of each channel of the digital isolator, so that the test circuit of the multi-channel digital isolator of the present embodiment is compatible with the burn-in test or the reliability test of the digital isolators with the same package specification and different types.
In this embodiment, the method further includes:
and the first capacitor (C3) is connected with the first power supply end and the power supply of the multi-channel test socket.
And the second capacitor (C4) is connected with the second power supply end of the multi-channel test socket and the power supply.
In this embodiment, specifically, each port on the left and right sides of the multi-channel test socket may be used as an input channel or an output channel, so as to implement compatible sharing of digital isolators with the same package size and different types during aging test or reliability test.
The circuit of the embodiment can realize the power-on test of the digital isolator, and has the advantages of simple circuit, good compatibility, flexible application, less system test investment, wide application range and the like. Different test sockets can be adopted according to different product packaging sizes.
Example four
Based on the foregoing embodiments, parts of the present embodiment that are the same as those of the foregoing embodiments are not repeated, and this embodiment provides a testing apparatus for a multi-channel digital isolator, including a testing circuit for the multi-channel digital isolator.
The reliability testing circuit provided by the device can realize the power-on test of the digital isolator, and has the advantages of simple circuit, good compatibility, flexible application, less system testing investment, wide application range and the like. Different test sockets can be adopted according to different product packaging sizes.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of program modules is illustrated, and in practical applications, the above-described distribution of functions may be performed by different program modules, that is, the internal structure of the apparatus may be divided into different program units or modules to perform all or part of the above-described functions. Each program module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one processing unit, and the integrated unit may be implemented in a form of hardware, or may be implemented in a form of software program unit. In addition, the specific names of the program modules are only used for distinguishing the program modules from one another, and are not used for limiting the protection scope of the application.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or recited in detail in a certain embodiment.
Those of ordinary skill in the art will appreciate that the elements of the examples described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed system may be implemented in other ways. The above-described embodiments are merely illustrative, and the division of the modules or units is merely illustrative, and the actual implementation may have another division, and a plurality of units or components may be combined or integrated into another system, or some features may be omitted or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (9)
1. A test circuit for a multi-channel digital isolator, comprising:
the multi-channel test seat is used for placing the multi-channel digital isolator;
the PWM signal module is used for outputting a PWM signal to the multi-channel test seat and receiving a test signal;
and the voltage division module comprises a resistor arranged on each channel of the multi-channel test seat, is connected with the PWM signal module and the multi-channel test seat, and is used for forming a bidirectional transmission channel of the PWM signal module and the multi-channel test seat so as to test the multi-channel digital isolators of different types.
2. The test circuit of the multi-channel digital isolator of claim 1, wherein the PWM signal module comprises:
the first PWM signal circuit is used for inputting a first PWM signal or outputting a second test signal;
and the second PWM signal circuit is used for inputting a second PWM signal or outputting a first test signal.
3. The test circuit of the multi-channel digital isolator according to claim 2, wherein the voltage dividing module comprises a first voltage dividing circuit and a second voltage dividing circuit;
the first voltage division circuit is connected with the multi-channel test socket and the first PWM signal circuit, is used for forming a first transmission channel of the multi-channel test chip and the first PWM signal circuit, and inputs the first PWM signal or outputs the second test signal;
the second voltage division circuit is connected with the multi-channel test socket and the second PWM signal circuit, is used for forming a second transmission channel of the multi-channel test chip and the second PWM signal circuit, and inputs the second PWM signal or outputs the first test signal.
4. The test circuit of the multi-channel digital isolator of claim 3, wherein:
the first PWM signal circuit comprises a first PWM port and is used for inputting the first PWM signal;
the first voltage division circuit comprises a first resistor and a second resistor which are arranged on each channel of the multi-channel test socket, and the first resistor and the second resistor on each channel are connected with the first PWM port and used for isolating and inputting the first PWM signal to a plurality of channels of the multi-channel test socket;
the second voltage division circuit comprises a third resistor and a fourth resistor which are arranged on each channel of the multi-channel test socket, and the third resistor and the fourth resistor on each channel are connected with the second PWM port and used for isolating and outputting the first test signal to the second PWM signal circuit;
the second PWM signal circuit includes a second PWM port for outputting the first test signal.
5. The test circuit of the multi-channel digital isolator of claim 4, wherein:
the second PWM signal circuit comprises a second PWM port and is used for inputting the second PWM signal;
the second voltage division circuit comprises a third resistor and a fourth resistor which are arranged on each channel of the multi-channel test socket, and the third resistor and the fourth resistor on each channel are connected with the second PWM port and used for isolating and inputting the second PWM signal to a plurality of channels of the multi-channel test socket;
the first PWM signal circuit comprises a first PWM port and is used for outputting the second test signal;
the first voltage division circuit comprises a first resistor and a second resistor which are arranged on each channel of the multi-channel test socket, and the first resistor and the second resistor on each channel are connected with the first PWM port and used for isolating and outputting the second test signal to the first PWM signal circuit.
6. The test circuit of the multi-channel digital isolator of claim 3, wherein:
the first PWM signal circuit comprises a plurality of first PWM ports and is used for inputting a first PWM signal corresponding to each channel in the multi-channel test socket;
the first voltage division circuit comprises a first resistor and a second resistor which are arranged on each channel of the multi-channel test socket, and the first resistor and the second resistor on each channel are connected with the first PWM port corresponding to each channel and used for isolating and inputting the first PWM signal corresponding to each channel;
the second voltage division circuit comprises a third resistor and a fourth resistor which are arranged on each channel of the multi-channel test socket, and the third resistor and the fourth resistor on each channel are connected with the second PWM port corresponding to each channel and used for isolating and outputting the first test signal corresponding to each channel to the first PWM signal circuit;
the second PWM signal circuit includes a plurality of second PWM ports for outputting the first test signal corresponding to each channel in the multi-channel test socket.
7. The test circuit of the multi-channel digital isolator of claim 6, wherein:
the second PWM signal circuit comprises a plurality of second PWM ports and is used for inputting a second PWM signal corresponding to each channel in the multi-channel test socket;
the second voltage division circuit comprises a third resistor and a fourth resistor which are arranged on each channel of the multi-channel test socket, and the third resistor and the fourth resistor on each channel are connected with the second PWM port corresponding to each channel and used for isolating and inputting the second PWM signal corresponding to each channel to the multi-channel test socket;
the first PWM signal circuit includes a plurality of first PWM ports, and is configured to output the second test signal corresponding to each channel;
the first voltage division circuit comprises a first resistor and a second resistor which are arranged on each channel of the multi-channel test socket, and the first resistor and the second resistor on each channel are connected with the first PWM port corresponding to each channel and used for isolating and outputting the second test signal corresponding to each channel to the first PWM signal circuit.
8. The test circuit of the multi-channel digital isolator of claim 5 or 6, further comprising:
the first capacitor is connected with a first power supply end and a power supply of the multi-channel test socket;
and the second capacitor is connected with a second power supply end of the multi-channel test socket and the power supply.
9. A test apparatus for a multi-channel digital isolator, comprising a test circuit for a multi-channel digital isolator according to any one of claims 1 to 8.
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| CN116047271A (en) * | 2023-01-16 | 2023-05-02 | 荣湃半导体（上海）有限公司 | Automatic test system and automatic test method |
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