CN217116234U - Video signal expansion circuit and expansion device - Google Patents
Video signal expansion circuit and expansion device Download PDFInfo
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- CN217116234U CN217116234U CN202220809713.2U CN202220809713U CN217116234U CN 217116234 U CN217116234 U CN 217116234U CN 202220809713 U CN202220809713 U CN 202220809713U CN 217116234 U CN217116234 U CN 217116234U
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Abstract
The utility model provides a video signal expansion circuit and expansion equipment, which comprises a processor, a FPGA chip and a differential circuit; the processor is connected with the FPGA chip and is used for outputting a DSI video signal to the FPGA chip, wherein the DSI video signal is a double-picture video signal; the FPGA chip is respectively connected with a first display and the differential circuit, and is used for converting the DSI video signal into a first video signal and a second video signal and respectively outputting the first video signal and the second video signal to the first display and the differential circuit; the differential circuit is connected with a second display and used for converting the second video signal into a differential signal and outputting the differential signal to the second display. The utility model discloses can convert double-picture video signal into first video signal and second video signal, and export the display to the difference respectively, need not to convert bridging chip's support, improved the convenience.
Description
Technical Field
The utility model relates to the field of electronic technology, concretely relates to video signal expander circuit and expansion equipment.
Background
In practical applications, an application situation is often encountered in which a device host needs to output multiple video signals to drive multiple displays or to display different pictures on other devices, for example, a dual-picture video signal is respectively output to different displays, and the picture of each display is different. The existing mode of outputting multiple video signals is that one video channel outputs one video signal, and multiple video channels are needed for outputting multiple video signals. The number of the video output channels of the device host is limited, and when the number of the display pictures is larger than that of the video output channels of the device host, the requirements cannot be met frequently.
SUMMERY OF THE UTILITY MODEL
The utility model provides a video signal expander circuit and expansion device can directly cut apart the output to the video signal of double picture, need not other conversion bridging chip, the cost is reduced.
In a first aspect, the present invention provides a video signal expansion circuit, which includes a processor, an FPGA chip, and a differential circuit; the processor is connected with the FPGA chip and is used for outputting a DSI video signal to the FPGA chip, wherein the DSI video signal is a double-picture video signal; the FPGA chip is respectively connected with a first display and the differential circuit, and is used for converting the DSI video signal into a first video signal and a second video signal and respectively outputting the first video signal and the second video signal to the first display and the differential circuit; the differential circuit is connected with a second display and used for converting the second video signal into a differential signal and outputting the differential signal to the second display.
Furthermore, the FPGA chip comprises a DSI video signal receiving module, and a first video signal output module and a second video signal output module which are connected with the DSI video signal receiving module;
the DSI video signal receiving module is further connected with the processor, the first video signal output module is connected with the first display, and the second video signal output module is connected with the differential circuit.
Furthermore, the differential circuit comprises a sequential circuit and at least one data circuit, one end of the sequential circuit and one end of the data circuit are both connected with the second video signal output module, and the other end of the sequential circuit and the other end of the data circuit are both connected with the second display.
Furthermore, the second video signal output module comprises a first output submodule and a second output submodule, one end of each of the first output submodule and the second output submodule is connected with the DSI video signal receiving module, and the other end of each of the first output submodule and the second output submodule is connected with the sequential circuit and the data circuit.
Further, the differential circuit includes four of the data circuits.
Furthermore, the sequential circuit and the data circuit both comprise a first input end, a second input end, a third input end, a fourth input end, a first output end, a second output end, a first resistor, a second resistor and a filter circuit; the first input end and the third input end are both connected with the second output submodule, the second input end and the fourth input end are both connected with the first output submodule, and the first output end and the second output end are both connected with the second display; the first input end is connected with the filter circuit through the first resistor, the third input end is connected with the filter circuit through the second resistor, and the third input end, the fourth input end, the first output end and the second output end are connected with the filter circuit.
Further, the filter circuit comprises a first capacitor, a second capacitor and a common-mode inductor; two ends of the first capacitor are respectively connected with a third pin and a fourth pin of the common mode inductor, two ends of the second capacitor are respectively connected with a first pin and a second pin of the common mode inductor, and the first pin and the second pin of the common mode inductor are both connected with the second display; and a third pin of the common mode inductor is connected with the first resistor and the second input end, and a fourth pin of the common mode inductor is connected with the second resistor and the fourth input end.
Further, the device also comprises a conversion chip and a memory; the system support module of the FPGA chip is connected with the memory through the conversion chip; the conversion chip is also connected with the processor.
Furthermore, the device also comprises an active clock circuit, and the active clock circuit is connected with the procedure debugging module of the FPGA chip.
In a second aspect, the present invention further provides a video signal expansion device, which includes any one of the video signal expansion circuits described above.
The utility model discloses a video signal expander circuit and expansion device, cut apart the processing through the FPGA chip to the DSI video signal that the treater exported, thereby obtain first video signal and second video signal, and export first video signal to first display, export second video signal to the second display behind the differential circuit, thereby realize accomplishing the cutting apart to two picture video signal under the condition of an FPGA chip, and can export two pictures to different displays respectively, and need not bridging chip conversion format.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without any creative effort.
Fig. 1 is a block diagram of a video signal expansion circuit according to an embodiment of the present invention;
fig. 2 is a block diagram of a video signal expansion circuit according to another embodiment of the present invention;
fig. 3 is a circuit diagram of a differential circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
In addition, the directional terms of the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", and the like, refer to the attached drawings and the direction of the usage of the product. Accordingly, the directional terms used are used for describing and understanding the present invention, and are not used for limiting the present invention. Further, in the drawings, structures that are similar or identical are denoted by the same reference numerals.
Referring to fig. 1 to fig. 3, fig. 1 shows a block diagram of a video signal expansion circuit 100 provided by the present invention, fig. 2 shows a block diagram of a video signal expansion circuit 100 provided by another embodiment of the present invention, and fig. 3 is a circuit diagram of a differential circuit 30 of the present invention. As shown in fig. 1, the video signal expansion circuit 100 includes a processor 10, an FPGA chip 20, and a differential circuit 30; the processor 10 is connected to the FPGA chip 20, and is configured to output a DSI video signal to the FPGA chip 20, where the DSI video signal is a dual-picture video signal; the FPGA chip 20 is connected to the first display 200 and the differential circuit 30, respectively, and is configured to convert the DSI video signal into a first video signal and a second video signal, and output the first video signal and the second video signal to the first display 200 and the differential circuit 30, respectively; the differential circuit 30 is connected to the second display 300, and is configured to convert the second video signal into a differential signal and output the differential signal to the second display 300.
Wherein, the processor 10 supports the composite output of double pictures, that is, when the video signals of two different sources are input into the processor 10, the processor 10 composites the two video signals to obtain the DSI video signal. After obtaining the DSI video signal, the processor 10 outputs the DSI video signal to the FPGA chip 20, and the FPGA chip 20 performs division processing on the DSI video signal to obtain a first video signal and a second video signal, where the first video signal may be an LVDS signal, and the second video signal may be an MIPI signal, or other differential signals. After obtaining the first video signal and the second video signal, the FPGA chip 20 sends the first video signal to the first display 200, and sends the second video signal to the differential circuit 30, and the differential circuit 30 is connected to the second display 300 to synthesize the second video signal, wherein the differential circuit 30 may include a timing circuit 31 and at least one data circuit 32, and the number of the data circuits 32 is determined by the resolution of the second display 300. The second video signal is converted into a differential signal through the differential circuit 30 and output to the second display 300, thereby completing the output of the cut video signal to the first display 200 and the second display 300, respectively.
Referring to fig. 2, in an embodiment, the FPGA chip 20 includes a DSI video signal receiving module 21, and a first video signal output module 22 and a second video signal output module 23 connected to the DSI video signal receiving module 21; the DSI video signal receiving module 21 is further connected to the processor 10, the first video signal output module 22 is connected to the first display 200, and the second video signal output module 23 is connected to the difference circuit 30.
The FPGA chip 20 may include a plurality of functional modules, including but not limited to a DSI video signal receiving module 21, a first video signal output module 22, a second video signal output module 23, and a system support module. The DSI video signal receiving module 21 is configured to receive a DSI video signal sent by the receiving processor 10, and perform a segmentation process on the DSI video signal to obtain a first video signal and a second video signal, respectively output the first video signal and the second video signal to the first video signal output module 22 and the second video signal output module 23, respectively process the first video signal by the first video signal output module 22 and process the second video signal by the second video signal output module 23, finally output the first video signal to the first display 200 by the first video signal output module 22, and output the second video signal to the difference circuit 30 by the second video signal output module 23.
Referring to fig. 3, in a further embodiment, the differential circuit 30 includes a timing circuit 31 and at least one data circuit 32, one end of each of the timing circuit 31 and the data circuit 32 is connected to the second video signal output module 23, and the other end of each of the timing circuit 31 and the data circuit 32 is connected to the second display 300.
In a further embodiment, the second video signal output module 23 includes a first output submodule 231 and a second output submodule 232, one end of each of the first output submodule 231 and the second output submodule 232 is connected to the DSI video signal receiving module 21, and the other end of each of the first output submodule 231 and the second output submodule 232 is connected to the sequential circuit 31 and the data circuit 32.
In a further embodiment, the differential circuit 30 includes four of the data circuits 32.
The first output sub-module 231 and the second output sub-module 232 are respectively connected to a power supply chip, and power supply pins of the connected power supply chip are different, for example, the first output sub-module 231 may be connected to a 2.5V power supply pin of the power supply chip, the second output sub-module 232 may be connected to a 1.2V power supply pin of the power supply chip, and both the first output sub-module 231 and the second output sub-module 232 are connected to the DSI video signal receiving module 21 and receive the second video signal. Meanwhile, the first output submodule 231 and the second output submodule 232 are both connected to the sequential circuit 31 and the data circuit 32, and the sequential circuit 31 is taken as an example for explanation, and the data circuit 32 can be understood by referring to the explanation of the sequential circuit 31. The timing circuit 31 may include two groups of connection terminals, each group of connection terminals includes two input terminals and one output terminal, the two input terminals are connected to the first output submodule 231 and the second output submodule 232, one output terminal is connected to the second display 300, because the voltages output by the first output submodule 231 and the second output submodule 232 are different, for example, the first output submodule 231 outputs 2.5V voltage, the second output submodule 232 outputs 1.2V voltage, and the first output submodule 231 and the second output submodule 232 also synchronously output the timing signal in the second video signal, the timing circuit 31 adjusts the output voltage according to the received 2.5V voltage and 1.2V voltage, so that the voltage output to the second display 300 meets the requirement of the second display 300, and the timing signal is used to ensure accuracy in data transmission. The data circuit 32 is used for transmitting data packets or data signals in the second video signal, and a plurality of data circuits 32 may be provided for different resolutions to improve efficiency in transmitting data, for example, four data circuits 32 and one timing circuit 31 may be provided for a display with 1920 × 1080 resolution.
In a further embodiment, the timing circuit 31 and the data circuit 32 each include a first input a1, a second input a2, a third input A3, a fourth input a4, a first output B1, a second output B2, a first resistor R1, a second resistor R2, and a filter circuit 311; the first input end a1 and the third input end A3 are both connected with the second output submodule 232, the second input end a2 and the fourth input end a4 are both connected with the first output submodule 231, and the first output end B1 and the second output end B2 are both connected with the second display 300; the first input terminal a1 is connected to the filter circuit 311 through the first resistor R1, the third input terminal A3 is connected to the filter circuit 311 through the second resistor R2, and the third input terminal A3 and the fourth input terminal a4, and the first output terminal B1 and the second output terminal B2 are connected to the filter circuit 311.
In a further embodiment, the filter circuit 311 includes a first capacitor C1, a second capacitor C2, and a common mode inductor L1; two ends of the first capacitor C1 are connected to the third pin and the fourth pin of the common mode inductor L1, two ends of the second capacitor C2 are connected to the first pin and the second pin of the common mode inductor L1, and the first pin and the second pin of the common mode inductor L1 are both connected to the second display 300; the third pin of the common mode inductor L1 is connected to the first resistor R1 and the second input terminal a2, and the fourth pin of the common mode inductor L1 is connected to the second resistor R2 and the fourth input terminal a 4.
Taking the timing circuit 31 as an example for illustration, the first input terminal a1 is connected to the second output submodule 232 through a first resistor R1 and is configured to receive a 1.2V voltage, the second input terminal a2 is connected to the first output submodule 231 and is configured to receive a 2.5V voltage, the first input terminal a1 and the second input terminal a2 both receive a timing signal at the same time, the output voltage is adjusted through a first resistor R1, the output voltage is filtered and protected through the filter circuit 311, and finally the voltage is output to the second display 300 through the first output terminal B1, the principle of the third input terminal A3, the fourth input terminal a4, and the second output terminal B2 may refer to the first input terminal a1, the second input terminal a2, and the first output terminal B1, wherein the resistances of the first resistor R1 and the second resistor R2 may be 49.5 ohms. The filter circuit 311 may include a first capacitor C1, a second capacitor C2, and a common mode inductor L1, and the output voltage is protected and filtered by the combination of the first capacitor C1, the second capacitor C2, and the common mode inductor L1.
In a further embodiment, the system further comprises a conversion chip and a memory; the system support module of the FPGA chip 20 is connected to the memory through the conversion chip; the conversion chip is also connected to the processor 10.
The memory may include a program required by the FPGA when running, for example, a DSI video signal is divided, a system support module of the FPGA chip 20 is connected to the memory through a conversion chip, and may read the program in the memory, meanwhile, the conversion chip may also be connected to the processor 10, and the processor 10 may upgrade the program in the memory through the conversion chip.
In a further embodiment, the system further comprises an active clock circuit, and the active clock circuit is connected with the process debugging module of the FPGA chip 20.
The active clock circuit is used for controlling the time sequence of the procedure debugging module and ensuring the orderly work of the FPGA chip 20.
The utility model also discloses a look screen signal expansion equipment, including any of the aforesaid video signal extension circuit 100.
The utility model discloses a video signal expander circuit and expansion device can cut the DSI video signal of double-picture through a FPGA chip to first video signal and second video signal after will cutting export respectively to first display and second display, thereby realize exporting two-sided video signal to different displays respectively, and need not other conversion bridging chip support, improved the convenience.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope of the present invention, and these modifications or replacements should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A video signal expansion circuit is characterized by comprising a processor, an FPGA chip and a differential circuit;
the processor is connected with the FPGA chip and is used for outputting a DSI video signal to the FPGA chip, wherein the DSI video signal is a double-picture video signal;
the FPGA chip is respectively connected with a first display and the differential circuit, and is used for converting the DSI video signal into a first video signal and a second video signal and respectively outputting the first video signal and the second video signal to the first display and the differential circuit;
the differential circuit is connected with a second display and used for converting the second video signal into a differential signal and outputting the differential signal to the second display.
2. The video signal expansion circuit of claim 1, wherein the FPGA chip comprises a DSI video signal receiving module and first and second video signal output modules connected to the DSI video signal receiving module;
the DSI video signal receiving module is further connected with the processor, the first video signal output module is connected with the first display, and the second video signal output module is connected with the differential circuit.
3. The video signal expansion circuit according to claim 2, wherein the differential circuit includes a timing circuit and at least one data circuit, one ends of the timing circuit and the data circuit are connected to the second video signal output module, and the other ends of the timing circuit and the data circuit are connected to the second display.
4. The video signal expansion circuit according to claim 3, wherein the second video signal output module includes a first output sub-module and a second output sub-module, one end of each of the first output sub-module and the second output sub-module is connected to the DSI video signal receiving module, and the other end thereof is connected to the timing circuit and the data circuit.
5. The video signal expansion circuit of claim 3, wherein said differential circuit includes four of said data circuits.
6. The video signal expansion circuit of claim 4, wherein the timing circuit and the data circuit each comprise a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a first output terminal, a second output terminal, a first resistor, a second resistor, and a filter circuit;
the first input end and the third input end are both connected with the second output submodule, the second input end and the fourth input end are both connected with the first output submodule, and the first output end and the second output end are both connected with the second display;
the first input end is connected with the filter circuit through the first resistor, the third input end is connected with the filter circuit through the second resistor, and the third input end, the fourth input end, the first output end and the second output end are connected with the filter circuit.
7. The video signal expansion circuit of claim 6, wherein the filter circuit comprises a first capacitor, a second capacitor, and a common mode inductor;
two ends of the first capacitor are respectively connected with a third pin and a fourth pin of the common mode inductor, two ends of the second capacitor are respectively connected with a first pin and a second pin of the common mode inductor, and the first pin and the second pin of the common mode inductor are both connected with the second display;
and a third pin of the common mode inductor is connected with the first resistor and the second input end, and a fourth pin of the common mode inductor is connected with the second resistor and the fourth input end.
8. The video signal expansion circuit according to claim 2, further comprising a conversion chip and a memory;
the system support module of the FPGA chip is connected with the memory through the conversion chip;
the conversion chip is also connected with the processor.
9. The video signal expansion circuit of claim 2, further comprising an active clock circuit connected to a process debugging module of the FPGA chip.
10. A video signal expansion apparatus comprising the video signal expansion circuit according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220809713.2U CN217116234U (en) | 2022-04-08 | 2022-04-08 | Video signal expansion circuit and expansion device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220809713.2U CN217116234U (en) | 2022-04-08 | 2022-04-08 | Video signal expansion circuit and expansion device |
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| Publication Number | Publication Date |
|---|---|
| CN217116234U true CN217116234U (en) | 2022-08-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220809713.2U Active CN217116234U (en) | 2022-04-08 | 2022-04-08 | Video signal expansion circuit and expansion device |
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| CN (1) | CN217116234U (en) |
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- 2022-04-08 CN CN202220809713.2U patent/CN217116234U/en active Active
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