CN216565737U

CN216565737U - Chip PCB packaging structure

Info

Publication number: CN216565737U
Application number: CN202121908005.6U
Authority: CN
Inventors: 孙骥; 杨涛
Original assignee: Shanghai Faith Information Technology Co ltd
Current assignee: Shanghai Faith Information Technology Co ltd
Priority date: 2021-08-16
Filing date: 2021-08-16
Publication date: 2022-05-17
Anticipated expiration: 2031-08-16

Abstract

The utility model provides a chip PCB packaging structure, wherein a chip bonding pad of the packaging structure comprises a pin bonding area 11 and a chip bonding area, the chip bonding area comprises a solder resisting area 121 and an exposed bonding pad area 122, the solder resisting area 121 is communicated with the pin bonding area 11, and the distance between the exposed bonding pad area 122 and the pin bonding area 11 is not less than half of the length of the pin bonding area 11. Because the solder paste is heated during reflow soldering, the chip can be supported possibly to influence the soldering effect of the chip, the paste layer area of the soldering area of the solder chip is reduced properly, the soldering effect is not influenced under the performance that the solder paste is heated to flow, the pin bonding pad is independent of the exposed bonding pad, the solder paste on the pin bonding area 11 cannot be communicated with the solder paste of the exposed bonding pad area 122 and cannot be sucked away by the solder paste of the exposed bonding pad area 122 in reflow soldering, and therefore the amount of the solder paste on the pin bonding pad cannot be reduced, and the poor soldering condition of the pin cannot be caused.

Description

Chip PCB packaging structure

Technical Field

The present invention relates to a PCB package, and more particularly, to a chip PCB package structure.

Background

The chip package plays a role in placing, fixing, sealing, protecting the chip and enhancing the electrothermal performance, and is also a bridge for communicating the internal world of the chip with the external circuit, i.e. the connection points on the chip are connected to the pins of the package shell by wires, the pins are connected with other devices by the wires on the printed board, and the heat dissipation and soldering of the chip are also very important in the package.

The QFN chip is applied to a power supply, a plurality of irregular exposed welding ends with large areas connected with partial I/O welding ends are arranged at the bottom of a QFN element and used for conducting heat, I/O welding ends (pins) for realizing electrical connection are arranged on the periphery of the QFN chip, and the I/O welding ends are exposed on the side face of the element.

Because the pin bonding pad and the bottom exposed bonding pad of the QFN chip are directly connected (exist as a whole), and the area of the exposed bonding pad is much larger than that of the pin bonding pad, soldering tin on the chip pin can be absorbed by tin paste on the exposed bonding pad during reflow soldering, so that uneven and bad welding phenomena such as chip pin missing welding, insufficient welding, missing welding and the like are caused, and the heat dissipation problem of the chip is solved.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problems that because the size of a chip exposed bonding pad is larger, the corresponding solder paste layer area is also larger, more solder paste is generated, the chip can be supported up due to the fact that the solder paste is heated during reflow soldering, the chip soldering effect is influenced, and the solder paste on a pin bonding pad can be sucked away, so that the pin soldering is poor.

The technical scheme for solving the technical problems is as follows:

the utility model provides a chip PCB packaging structure, packaging structure's chip bonding pad includes pin welding area and chip welding area, the chip welding area is including hindering the solder mask area and exposing the pad area, hinder the solder mask area UNICOM the pin welding area, expose the pad area with the interval of pin welding area is not less than half of pin welding area length.

As a preferred embodiment of the present invention, the distance between the exposed pad area and the lead bonding area is not less than 0.3 mm.

As a preferred embodiment of this embodiment, the length of the lead bonding area is not less than 0.6 mm.

As a preferred embodiment of this embodiment, the pin pad area and the exposed pad area are electrically connected through a wiring layer of the PCB.

As a preferred implementation of this embodiment, the exposed pad area is divided into a plurality of areas, and adjacent areas are separated by the solder resist area.

The utility model has the beneficial effects that:

according to the utility model, the chip welding area is divided into the solder resisting area and the exposed welding pad area, the solder resisting area is communicated with the pin welding area, and the distance between the exposed welding pad area and the pin welding area is not less than half of the length of the pin welding area. Because the solder paste is heated during reflow soldering, the chip can be supported possibly, and the chip soldering effect is influenced, so that the paste layer area of the chip soldering area is reduced properly, the soldering effect is not influenced under the performance that the solder paste is heated to flow, the pin soldering pad is independent of the exposed soldering pad through the solder-resisting area, the solder paste on the pin soldering area cannot be communicated with the solder paste of the exposed soldering pad area, and cannot be absorbed by the solder paste of the exposed soldering pad area in reflow soldering, so that the amount of the solder paste on the pin soldering pad cannot be reduced, the poor pin soldering condition cannot be caused, and the bad phenomena of missing soldering, faulty soldering, missing soldering and the like when the chip pin is connected with the middle soldering pad are solved.

Drawings

FIG. 1 is a schematic diagram of the distribution of the bonding areas of the chip according to the present invention.

Fig. 2 is a schematic diagram of a pin pad of the present invention.

Fig. 3 is a schematic structural diagram of a solder resist area and a bare pad area according to the present invention.

Detailed Description

The following description is presented to enable any person skilled in the art to make and use the utility model and is incorporated in the context of a particular application. Various modifications, as well as various uses in different applications will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the utility model. It will be apparent, however, to one skilled in the art that the practice of the utility model may not necessarily be limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

The reader's attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. All the features disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

It is noted that, where used, further, preferably, still further and more preferably is a brief introduction to the exposition of the alternative embodiment on the basis of the preceding embodiment, the contents of the further, preferably, still further or more preferably back band being combined with the preceding embodiment as a complete constituent of the alternative embodiment. Several further, preferred, still further or more preferred arrangements of the belt after the same embodiment may be combined in any combination to form a further embodiment.

The utility model is described in detail below with reference to the figures and specific embodiments. It is noted that the aspects described below in connection with the figures and the specific embodiments are only exemplary and should not be construed as imposing any limitation on the scope of the present invention.

The noun explains:

QFN (Quad Flat No-leads Package), one of surface mount packages. QFN is a name prescribed by the japan electronics and mechanical industries.

I/O welding end: I/O (Input/Output), i.e., Input/Output welding port.

VIN: a power supply input terminal; GND: and a power supply ground terminal.

Referring to fig. 1, fig. 2 and fig. 3, the present invention provides a chip-PCB package structure, a chip pad of the package structure includes a pin pad 11 and a chip pad, the chip pad includes a solder mask area 121 and a bare pad area 122, the solder mask area 121 communicates with the pin pad 11, and a distance between the bare pad area 122 and the pin pad 11 is not less than half of a length of the pin pad 11. According to the utility model, the chip welding area is divided into the solder resisting area 121 and the exposed welding pad area 122, the solder resisting area 121 is communicated with the pin welding area 11, and the distance between the exposed welding pad area 122 and the pin welding area 11 is not less than half of the length of the pin welding area 11. Because the solder paste is heated during reflow soldering, the chip can be supported possibly, and the chip soldering effect is influenced, so that the paste layer area of the chip soldering area is properly reduced, the soldering effect is not influenced under the performance that the solder paste is heated to flow, the pin bonding pad is independent of the exposed bonding pad, the solder paste on the pin bonding area 11 cannot be communicated with the solder paste of the exposed bonding pad area 122, and cannot be absorbed by the solder paste of the exposed bonding pad area 122 in reflow soldering, so that the amount of the solder paste on the pin bonding pad cannot be reduced, the poor pin soldering condition cannot be caused, and the poor phenomena of missing soldering, faulty soldering, missing soldering and the like when the chip pins are connected with the middle bonding pad are solved. In the embodiment, the chip packaging size is firstly determined, and because the exposed bonding pad of the chip is irregular in shape, the exposed bonding pad of the chip is divided into two parts, and one part is a pin; the other part is the chip pad in the middle of the chip.

Furthermore, the size of the peripheral pin bonding pad is determined firstly, and the peripheral pin bonding pad is manufactured on the PCB according to the size.

Further, taking the QFN chip as an example, the shape of the exposed pad is drawn by drawing the windowing area, i.e. the solder mask area 121, according to the size of the exposed pad of the QFN chip, and the size of the exposed pad of the solder mask area 121 is communicated with the size of the connected pin pad, so as to expose the same area on the PCB as the solder area of the QFN chip.

Further, since the lead lands 11 (lead pads) are separately fabricated, the size and area of the solder paste layer have been defined, and only the area and size of the solder paste layer of the chip lands need to be determined.

Further, the size of the solder paste layer in the chip bonding area is determined, so that the size of the solder paste layer does not exceed the size of the solder mask area 121, and the distance between the solder paste layer in the chip bonding area and the pin bonding area 11 is greater than or equal to 1/2 of the length of the pin bonding area 11. In this embodiment, the length of the pin bonding area 11 is 0.6mm, and further, the distance from the solder paste layer of the chip bonding area to the pin bonding area 11 is greater than or equal to 0.3 mm. It should be noted that the solder paste layer, i.e., the exposed pad area 122, is described as the exposed pad area 122 when the solder paste is not applied, and is described as the solder paste layer after the solder paste is applied.

Still further, since the electrical property of the chip is determined, the pin pad (pin land 11) with the same property and the middle exposed pad (exposed pad area 122) are electrically connected through the wiring layer, so as to connect the middle exposed pad with the PCB and increase the heat dissipation area, thereby improving the heat dissipation effect of the device.

Further, since the sizes of the solder resist area 121 and the solder paste layer on the exposed pad area 122 of the exposed pad have been defined, the solder paste layer of the lead pad is already independent of the exposed pad, and the size can be determined without affecting the soldering effect and without being absorbed by the exposed pad.

Because the size of the exposed pad area 122 is larger, the corresponding solder paste area is also larger, and the amount of solder paste is more, the chip may be lifted up due to the heating of the solder paste during reflow soldering, and the soldering effect of the chip is affected. Therefore, the size of the single region is reduced after the exposed pad region 122 is divided, and the soldering effect is not affected under the performance of solder paste heated and flowed. The pin bonding pad is independent of the exposed bonding pad of the chip, so that the phenomenon that fluid is absorbed by solder paste which becomes fluid in reflow soldering is avoided, the quantity of the solder paste on the pin bonding pad is not absorbed by the solder paste exposed on the bonding pad area 122, the quantity of the solder paste is not reduced, and the poor welding condition of the pin is avoided.

As can be seen from fig. 3, the exposed pad area 122 is divided into a plurality of areas, and adjacent areas are separated by the solder resist area 121.

While the present invention has been described in detail and with reference to the embodiments thereof as illustrated in the accompanying drawings, it will be apparent to one skilled in the art that various changes and modifications can be made therein. Therefore, certain details of the embodiments are not to be interpreted as limiting, and the scope of the utility model is to be determined by the appended claims.

Claims

1. The utility model provides a chip PCB packaging structure, its characterized in that, packaging structure's chip bonding pad includes pin welding area and chip welding area, the chip welding area is including hindering the welding area and exposing the pad area, hinder welding area UNICOM the pin welding area, expose the pad area with the interval of pin welding area is not less than half of pin welding area length.

2. The chip PCB package structure of claim 1, wherein: the distance between the exposed bonding pad area and the pin bonding area is not less than 0.3 mm.

3. The chip PCB package structure of claim 2, wherein: the length of the pin welding area is not less than 0.6 mm.

4. The chip PCB package structure of claim 1, wherein: the pin welding area is electrically connected with the exposed pad area through a wiring layer of the PCB.

5. The chip PCB package structure of claim 1, wherein: the exposed welding pad area is divided into a plurality of areas, and the adjacent areas are separated by the solder resisting area.