CN216565089U - Impedance matching circuit and antenna - Google Patents
Impedance matching circuit and antenna Download PDFInfo
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- CN216565089U CN216565089U CN202122591267.0U CN202122591267U CN216565089U CN 216565089 U CN216565089 U CN 216565089U CN 202122591267 U CN202122591267 U CN 202122591267U CN 216565089 U CN216565089 U CN 216565089U
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Abstract
The utility model discloses an impedance matching circuit and an antenna, wherein the impedance matching circuit comprises a first matching circuit and a balun circuit; a first matching circuit: one end of the first inductor is electrically connected with one end of the second inductor and one end of the first capacitor respectively, the other end of the second inductor is grounded, one end of the third inductor is electrically connected with one end of the fourth inductor and one end of the second capacitor respectively, the other end of the fourth inductor is grounded, and the other ends of the first capacitor and the second capacitor are connected with the signal output end; the balun circuit: the other end of the first inductor is electrically connected with one end of the fifth inductor and one end of the third capacitor respectively, the other end of the third inductor is electrically connected with one end of the sixth inductor and one end of the fourth capacitor respectively, the other end of the third capacitor and the other end of the sixth inductor are grounded, and the other end of the fifth inductor and the other end of the fourth capacitor are connected with the signal source end. The impedance matching circuit disclosed by the utility model can solve the technical problem that the efficiency of the existing regulating circuit is lower when the impedance matching is adjusted.
Description
Technical Field
The utility model belongs to the technical field of matching networks, and particularly relates to an impedance matching circuit and an antenna.
Background
The radio frequency amplifier of the existing radio frequency antenna generally adopts a single-ended structure, and a load end (a signal output end) of a radio frequency amplifying circuit and a signal source end have impedance difference, so that the radio frequency amplifying circuit can be used after the impedance of the load end and the impedance of the signal source end are matched through an adjusting circuit; on the other hand, balance and unbalance conversion is also required between the load end and the signal source end.
However, for the current adjusting circuit, if the power maximization is satisfied while the impedance matching function is realized, the specific parameters of the components of the current adjusting circuit can only be adjusted by experience in the actual application process, and the efficiency is very low.
SUMMERY OF THE UTILITY MODEL
In order to overcome the above disadvantages of the prior art, an object of the present invention is to provide an impedance matching circuit, which aims to solve the technical problem of low efficiency of the existing adjusting circuit in performing impedance matching adjustment.
In order to achieve the purpose, the technical scheme adopted by the utility model is as follows:
an impedance matching circuit comprising a first matching circuit and a balun circuit; wherein:
the first matching circuit comprises a first inductor, a second inductor, a third inductor, a fourth inductor, a first capacitor and a second capacitor; one end of the first inductor is electrically connected with one end of the second inductor and one end of the first capacitor respectively, the other end of the second inductor is grounded, one end of the third inductor is electrically connected with one end of the fourth inductor and one end of the second capacitor respectively, the other end of the fourth inductor is grounded, and the other end of the first capacitor and the other end of the second capacitor are used for being connected with a signal output end;
the balun circuit comprises a fifth inductor, a sixth inductor, a third capacitor and a fourth capacitor; the other end of the first inductor is electrically connected with one end of the fifth inductor and one end of the third capacitor respectively, the other end of the third inductor is electrically connected with one end of the sixth inductor and one end of the fourth capacitor respectively, the other end of the third capacitor and the other end of the sixth inductor are grounded, and the other end of the fifth inductor and the other end of the fourth capacitor are used for being connected with a signal source end.
Further, the impedance matching circuit further comprises a second matching circuit; wherein:
the second matching circuit comprises a fifth capacitor, a seventh inductor and an eighth inductor; one end of the seventh inductor is electrically connected to one end of the eighth inductor, the other end of the fifth inductor, and the other end of the fourth capacitor, respectively, the other end of the eighth inductor is grounded, the other end of the seventh inductor and one end of the fifth capacitor are used for connecting the signal source terminal, and the other end of the fifth capacitor is grounded.
Further, an inductance value of the fifth inductor is calculated based on a product of an impedance value of the signal output terminal and an impedance value of the signal source terminal, and the inductance value of the fifth inductor is equal to an inductance value of the sixth inductor.
Further, the capacitance value of the third capacitor is calculated based on the product of the impedance value of the signal output terminal and the impedance value of the signal source terminal, and the capacitance value of the third capacitor is equal to the capacitance value of the fourth capacitor.
Further, the inductance value of the first inductor is calculated based on the product of the impedance value of the signal output terminal and the impedance value of the signal source terminal, and the inductance value of the first inductor is equal to the inductance value of the third inductor.
Further, an inductance value of the second inductor is calculated based on a product of an impedance value of the signal output terminal and an impedance value of the signal source terminal, and the inductance value of the second inductor is equal to an inductance value of the fourth inductor.
Further, the capacitance value of the first capacitor is calculated based on the product of the impedance value of the signal output terminal and the impedance value of the signal source terminal, and the capacitance value of the first capacitor is equal to the capacitance value of the second capacitor.
Further, an inductance value of the first inductor is calculated based on a product of an impedance value of the signal output terminal and an impedance value of the signal source terminal, and the inductance value of the first inductor is equal to an inductance value of the third inductor, and an inductance value of the eighth inductor is one half of an inductance value of the first inductor.
Further, an inductance value of the second inductor is calculated based on a product of an impedance value of the signal output terminal and an impedance value of the signal source terminal, and the inductance value of the second inductor is equal to an inductance value of the fourth inductor, and an inductance value of the seventh inductor is one half of an inductance value of the second inductor.
Further, the capacitance value of the first capacitor is calculated based on a product of the impedance value of the signal output terminal and the impedance value of the signal source terminal, and the capacitance value of the first capacitor is equal to the capacitance value of the second capacitor, and the capacitance value of the fifth capacitor is twice the capacitance value of the first capacitor.
Correspondingly, the utility model also provides an antenna, which comprises the impedance matching circuit.
Compared with the prior art, the utility model has the beneficial effects that:
according to the impedance matching circuit provided by the utility model, the single-end signal is converted into two differential signals through the balun circuit, and the two output ends of the balun circuit are connected with the first matching circuit in a cascade manner to obtain the differential matching network, so that on the premise of realizing balance and unbalance conversion between the signal output end and the signal source end, the optimal values of each inductor and each capacitor in the differential matching network can be calculated in advance according to the specific impedance values of the signal source end and the signal output end, further, the power maximization based on the differential matching network is achieved while the impedance mismatching at the two ends is eliminated, the operation of debugging element parameters after the circuit connection is finished is omitted, and the working efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a connection diagram of an impedance matching circuit according to an embodiment of the utility model.
Description of reference numerals:
the implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture, and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, if the meaning of "and/or" and/or "appears throughout, the meaning includes three parallel schemes, for example," A and/or B "includes scheme A, or scheme B, or a scheme satisfying both schemes A and B. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
Referring to fig. 1, an embodiment of the present invention provides an impedance matching circuit, which includes a first matching circuit 1 and a balun circuit 2; wherein:
the first matching circuit 1 comprises a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a first capacitor C1 and a second capacitor C2; one end of a first inductor L1 is electrically connected with one end of a second inductor L2 and one end of a first capacitor C1 respectively, the other end of the second inductor L2 is grounded, one end of a third inductor L3 is electrically connected with one end of a fourth inductor L4 and one end of a second capacitor C2 respectively, the other end of the fourth inductor L4 is grounded, and the other end of the first capacitor C1 and the other end of the second capacitor C2 are used for being connected with a signal output end Zdp;
the balun circuit 2 comprises a fifth inductor L5, a sixth inductor L6, a third capacitor C3 and a fourth capacitor C4; the other end of the first inductor L1 is electrically connected to one end of a fifth inductor L5 and one end of a third capacitor C3, the other end of the third inductor L3 is electrically connected to one end of a sixth inductor L6 and one end of a fourth capacitor C4, the other end of the third capacitor C3 and the other end of the sixth inductor L6 are grounded, and the other end of the fifth inductor L5 and the other end of the fourth capacitor C4 are used for connecting a signal source end Zsn.
In this embodiment, the balun circuit 2 and the first matching circuit 1 are cascade-connected, so that a differential matching network can be obtained. Specifically, the balun circuit 2 is a conversion module between a single-ended terminal and a differential pair, and when a radio frequency signal output by the signal source terminal Zsn is input from an input terminal (i.e., the left terminal in the diagram) of the balun circuit 2, the radio frequency signal is output through two output terminals (i.e., the right terminal in the diagram) of the balun circuit 2, which is equivalent to dividing one input signal into two output signals, thereby realizing balanced and unbalanced conversion. However, at this time, the impedance of the output end of the balun circuit 2 still has a mismatch problem with the impedance of the signal output end Zdp, so that the two output ends of the balun circuit 2 are respectively connected with the two input ends of the first matching circuit 1 (i.e., the other end of the first inductor L1 and the other end of the third inductor L3), so that the first matching circuit 1 can realize T-type matching by adjusting specific values of each inductor and capacitor in the first matching circuit 1, the impedance mismatch problem of the output signal of the balun circuit 2 is eliminated, and the impedance matching between the output end of the balun circuit 2 and the signal output end Zdp is realized. The specific values of the inductors and the capacitors in the balun circuit 2 and the first matching circuit 1 can be obtained by calculation in advance according to the specific impedance values of the signal source end Zsn and the signal output end Zdp, and the specific impedance values of the signal source end Zsn and the signal output end Zdp can be obtained by searching a chip manual or by measuring through a vector network analyzer.
Therefore, in the impedance matching circuit provided by this embodiment, the single-end signal is converted into two differential signals through the balun circuit 2, and two output ends of the balun circuit 2 are cascade-connected to the first matching circuit 1 to obtain the differential matching network, so that on the premise of realizing the balance and unbalance conversion between the signal output end Zdp and the signal source end Zsn, the optimal values of each inductor and capacitor in the differential matching network can be pre-calculated according to the specific impedance values of the signal source end Zsn and the signal output end Zdp, thereby achieving the power maximization based on the differential matching network while eliminating the impedance mismatch at two ends, eliminating the operation of debugging the element parameters after the circuit connection is completed, and improving the working efficiency.
Specifically, referring to fig. 1, the impedance matching circuit further includes a second matching circuit 3; wherein:
the second matching circuit 3 comprises a fifth capacitor C5, a seventh inductor L7 and an eighth inductor L8; one end of the seventh inductor L7 is electrically connected to one end of the eighth inductor L8, the other end of the fifth inductor L5, and the other end of the fourth capacitor C4, respectively, the other end of the eighth inductor L8 is grounded, the other end of the seventh inductor L7 and one end of the fifth capacitor C5 are used for connecting the signal source terminal Zsn, and the other end of the fifth capacitor C5 is grounded.
Signal transmission will be affected due to the possible mismatch between the impedance of the input terminal of the balun circuit 2 and the impedance of the signal source terminal Zsn. Thus, in the present embodiment, the input terminal of the balun circuit 2 is connected to the output terminal of the second matching circuit 3 (i.e. one terminal of the seventh inductor L7 and one terminal of the eighth inductor L8), so that by adjusting the specific values of the inductors and capacitors in the second matching circuit 3, pi-type matching can be implemented in the second matching circuit 3, and impedance matching between the input terminal of the balun circuit 2 and the signal source terminal Zsn can be implemented. The specific values of the inductors and the capacitors in the second matching circuit 3 may be calculated in advance according to the specific impedance values of the signal source end Zsn and the signal output end Zdp, and the specific impedance values of the signal source end Zsn and the signal output end Zdp may be obtained by searching a chip manual or by measuring with a vector network analyzer.
Specifically, the inductance value of the fifth inductor L5 is calculated based on the product of the impedance value of the signal output end Zdp and the impedance value of the signal source end Zsn, and the inductance value of the fifth inductor L5 is equal to the inductance value of the sixth inductor L6.
Specifically, the capacitance value of the third capacitor C3 is calculated based on the product of the impedance value of the signal output end Zdp and the impedance value of the signal source end Zsn, and the capacitance value of the third capacitor C3 is equal to the capacitance value of the fourth capacitor C4.
As a preferred embodiment, for the balun circuit 2, the inductance values of the fifth inductor L5 and the sixth inductor L6, and the impedance values of the signal output end Zdp and the signal source end Zsn satisfy the following calculation formula:
the capacitance values of the third capacitor C3 and the fourth capacitor C4, the impedance values of the signal output end Zdp and the signal source end Zsn satisfy the following calculation formula:
specifically, the inductance value of the first inductor L1 is calculated based on the product of the impedance value of the signal output end Zdp and the impedance value of the signal source end Zsn, and the inductance value of the first inductor L1 is equal to the inductance value of the third inductor L3.
Specifically, the inductance value of the second inductor L2 is calculated based on the product of the impedance value of the signal output end Zdp and the impedance value of the signal source end Zsn, and the inductance value of the second inductor L2 is equal to the inductance value of the fourth inductor L4.
Specifically, the capacitance value of the first capacitor C1 is calculated based on the product of the impedance value of the signal output end Zdp and the impedance value of the signal source end Zsn, and the capacitance value of the first capacitor C1 is equal to the capacitance value of the second capacitor C2.
As a preferred embodiment, for the first matching circuit 1, the inductance values of the first inductor L1 and the third inductor L3, and the impedance values of the signal output end Zdp and the signal source end Zsn satisfy the following calculation formula:
the inductance values of the second inductor L2 and the fourth inductor L4, and the impedance values of the signal output end Zdp and the signal source end Zsn satisfy the following calculation formula:
the capacitance values of the first capacitor C1 and the second capacitor C2, the impedance values of the signal output end Zdp and the signal source end Zsn satisfy the following calculation formula:
in the above calculation formula, ω is 2 × pi × f, where f is a frequency (e.g., 2.4G, 5.8G, etc.) used by the antenna rf amplifier chip.
Specifically, the inductance value of the eighth inductor L8 is one-half of the inductance value of the first inductor L1.
Specifically, the inductance value of the seventh inductor L7 is one-half of the inductance value of the second inductor L2.
Specifically, the capacitance value of the fifth capacitor C5 is twice the capacitance value of the first capacitor C1.
For the second matching circuit 3, the inductance values of the eighth inductor L8 and the seventh inductor L7 and the inductance values of the first inductor L1 and the second inductor L2 satisfy the following relationship:
L8＝L1/2
L7＝L2/2
the capacitance of the fifth capacitor C5 and the capacitance of the first capacitor C1 satisfy the following relationship:
C5＝C1*2
thus, by using the calculation formula in the above embodiment, the inductance values of the inductors and the capacitance values of the capacitors in the balun circuit 2, the first matching circuit 1, and the second matching circuit 3 can be determined in advance based on the obtained impedance values of the signal output end Zdp and the signal source end Zsn, thereby eliminating the operation of debugging the element parameters after the connection of the balun circuit 2, the first matching circuit 1, and the second matching circuit 3 is completed. Therefore, the balance and unbalance conversion and impedance matching of the signal output end Zdp and the signal source end Zsn are realized in a simple, quick and easy way, the power maximization based on the differential matching network is achieved, and the working stability of the matching network is improved.
Correspondingly, the embodiment of the utility model also provides an antenna, which comprises the impedance matching circuit in any embodiment.
The antenna provided in this embodiment is specifically a radio frequency antenna with a radio frequency amplifier, and the signal source terminal Zsn and the signal output terminal Zdp correspond to two ends of the input and output feed signals of the radio frequency amplifier chip. As for the specific connection relationship of the impedance matching circuit, the above-described embodiments may be referred to. Since the antenna adopts all technical solutions of all the embodiments, at least all the beneficial effects brought by the technical solutions of the embodiments are achieved, and are not described in detail herein.
It should be noted that other contents of the impedance matching circuit and the antenna disclosed in the present invention can be referred to in the prior art, and are not described herein again.
The above description is only an alternative embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. An impedance matching circuit, characterized in that the impedance matching circuit comprises a first matching circuit and a balun circuit; wherein:
the first matching circuit comprises a first inductor, a second inductor, a third inductor, a fourth inductor, a first capacitor and a second capacitor; one end of the first inductor is electrically connected with one end of the second inductor and one end of the first capacitor respectively, the other end of the second inductor is grounded, one end of the third inductor is electrically connected with one end of the fourth inductor and one end of the second capacitor respectively, the other end of the fourth inductor is grounded, and the other end of the first capacitor and the other end of the second capacitor are used for being connected with a signal output end;
the balun circuit comprises a fifth inductor, a sixth inductor, a third capacitor and a fourth capacitor; the other end of the first inductor is electrically connected with one end of the fifth inductor and one end of the third capacitor respectively, the other end of the third inductor is electrically connected with one end of the sixth inductor and one end of the fourth capacitor respectively, the other end of the third capacitor and the other end of the sixth inductor are grounded, and the other end of the fifth inductor and the other end of the fourth capacitor are used for being connected with a signal source end.
2. The impedance matching circuit of claim 1, further comprising a second matching circuit; wherein:
the second matching circuit comprises a fifth capacitor, a seventh inductor and an eighth inductor; one end of the seventh inductor is electrically connected to one end of the eighth inductor, the other end of the fifth inductor, and the other end of the fourth capacitor, respectively, the other end of the eighth inductor is grounded, the other end of the seventh inductor and one end of the fifth capacitor are used for connecting the signal source terminal, and the other end of the fifth capacitor is grounded.
3. The impedance matching circuit of claim 1, wherein an inductance value of the fifth inductor is calculated based on a product of an impedance value of the signal output terminal and an impedance value of the signal source terminal, and the inductance value of the fifth inductor is equal to an inductance value of the sixth inductor;
and/or the capacitance value of the third capacitor is calculated based on the product of the impedance value of the signal output end and the impedance value of the signal source end, and the capacitance value of the third capacitor is equal to the capacitance value of the fourth capacitor.
4. The impedance matching circuit of claim 1, wherein the inductance value of the first inductor is calculated based on a product of the impedance value of the signal output terminal and the impedance value of the signal source terminal, and the inductance value of the first inductor is equal to the inductance value of the third inductor.
5. The impedance matching circuit of claim 1, wherein the inductance value of the second inductor is calculated based on a product of the impedance value of the signal output terminal and the impedance value of the signal source terminal, and the inductance value of the second inductor is equal to the inductance value of the fourth inductor.
6. The impedance matching circuit of claim 1, wherein the capacitance of the first capacitor is calculated based on a product of an impedance value of the signal output terminal and an impedance value of the signal source terminal, and the capacitance of the first capacitor is equal to the capacitance of the second capacitor.
7. The impedance matching circuit of claim 2, wherein the inductance value of the first inductor is calculated based on a product of the impedance value of the signal output terminal and the impedance value of the signal source terminal, and the inductance value of the first inductor is equal to the inductance value of the third inductor, and the inductance value of the eighth inductor is one-half of the inductance value of the first inductor.
8. The impedance matching circuit of claim 2, wherein the inductance value of the second inductor is calculated based on the product of the impedance value of the signal output terminal and the impedance value of the signal source terminal, and the inductance value of the second inductor is equal to the inductance value of the fourth inductor, and the inductance value of the seventh inductor is one-half of the inductance value of the second inductor.
9. The impedance matching circuit of claim 2, wherein the capacitance of the first capacitor is calculated based on a product of an impedance value of the signal output terminal and an impedance value of the signal source terminal, and the capacitance of the first capacitor is equal to the capacitance of the second capacitor, and the capacitance of the fifth capacitor is twice the capacitance of the first capacitor.
10. An antenna characterized in that it comprises an impedance matching circuit according to any one of claims 1 to 9.
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| CN202122591267.0U CN216565089U (en) | 2021-10-26 | 2021-10-26 | Impedance matching circuit and antenna |
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| CN202122591267.0U CN216565089U (en) | 2021-10-26 | 2021-10-26 | Impedance matching circuit and antenna |
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