CN115208441B - Antenna network and related electronic device - Google Patents

Antenna network and related electronic device Download PDF

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CN115208441B
CN115208441B CN202110378200.0A CN202110378200A CN115208441B CN 115208441 B CN115208441 B CN 115208441B CN 202110378200 A CN202110378200 A CN 202110378200A CN 115208441 B CN115208441 B CN 115208441B
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positive
negative
antenna
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matching circuit
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CN115208441A (en
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刘诗雨
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Priority to PCT/CN2021/137429 priority patent/WO2022213649A1/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
    • H04B7/0413—MIMO systems
    • H04B7/0426—Power distribution
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
    • H04B7/08—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Details Of Aerials (AREA)

Abstract

The application discloses an antenna network, comprising: electromagnetic compatibility filter, matching circuit and antenna. The application also discloses an antenna network, which comprises: an electromagnetic compatibility filter, a matching circuit, a quality-reducing factor circuit, and an antenna. The application also discloses an electronic device, which comprises: the chip is provided with a positive output end and a negative output end; and the antenna network described above, wherein the positive output terminal of the chip is coupled to the positive input terminal of the electromagnetic compatibility filter of the antenna network, and the negative output terminal of the chip is coupled to the negative input terminal of the electromagnetic compatibility filter of the antenna network.

Description

Antenna network and related electronic device
Technical Field
The present application relates to the field of signal transmission, and in particular, to an antenna network for near field communication and a near field communication device.
Background
In the field of near field communication, when designing an antenna, the problem of impedance matching between a near field communication control chip and the antenna needs to be considered, and when the impedance is matched, the lower the reflected signal generated when a signal enters the antenna from the chip, the higher the power output from the chip to the antenna, and the higher the efficiency. In order to achieve impedance matching, a matching network is provided between the antenna and the chip, and the values of the devices in the matching network are tuned. The antenna together with the matching network may be referred to as an antenna network. According to the circuit principle, as the frequency of the signal source changes, the network impedance of the antenna network changes, and at certain specific frequency points, the network impedance of the antenna network is a pure resistor, so that the output power of the antenna network is highest, and the radiation magnetic field of the antenna is strongest. Tuning is to make the network impedance of the antenna network pure at the operating frequency.
In general, tuning methods are mostly asymmetric tuning, that is, the ideal value of each tuned device can make the antenna network and the chip achieve impedance matching at the working frequency, but some mistuning is actually caused by errors, when the asymmetrically tuned antenna network is mistuned, the impedance seen from the chip to the antenna network is in an asymmetric form based on the real axis on the smith chart, as shown in fig. 1. However, the bandwidth and antenna quality factor (Q value) obtained by asymmetric tuning are less than ideal, resulting in limited communication distance, which needs to be further improved.
Disclosure of Invention
An objective of the present application is to disclose an antenna network and related electronic device for solving the above-mentioned problems.
An embodiment of the application discloses an antenna network for receiving a chip transmitting end positive signal and a chip transmitting end negative signal from a chip to generate an antenna signal, comprising: electromagnetic compatibility EMC filter, including positive input, negative input, positive output and negative output, wherein positive input is used for receiving the chip transmitting end positive end signal, negative input is used for receiving the chip transmitting end negative end signal, the equivalent model of EMC filter includes: a first positive end inductance is equivalently coupled between the positive input end of the EMC filter and the positive output end of the EMC filter; a first negative side inductance is equivalently coupled between the negative input of the EMC filter and the negative output of the EMC filter; the first positive end capacitor is equivalently coupled between the positive output end of the EMC filter and the ground voltage; and a first negative terminal capacitively coupled between the negative output of the EMC filter and the ground voltage; wherein the first positive side inductor and the first negative side inductor both have an inductance value L 0 The first positive side capacitor and the first negative side capacitor both have a capacitance value C 0 The method comprises the steps of carrying out a first treatment on the surface of the The matching circuit comprises a positive input end, a negative input end, a positive output end and a negative output end, wherein the positive input end of the matching circuit is coupled with the positive output end of the EMC filter, the negative input end of the matching circuit is coupled with the negative output end of the EMC filter, and an equivalent model of the matching circuit comprises: a second positive terminal capacitance equivalent is coupled between the positive input terminal of the matching circuit and the positive output terminal of the matching circuit; a second negative terminal is capacitively coupled between the negative input of the matching circuit and the negative output of the matching circuit; the third positive end capacitor is equivalently coupled between the positive output end of the matching circuit and the ground voltage; and a third negative terminal capacitively coupled between the negative output of the matching circuit and the ground voltage; wherein the second positive side capacitor and the second negative side capacitor both have a capacitance value C 1 The third positive side capacitor and the third negative side capacitor both have a capacitance value C 2 The method comprises the steps of carrying out a first treatment on the surface of the AntennaThe antenna comprises a positive input end and a negative input end, wherein the positive input end of the antenna is coupled with the positive output end of the matching circuit, the negative input end of the antenna is coupled with the negative output end of the matching circuit, and an equivalent model of the antenna comprises: a fourth capacitive equivalent is coupled between the positive input of the antenna and the negative input of the antenna; the first resistor and the antenna inductance are equivalently connected in series between the positive input end of the antenna and the negative input end of the antenna; wherein the fourth capacitor has a capacitance value C a The first resistor has a resistance value R a The antenna inductance has an inductance value L a The method comprises the steps of carrying out a first treatment on the surface of the Wherein the working angular frequency of the antenna network is omega, and the target impedance is a resistance value R t The EMC filter has a cut-off angular frequency ω r0 And (2) and
an embodiment of the application discloses an antenna network for receiving a chip transmitting end positive signal and a chip transmitting end negative signal from a chip to generate an antenna signal, comprising: electromagnetic compatibility EMC filter, including positive input, negative input, positive output and negative output, wherein positive input is used for receiving the chip transmitting end positive end signal, negative input is used for receiving the chip transmitting end negative end signal, the equivalent model of EMC filter includes: a first positive end inductance is equivalently coupled between the positive input end of the EMC filter and the positive output end of the EMC filter; a first negative side inductance is equivalently coupled between the negative input of the EMC filter and the negative output of the EMC filter; the first positive end capacitor is equivalently coupled between the positive output end of the EMC filter and the ground voltage; and a first negative terminal capacitively coupled between the negative output of the EMC filter and the ground voltage; wherein the first positive side inductor and the first negative side inductor both have an inductance value L 0 The first positive side capacitor and the first negative side capacitor both have a capacitance value C 0 The method comprises the steps of carrying out a first treatment on the surface of the Matching circuitThe input end of the matching circuit is coupled with the positive output end of the EMC filter, the negative input end of the matching circuit is coupled with the negative output end of the EMC filter, and an equivalent model of the matching circuit comprises: a second positive terminal capacitance equivalent is coupled between the positive input terminal of the matching circuit and the positive output terminal of the matching circuit; a second negative terminal is capacitively coupled between the negative input of the matching circuit and the negative output of the matching circuit; the third positive end capacitor is equivalently coupled between the positive output end of the matching circuit and the ground voltage; and a third negative terminal capacitively coupled between the negative output of the matching circuit and the ground voltage; wherein the second positive side capacitor and the second negative side capacitor both have a capacitance value C 1 The third positive side capacitor and the third negative side capacitor both have a capacitance value C 2 The method comprises the steps of carrying out a first treatment on the surface of the A Q-factor (Q-factor) reducing circuit comprising a positive input, a negative input, a positive output and a negative output, the positive input of the Q-factor reducing circuit being coupled to the positive output of the matching circuit, the negative input of the Q-factor reducing circuit being coupled to the negative output of the matching circuit, wherein an equivalent model of the Q-factor reducing circuit comprises: the second positive end resistor is equivalently coupled between the positive input end of the Q value reduction circuit and the positive output end of the Q value reduction circuit; and a second negative side resistor is equivalently coupled between the negative input terminal of the Q-down circuit and the negative output terminal of the Q-down circuit; wherein the second positive terminal resistor and the second negative terminal resistor both have a resistance value R q The method comprises the steps of carrying out a first treatment on the surface of the The antenna comprises a positive input end and a negative input end, wherein the positive input end of the antenna is coupled with the positive output end of the Q value reduction circuit, the negative input end of the antenna is coupled with the negative output end of the Q value reduction circuit, and an equivalent model of the antenna comprises: a fourth capacitive equivalent is coupled between the positive input of the antenna and the negative input of the antenna; and the first resistor and the antenna inductance are equivalently connected in series with the antennaBetween the positive input and the negative input of the antenna; wherein the fourth capacitor has a capacitance value C a The first resistor has a resistance value R a The antenna inductance has an inductance value L a The method comprises the steps of carrying out a first treatment on the surface of the Wherein the working angular frequency of the antenna network is omega, and the target impedance is a resistance value R t The EMC filter has a cut-off angular frequency ω r0 And (2) and
an embodiment of the application discloses an electronic device, which comprises a chip, a first power supply, a second power supply, a third power supply, a fourth power supply, a fifth power supply and a fourth power supply, wherein the chip is provided with a positive output end and a negative output end; and the antenna network described above, wherein the positive output terminal of the chip is coupled to the positive input terminal of the EMC filter of the antenna network, and the negative output terminal of the chip is coupled to the negative input terminal of the EMC filter of the antenna network.
The antenna network and the related electronic device can obtain larger bandwidth and higher antenna Q value through innovative element arrangement, thereby realizing longer communication distance.
Drawings
Fig. 1 is a representation of the impedance of an asymmetrically tuned antenna network on a smith chart.
Fig. 2 is a representation of the impedance of a symmetrically tuned antenna network on a smith chart.
Fig. 3 is a schematic diagram of a first embodiment of an antenna network according to the present application.
Fig. 4 is a schematic diagram of a second embodiment of an antenna network according to the present application.
Detailed Description
The following disclosure provides various embodiments or examples that can be used to implement the various features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. It is to be understood that these descriptions are merely exemplary and are not intended to limit the present disclosure. For example, in the following description, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may include embodiments in which additional components are formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. Such reuse is for brevity and clarity purposes and does not itself represent a relationship between the different embodiments and/or configurations discussed.
Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. However, any numerical value inherently contains certain standard deviations found in their respective testing measurements. As used herein, "about" generally means that the actual value is within plus or minus 10%, 5%, 1% or 0.5% of a particular value or range. Alternatively, the term "about" means that the actual value falls within an acceptable standard error of the average value, depending on the consideration of the person having ordinary skill in the art to which the present application pertains. It is to be understood that all ranges, amounts, values, and percentages used herein (e.g., to describe amounts of materials, lengths of time, temperatures, operating conditions, ratios of amounts, and the like) are modified by the word "about" unless otherwise specifically indicated. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present specification and attached claims are approximations that may vary depending upon the desired properties. At least these numerical parameters should be construed as the number of significant digits and by applying ordinary rounding techniques. Herein, a numerical range is expressed as from one end point to another end point or between two end points; unless otherwise indicated, all numerical ranges recited herein include endpoints.
Compared to the conventional asymmetric tuning, the symmetric tuning can make the impedance of the antenna network approximately symmetric based on the real axis on the smith chart, and as shown in fig. 2, the horizontal axis is the real axis and the vertical axis is the imaginary axis. This has the advantage of enabling the antenna network to achieve a larger bandwidth and a higher antenna Q (quality factor) and thus a longer communication distance. In addition, the symmetrical tuning mode provided by the application can enable the research and development personnel to quickly and correctly obtain the values of all elements when designing the antenna network, and the time and the development cost can be saved without manual trial and error adjustment.
Fig. 3 is a schematic diagram of a first embodiment of an antenna network according to the present application, wherein the antenna network is used for generating an antenna signal according to a chip transmitting end positive signal and a chip transmitting end negative signal. As shown in fig. 3, the antenna network 100 includes an electromagnetic compatibility (EMC) filter 102, a matching circuit 104, and an antenna 108. It should be noted that the EMC filter 102, the matching circuit 104, and the antenna 108 are shown in fig. 1 as equivalent models of resistance, capacitance, and inductance, and can be implemented using virtually any element or structure, for example, a plurality of elements connected in series or parallel, so long as the equivalent models of resistance, capacitance, and inductance shown in fig. 1 are provided.
The EMC filter 102 is used to filter out unwanted higher harmonics from the signal source. The EMC filter 102 includes a positive input Ip0, a negative input In0, a positive output Op0, and a negative output On0, where the positive input Ip0 is used to receive the chip transmitting positive signal, the negative input In0 is used to receive the chip transmitting negative signal, and an equivalent model of the EMC filter 102 includes a first positive inductor 1022, a first negative inductor 1024, a first positive capacitor 1026, and a first negative capacitor 1028. Wherein the first positive inductor 1022 is equivalently coupled between the positive input Ip0 of the EMC filter 102 and the positive output Op0 of the EMC filter 102; the first negative side inductor 1024 is equivalently coupled between the negative input terminal In0 of the EMC filter 102 and the negative output terminal On0 of the EMC filter 102; the first positive terminal capacitor 1026 is equivalently coupled between the positive output Op0 of the EMC filter 102 and the ground voltage; and a first negative side capacitor 1028 equivalently coupled between the negative output terminal On0 of the EMC filter 102 and the ground voltage; wherein the first positive side inductor 1022 and the first negative side inductor 1024 both have an inductance value L 0 The first positive side capacitor 1026 and the first negative side capacitor 1028 both have a capacitance C 0 。
The matching circuit 104 is used to make the target impedance of the antenna network 100 pure. The matching circuit 104 includes a positive input terminal Ip1, a negative input terminal In1, a positive output terminal Op1, and a negative output terminal On1. The positive input terminal Ip1 of the matching circuit 104 is coupled to the positive output terminal Op0 of the EMC filter 102, the negative input terminal In1 of the matching circuit 104 is coupled to the negative output terminal On0 of the EMC filter 102, and the equivalent model of the matching circuit 104 includes a second positive terminal capacitor 1042, a second negative terminal capacitor 1044, a third positive terminal capacitor 1046, and a third negative terminal capacitor 1048. The second positive-side capacitor 1042 is equivalently coupled between the positive input terminal Ip1 of the matching circuit 104 and the positive output terminal Op1 of the matching circuit 104; the second negative side capacitor 1044 is equivalently coupled between the negative input terminal In1 of the matching circuit 104 and the negative output terminal On1 of the matching circuit 104; the third positive end capacitor 1046 is equivalently coupled between the positive output end Op1 of the matching circuit 104 and the ground voltage; and a third negative side capacitor 1048 equivalently coupled between the negative output terminal On1 of the matching circuit 104 and the ground voltage; wherein the second positive side capacitor 1042 and the second negative side capacitor 1044 both have a capacitance C 1 The third positive side capacitor 1046 and the third negative side capacitor 1048 each have a capacitance C 2 。
The antenna 108 includes a positive input terminal Ip3 and a negative input terminal In3, the positive input terminal Ip3 of the antenna 108 is coupled to the positive output terminal Op1 of the matching circuit 104, and the negative input terminal In3 of the antenna 108 is coupled to the negative output terminal On1 of the matching circuit 104. And an equivalent model of the antenna 108 includes a fourth capacitance 1082, a first resistance 1084, and an antenna inductance 1086. Wherein the fourth capacitor 1082 is equivalently coupled between the positive input Ip3 of the antenna 108 and the negative input In3 of the antenna 108; and the first resistor 1084 and the antenna inductance 1086 are equivalently connected In series between the positive input terminal Ip3 of the antenna 108 and the negative input terminal In3 of the antenna 108; wherein the fourth capacitor 1082 has a capacitance value C a The first resistor 1084 has a resistance value R a Antenna inductance 1086 has an inductance value L a 。
The antenna network 100 may be coupled to a chip to achieve various applications, such as coupling the positive input Ip0 and the negative input In0 of the EMC filter 102 of the antenna network 100 to the Near Field Communication (NFC) chip 110 to realize an electronic device capable of supporting NFC. As shown In fig. 3, the positive output terminal of the NFC chip 110 outputs the chip transmitting terminal positive terminal signal to the positive input terminal Ip0 of the EMC filter 102, and the negative output terminal of the NFC chip 110 outputs the chip transmitting terminal negative terminal signal to the negative input terminal In0 of the EMC filter 102.
In designing the antenna network 100, the configuration of the antenna 108 and parameters including the capacitance C are determined according to the application requirements a Resistance value R a Inductance value L a . In addition, the target impedance and the operating angular frequency ω of the antenna network 100 are determined according to the application requirements, for example, the operating frequency of the NFC chip is 13.56MHz, and the corresponding angular frequency is 2pi×13.56MHz. Specifically, the target impedance is determined according to the required minimum transmission distance or minimum output power of the NFC, the supply voltage of the NFC chip, and the maximum output current of the NFC chip. The smaller the target impedance is, the larger the maximum output current of the chip is, namely the larger the output power is, and the farther the NFC transmission distance is; and vice versa. Generally, the target impedance is set to maximize the output power of the NFC chip without exceeding the maximum output current of the NFC chip. In some applications, the target impedance may be set to minimize the output current of the NFC chip without being less than the minimum output power of the NFC chip. In this embodiment, the target impedance determined according to the application requirement only includes a resistance value R t I.e. the resistance value is not 0 and the reactance value is 0.
Fig. 2 shows a schematic diagram of the antenna network 100 when symmetric tuning is satisfied, wherein the impedance curve represents the impedance of the antenna network 100 as a function of frequency. The impedance curve of FIG. 2 intersects the real axis of the Smith chart at three resonance frequency points, respectively at angular frequencies ω, ω 1 Omega, omega 2 . Wherein the angular frequency omega is the working angular frequency omega, the corresponding impedance is the target impedance (being a pure resistor with a resistance value of R t ). And angular frequency omega 1 Omega, omega 2 The corresponding impedances are the same and are also pure resistors, but the values of the resistors are different from the target impedance. After the derivation, the cut-off angle frequency ω of the EMC filter 102 satisfying the above condition is obtained r0 Is in the range of
Then, the cut-off angle frequency omega of the EMC filter 102 is passed r0 And inductance value L 0 Capacitance value C 0 Capacitance C 2 Can obtain the inductance value satisfying the above conditionsCapacitance valueCapacitance value +.>Thus, when designing the antenna network 100, the above-mentioned cutoff angular frequency ω is determined according to known requirements r0 An angular frequency is selected within the range of (1) to obtain the inductance value L rapidly 0 Capacitance value C 0 Capacitance C 2 。
In addition, due to capacitance C 1 Only for balanced impedance mismatch, has no effect on achieving symmetrical tuning. In the present embodiment, the capacitance C 1 Is set asWherein R is 1 、G 2 And X 1 This can be obtained via the following equation:
in some cases, it may be desirable to control the Q of the antenna network 100, for example, when the Q is too high, the Q may need to be reduced. Fig. 4 is a schematic diagram of an antenna network according to the present applicationThe difference between the antenna network 200 and the antenna network 100 is that the antenna network 200 additionally adds the Q-down circuit 106 to control the Q. Specifically, the Q-down circuit 106 includes a positive input terminal Ip2, a negative input terminal In2, a positive output terminal Op2, and a negative output terminal On2, the positive input terminal Ip2 of the Q-down circuit 106 is coupled to the positive output terminal Op1 of the matching circuit 104, and the negative input terminal In2 of the Q-down circuit 106 is coupled to the negative output terminal On1 of the matching circuit 104. And the equivalent model of the Q-down circuit 106 includes a second positive terminal resistor 1062 and a second negative terminal resistor 1064. Wherein the second positive terminal resistor 1062 is equivalently coupled between the positive input terminal Ip2 of the Q-down circuit 106 and the positive output terminal Op2 of the Q-down circuit 106; and a second negative side resistor 1064 equivalently coupled between the negative input In2 of the Q-down circuit 106 and the negative output On2 of the Q-down circuit 106; wherein the second positive terminal resistor 1062 and the second negative terminal resistor 1064 each have a resistance R q 。
With the Q-down circuit 106, the antenna network 200 is required to meet a symmetrically tuned cut-off angular frequency ω r0 Inductance value L 0 Capacitance value C 0 Capacitance value C 1 Capacitance C 2 May differ from the antenna network 100. After a derivation similar to the foregoing, the cut-off angle frequency ω of the EMC filter 102 is obtained r0 Is in the range ofInductance value->Capacitance value->Capacitance value +.>And the capacitance value C 1 Set to->Wherein R is 1 、G 2 And X 1 Can be obtained by the following equationThe formula is obtained:
the application also provides an electronic device comprising a chip and an antenna network 100/200, wherein a positive output terminal of the chip is coupled to a positive input terminal Ip0 of the EMC filter 102 of the antenna network 100/200, and a negative output terminal of the chip is coupled to a negative input terminal In0 of the EMC filter 102 of the antenna network 100/200.
The foregoing description briefly sets forth features of certain embodiments of the application in order to provide a thorough understanding of the various aspects of the present disclosure to those skilled in the art. It will be appreciated by those skilled in the art that the present disclosure may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. It will be apparent to those skilled in the art that such equivalent embodiments are within the spirit and scope of the present disclosure, and that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure.

Claims (11)

1. An antenna network for receiving a chip transmit side positive signal and a chip transmit side negative signal from a chip to generate an antenna signal, comprising:
electromagnetic compatibility EMC filter, including positive input, negative input, positive output and negative output, wherein positive input is used for receiving the chip transmitting end positive end signal, negative input is used for receiving the chip transmitting end negative end signal, the equivalent model of EMC filter includes:
a first positive end inductance is equivalently coupled between the positive input end of the EMC filter and the positive output end of the EMC filter;
a first negative side inductance is equivalently coupled between the negative input of the EMC filter and the negative output of the EMC filter;
the first positive end capacitor is equivalently coupled between the positive output end of the EMC filter and the ground voltage; and
a first negative terminal capacitively coupled between the negative output of the EMC filter and the ground voltage;
wherein the first positive side inductor and the first negative side inductor both have an inductance value L 0 The said
The first positive end capacitor and the first negative end capacitor both have a capacitance value C 0 ；
The matching circuit comprises a positive input end, a negative input end, a positive output end and a negative output end, wherein the positive input end of the matching circuit is coupled with the positive output end of the EMC filter, the negative input end of the matching circuit is coupled with the negative output end of the EMC filter, and an equivalent model of the matching circuit comprises:
a second positive terminal capacitance equivalent is coupled between the positive input terminal of the matching circuit and the positive output terminal of the matching circuit;
a second negative terminal is capacitively coupled between the negative input of the matching circuit and the negative output of the matching circuit;
the third positive end capacitor is equivalently coupled between the positive output end of the matching circuit and the ground voltage; and
a third negative terminal is equivalently coupled between the negative output end of the matching circuit and the ground voltage;
wherein the second positive side capacitor and the second negative side capacitor both have a capacitance value C 1 The third positive side capacitor and the third negative side capacitor both have a capacitance value C 2 ；
The antenna comprises a positive input end and a negative input end, wherein the positive input end of the antenna is coupled with the positive output end of the matching circuit, the negative input end of the antenna is coupled with the negative output end of the matching circuit, and an equivalent model of the antenna comprises:
a fourth capacitive equivalent is coupled between the positive input of the antenna and the negative input of the antenna; and
the first resistor and the antenna inductance are equivalently connected in series between the positive input end of the antenna and the negative input end of the antenna;
wherein the fourth capacitor has a capacitance value C a The first resistor has a resistance value R a The antenna inductance has an inductance value L a ；
Wherein the working angular frequency of the antenna network is omega, and the target impedance is a resistance value R t The EMC filter has a cut-off angular frequency ω r0 And (2) and
2. the antenna network of claim 1, wherein the inductance value
3. The antenna network of claim 1, wherein the capacitance value
4. The antenna network of claim 1, wherein the capacitance value
5. The antenna network of claim 1, wherein the capacitance valueWherein R is 1 、G 2 And X 1 Is according to->And +.>Obtained.
6. An antenna network for receiving a chip transmit side positive signal and a chip transmit side negative signal from a chip to generate an antenna signal, comprising:
electromagnetic compatibility EMC filter, including positive input, negative input, positive output and negative output, wherein positive input is used for receiving the chip transmitting end positive end signal, negative input is used for receiving the chip transmitting end negative end signal, the equivalent model of EMC filter includes:
a first positive end inductance is equivalently coupled between the positive input end of the EMC filter and the positive output end of the EMC filter;
a first negative side inductance is equivalently coupled between the negative input of the EMC filter and the negative output of the EMC filter;
the first positive end capacitor is equivalently coupled between the positive output end of the EMC filter and the ground voltage; and
a first negative terminal capacitively coupled between the negative output of the EMC filter and the ground voltage;
wherein the first positive side inductor and the first negative side inductor both have an inductance value L 0 The said
The first positive end capacitor and the first negative end capacitor both have a capacitance value C 0 ；
The matching circuit comprises a positive input end, a negative input end, a positive output end and a negative output end, wherein the positive input end of the matching circuit is coupled with the positive output end of the EMC filter, the negative input end of the matching circuit is coupled with the negative output end of the EMC filter, and an equivalent model of the matching circuit comprises:
a second positive terminal capacitance equivalent is coupled between the positive input terminal of the matching circuit and the positive output terminal of the matching circuit;
a second negative terminal is capacitively coupled between the negative input of the matching circuit and the negative output of the matching circuit;
the third positive end capacitor is equivalently coupled between the positive output end of the matching circuit and the ground voltage; and
a third negative terminal is equivalently coupled between the negative output end of the matching circuit and the ground voltage;
wherein the second positive side capacitor and the second negative side capacitor both have a capacitance value C 1 The third positive side capacitor and the third negative side capacitor both have a capacitance value C 2 ；
The positive input end of the quality-reducing factor circuit is coupled with the positive output end of the matching circuit, the negative input end of the quality-reducing factor circuit is coupled with the negative output end of the matching circuit, and an equivalent model of the quality-reducing factor circuit comprises:
a second positive terminal resistor is equivalently coupled between the positive input terminal of the degradation factor circuit and the positive output terminal of the degradation factor circuit; and
a second negative terminal resistor is equivalently coupled between the negative input terminal of the degradation factor circuit and the negative output terminal of the degradation factor circuit;
wherein the second positive terminal resistor and the second negative terminal resistor both have a resistance value R q ；
The antenna comprises a positive input end and a negative input end, wherein the positive input end of the antenna is coupled with the positive output end of the quality-reducing factor circuit, the negative input end of the antenna is coupled with the negative output end of the quality-reducing factor circuit, and an equivalent model of the antenna comprises:
a fourth capacitive equivalent is coupled between the positive input of the antenna and the negative input of the antenna; and
the first resistor and the antenna inductance are equivalently connected in series between the positive input end of the antenna and the negative input end of the antenna;
wherein the fourth capacitor has a capacitance value C a The first resistor has a resistance value R a The antenna inductance has an inductance value L a ；
Wherein the working angular frequency of the antenna network is omega, and the target impedance is a resistance value R t The EMC filter has a cut-off angular frequency ω r0 And (2) and
7. the antenna network of claim 6, wherein the inductance value
8. The antenna network of claim 6, wherein the capacitance value
9. The antenna network of claim 6, wherein the capacitance value
10. The antenna network of claim 6, wherein the capacitance valueWherein R is 1 、G 2 And X 1 Is according to->Andobtained.
11. An electronic device, comprising:
the chip is provided with a positive output end and a negative output end, wherein the positive output end is used for outputting a signal of the positive end of the chip transmitting end, and the negative output end is used for outputting a signal of the negative end of the chip transmitting end; and
the antenna network of any one of claims 1-10, wherein the positive output of the chip is coupled to the positive input of the EMC filter of the antenna network and the negative output of the chip is coupled to the negative input of the EMC filter of the antenna network.
CN202110378200.0A 2021-04-08 2021-04-08 Antenna network and related electronic device Active CN115208441B (en)

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CN102999670A (en) * 2012-11-30 2013-03-27 复旦大学 Design method of 13.56MHz RFID (Radio Frequency Identification) card reader near-field antenna
CN207691797U (en) * 2017-12-25 2018-08-03 江苏航天大为科技股份有限公司 A kind of low potato masher antenna circuit
CN108399345A (en) * 2017-02-06 2018-08-14 恩智浦有限公司 NFC reader with self-seeker

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US20100321128A1 (en) * 2006-10-19 2010-12-23 Nxp, B.V. Transceiving circuit for contactless communication
US10108825B2 (en) * 2017-03-22 2018-10-23 Nxp B.V. NFC reader with remote antenna

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Publication number Priority date Publication date Assignee Title
CN102999670A (en) * 2012-11-30 2013-03-27 复旦大学 Design method of 13.56MHz RFID (Radio Frequency Identification) card reader near-field antenna
CN108399345A (en) * 2017-02-06 2018-08-14 恩智浦有限公司 NFC reader with self-seeker
CN207691797U (en) * 2017-12-25 2018-08-03 江苏航天大为科技股份有限公司 A kind of low potato masher antenna circuit

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