CN115208441A - Antenna network and related electronic device - Google Patents
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Abstract
The application discloses antenna network includes: an electromagnetic compatibility filter, a matching circuit, and an antenna. The application also discloses an antenna network, including: an electromagnetic compatibility filter, a matching circuit, a quality factor reducing circuit and an antenna. The application also discloses an electronic device, including: a chip having a positive output terminal and a negative output terminal; and the antenna network mentioned above, wherein the positive output terminal of the chip is coupled to the positive input terminal of the emc filter of the antenna network, and the negative output terminal of the chip is coupled to the negative input terminal of the emc filter of the antenna network.
Description
Technical Field
The present application relates to the field of signal transmission, and in particular, to an antenna network and a near field communication device for near field communication.
Background
In the field of near field communication, when designing an antenna, the problem of impedance matching between a near field communication control chip and the antenna needs to be considered, and when the impedance is more matched, the lower the reflected signal generated when a signal enters the antenna from the chip, the higher the power output from the chip to the antenna, and the higher the efficiency. In order to achieve impedance matching, a matching network needs to be provided between the antenna and the chip, and values of devices in the matching network need to be tuned. The antenna together with the matching network may be referred to as an antenna network. According to the circuit principle, the network impedance of the antenna network changes along with the change of the signal source frequency, the network impedance of the antenna network is pure resistance at certain specific frequency points, the output power to the antenna network is the highest, and the radiation magnetic field of the antenna is the strongest. Tuning is to make the network impedance of the antenna network a pure resistance at the operating frequency.
Most of the common tuning methods are asymmetric tuning, that is, although the ideal value of each tuned device can make the antenna network and the chip achieve impedance matching at the operating frequency, in practice, most of the tuning is detuned due to errors, and when the antenna network tuned asymmetrically is detuned, the impedance seen from the chip to the antenna network is in an asymmetric form on the basis of the real axis on the smith chart, as shown in fig. 1. However, the bandwidth and antenna quality factor (Q value) obtained by asymmetric tuning are less desirable, resulting in limited communication distance and need to be further improved.
Disclosure of Invention
An objective of the present application is to disclose an antenna network and a related electronic device, so as to solve the above problems.
An embodiment of the present application discloses an antenna network for receiving a chip transmitting end positive end signal and a chip transmitting end negative end signal from a chip to generate an antenna signal, including: electromagnetic compatibility EMC wave filter, including positive input, negative input, positive output and negative output, wherein positive input is used for receiving chip transmitting terminal positive end signal, the negative input is used for receiving chip transmitting terminal negative end signal, EMC wave filter's equivalent model includes: a first positive side inductance is equivalently coupled between the positive input terminal of the EMC filter and the positive output terminal of the EMC filter; a first negative side inductance is equivalently coupled between the negative input terminal of the EMC filter and the negative output terminal of the EMC filter; a first positive side capacitor is equivalently coupled between the positive output terminal of the EMC filter and a ground voltage; and a first negative terminal capacitance is equivalently coupled between the negative output terminal of the EMC filter and the ground voltage; wherein the first positive side inductor and the first negative side inductor both have an inductance value L 0 The first positive side capacitor and the first negative side capacitor both have capacitance C 0 (ii) a A matching circuit comprising a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal, the positive input terminal of the matching circuit being coupled to the EMC filterThe negative input terminal of the matching circuit is coupled to the negative output terminal of the EMC filter, wherein an equivalent model of the matching circuit comprises: a second positive side capacitor equivalently coupled between the positive input of the matching circuit and the positive output of the matching circuit; a second negative side capacitor is equivalently coupled between the negative input terminal of the matching circuit and the negative output terminal of the matching circuit; a third positive side capacitor is equivalently coupled between the positive output terminal of the matching circuit and the ground voltage; and a third negative side capacitor is equivalently coupled between the negative output end of the matching circuit and the ground voltage; wherein the second positive side capacitor and the second negative side capacitor both have a capacitance C 1 The third positive side capacitor and the third negative side capacitor both have capacitance C 2 (ii) a An antenna comprising a positive input terminal and a negative input terminal, the positive input terminal of the antenna being coupled to the positive output terminal of the matching circuit, the negative input terminal of the antenna being coupled to the negative output terminal of the matching circuit, wherein an equivalent model of the antenna comprises: a fourth capacitor is equivalently coupled between the positive input terminal of the antenna and the negative input terminal of the antenna; the first resistor and the antenna inductor are equivalently connected in series between the positive input end of the antenna and the negative input end of the antenna; wherein the fourth capacitor has a capacitance value C a The first resistor has a resistance value R a The antenna inductor has an inductance value L a (ii) a Wherein the working angular frequency of the antenna network is omega, and the target impedance is a resistance value R t Said EMC filter having a cut-off angular frequency ω r0 And is made of
An embodiment of the present application discloses an antenna network for receiving a chip transmitting end positive end signal and a chip transmitting end negative end signal from a chip to generate an antenna signal, including: an electromagnetic compatibility (EMC) filter comprises a positive input end, a negative input end, a positive output end and a negative output end, wherein the positive input end is connected with the positive output end of the EMC filterThe input end is used for receiving the positive end signal of the chip transmitting end, the negative input end is used for receiving the negative end signal of the chip transmitting end, and the equivalent model of the EMC filter comprises: a first positive side inductance is equivalently coupled between the positive input terminal of the EMC filter and the positive output terminal of the EMC filter; a first negative side inductance is equivalently coupled between the negative input terminal of the EMC filter and the negative output terminal of the EMC filter; a first positive side capacitor is equivalently coupled between the positive output terminal of the EMC filter and a ground voltage; and a first negative side capacitance is equivalently coupled between the negative output terminal of the EMC filter and the ground voltage; wherein the first positive side inductor and the first negative side inductor both have inductance values L 0 The first positive side capacitor and the first negative side capacitor both have capacitance C 0 (ii) a A matching circuit comprising a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal, the positive input terminal of the matching circuit being coupled to the positive output terminal of the EMC filter, the negative input terminal of the matching circuit being coupled to the negative output terminal of the EMC filter, wherein an equivalent model of the matching circuit comprises: a second positive side capacitor is equivalently coupled between the positive input terminal of the matching circuit and the positive output terminal of the matching circuit; a second negative side capacitor is equivalently coupled between the negative input terminal of the matching circuit and the negative output terminal of the matching circuit; a third positive side capacitor is equivalently coupled between the positive output terminal of the matching circuit and the ground voltage; and a third negative end capacitor is equivalently coupled between the negative output end of the matching circuit and the ground voltage; wherein the second positive side capacitor and the second negative side capacitor both have a capacitance C 1 The third positive side capacitor and the third negative side capacitor both have capacitance C 2 (ii) a A quality factor (Q) reduction circuit comprising a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal, the positive input terminal of the Q reduction circuit being coupled to the positive output terminal of the matching circuit, the negative input terminal of the Q reduction circuit being coupled to the negative output terminal of the matching circuit, wherein the Q reduction circuit is equalThe effect model comprises: a second positive side resistor is equivalently coupled between the positive input terminal of the Q-drop circuit and the positive output terminal of the Q-drop circuit; and a second negative side resistor is equivalently coupled between the negative input terminal of the Q-drop circuit and the negative output terminal of the Q-drop circuit; wherein the second positive side resistor and the second negative side resistor both have a resistance R q (ii) a An antenna comprising a positive input terminal and a negative input terminal, the positive input terminal of the antenna being coupled to the positive output terminal of the Q-drop circuit, the negative input terminal of the antenna being coupled to the negative output terminal of the Q-drop circuit, wherein an equivalent model of the antenna comprises: a fourth capacitor is equivalently coupled between the positive input terminal of the antenna and the negative input terminal of the antenna; the first resistor and the antenna inductor are equivalently connected in series between the positive input end of the antenna and the negative input end of the antenna; wherein the fourth capacitor has a capacitance value C a The first resistor has a resistance value R a The antenna inductor has an inductance value L a (ii) a Wherein the working angular frequency of the antenna network is omega, and the target impedance is a resistance value R t Said EMC filter having a cut-off angular frequency ω r0 And is made of
An embodiment of the application discloses an electronic device, which comprises a chip, a first signal processing unit and a second signal processing unit, wherein the chip is provided with a positive output end and a negative output end, the positive output end is used for outputting a positive end signal of a chip transmitting end, and the negative output end is used for outputting a negative end signal of the chip transmitting end; and the antenna network described above, wherein the positive output of the chip is coupled to the positive input of the EMC filter of the antenna network, and the negative output of the chip is coupled to the negative input of the EMC filter of the antenna network.
The antenna network and the related electronic device can obtain larger bandwidth and higher Q value of the antenna through innovative element arrangement, thereby realizing longer communication distance.
Drawings
Figure 1 is a representation of the impedance of an asymmetrically tuned antenna network on a smith chart.
Figure 2 is a representation of the impedance of a symmetrically tuned antenna network on a smith chart.
Fig. 3 is a schematic diagram of a first embodiment of an antenna network of the present application.
Fig. 4 is a schematic diagram of a second embodiment of an antenna network of the present application.
Detailed Description
The following disclosure provides various embodiments or illustrations that can be used to implement various features of the disclosure. The specific embodiments of components and arrangements described below are provided to simplify the present disclosure. It is to be understood that such descriptions are merely illustrative and are not intended to limit the present disclosure. For example, in the description that follows, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may also include embodiments in which additional elements are formed between the first and second features described above, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Although numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain standard deviations found in their respective testing measurements. As used herein, "about" generally refers to actual values within 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, the term "about" indicates that the actual value falls within the acceptable standard error of the mean, subject to consideration by those of ordinary skill in the art to which this application pertains. It is understood that all ranges, amounts, values and percentages herein used (e.g., to describe amounts of materials, length of time, temperature, operating conditions, ratio of amounts, and the like) are modified by "about" in addition to the experimental examples, or unless otherwise expressly stated. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the specification and attached claims are approximations that may vary depending upon the desired properties sought to be obtained. At the very least, these numerical parameters are to be understood as meaning the number of significant digits and the number resulting from applying ordinary rounding techniques. Herein, numerical ranges are expressed from one end to the other or between the two ends; unless otherwise indicated, all numerical ranges set forth herein are inclusive of the endpoints.
Compared with the conventional asymmetric tuning method, the symmetric tuning method can make the impedance of the antenna network substantially symmetric on the smith chart based on the real axis, as shown in fig. 2, where the horizontal axis is the real axis and the vertical axis is the imaginary axis. This has the advantage that a larger bandwidth and a higher antenna Q (quality factor) value can be achieved for the antenna network, thus enabling a longer communication distance. In addition, the symmetrical tuning mode provided by the application can enable research and development personnel to quickly and correctly obtain the values of all elements when designing the antenna network, manual trial and error adjustment is not needed, and time and development cost can be saved.
Fig. 3 is a schematic diagram of a first embodiment of an antenna network for generating an antenna signal according to a chip transmit side positive end signal and a chip transmit side negative end signal. As shown in fig. 3, the antenna network 100 includes an electromagnetic compatibility (EMC) filter 102, a matching circuit 104, and an antenna 108. It should be noted that the EMC filter 102, the matching circuit 104, and the antenna 108 are illustrated in fig. 1 by equivalent models of resistance, capacitance, and inductance, and can be implemented by using any components or configurations, for example, by connecting a plurality of components in series or in parallel, as long as the EMC filter has the equivalent models of resistance, capacitance, and inductance as shown in fig. 1.
The EMC filter 102 is used to filter out unwanted higher harmonics from the signal source. The EMC filter 102 includes a positive input terminal Ip0, a negative input terminal In0, a positive output terminal Op0, and a negative output terminal On0, wherein the positive input terminal Ip0 is for receiving the chip emitting terminal positive signal, and the negative input terminal Ip0 is for receiving the chip emitting terminal positive signalIn0 is used to receive the chip transmit side negative side signal, and the equivalent model of the EMC filter 102 includes a first positive side inductance 1022, a first negative side inductance 1024, a first positive side capacitance 1026, and a first negative side capacitance 1028. Wherein the first positive side inductance 1022 is equivalently coupled between the positive input terminal Ip0 of the EMC filter 102 and the positive output terminal Op0 of the EMC filter 102; the first negative side inductor 1024 is equivalently coupled between the negative input terminal In0 of the EMC filter 102 and the negative output terminal On0 of the EMC filter 102; the first positive side capacitor 1026 is equivalently coupled between the positive output terminal Op0 of the EMC filter 102 and the ground voltage; the first negative terminal capacitor 1028 is equivalently coupled between the negative output terminal On0 of the EMC filter 102 and the ground voltage; wherein the first positive side inductor 1022 and the first negative side inductor 1024 both have inductance L 0 The first positive side capacitor 1026 and the first negative side capacitor 1028 both have capacitance C 0 。
The antenna 108 includes a positive input terminal Ip3 and a negative input terminal In3, the positive input terminal Ip3 of the antenna 108 is electrically coupled to the matching circuit 104The positive output port Op1 of the circuit and the negative input port In3 of the antenna 108 are coupled to the negative output port On1 of the matching circuit 104. And the equivalent model of the antenna 108 includes a fourth capacitor 1082, a first resistor 1084, and an antenna inductance 1086. Wherein the fourth capacitor 1082 is equivalently coupled between the positive input terminal Ip3 of the antenna 108 and the negative input terminal In3 of the antenna 108; the first resistor 1084 and the antenna inductor 1086 are equivalently connected In series between the positive input terminal Ip3 of the antenna 108 and the negative input terminal In3 of the antenna 108; wherein the fourth capacitor 1082 has a capacitance value C a The first resistor 1084 has a resistance value R a The antenna inductor 1086 has an inductance value L a 。
The antenna network 100 may be coupled to a chip for various applications, for example, the positive input Ip0 and the negative input In0 of the EMC filter 102 of the antenna network 100 are coupled to a Near Field Communication (NFC) chip 110, so as to implement an electronic device capable of supporting NFC. As shown In fig. 3, the positive output terminal of the NFC chip 110 outputs the chip transmit terminal positive end signal to the positive input terminal Ip0 of the EMC filter 102, and the negative output terminal of the NFC chip 110 outputs the chip transmit terminal negative end signal to the negative input terminal In0 of the EMC filter 102.
In designing the antenna network 100, the configuration and parameters of the antenna 108, including the capacitance C, are determined according to the application requirements a Resistance value R a And inductance value L a . In addition, the target impedance and the operating angular frequency ω of the antenna network 100 are determined according to application requirements, for example, the operating frequency of the NFC chip is 13.56MHz, and the corresponding angular frequency is 2 pi × 13.56MHz. Specifically, the target impedance is determined according to the required minimum transmission distance or minimum output power of the NFC chip, the supply voltage of the NFC chip, and the maximum output current of the NFC chip. The smaller the target impedance is, the larger the maximum output current of the chip is, namely the larger the output power is, the longer the NFC transmission distance is; and vice versa. Generally, the target impedance is set to maximize the output power of the NFC chip without exceeding the maximum output current of the NFC chip. However, in some applications, the target impedance may also be set to minimize the output current of the NFC chip without being less than the minimum output power of NFC. In the present embodiment, it is preferred that,the target impedance determined according to the application requirements only comprises a resistance value R t I.e. the resistance value is not 0 and the reactance value is 0.
Fig. 2 is a schematic diagram of the antenna network 100 satisfying the symmetric tuning, wherein the impedance curve represents the impedance of the antenna network 100 varying with the frequency. The impedance curves of FIG. 2 meet the real axes of the Smith chart at three resonant frequency points, which are the angular frequencies ω and ω, respectively 1 And omega 2 . Wherein the angular frequency ω is the working angular frequency ω, and the corresponding impedance is the target impedance (pure resistance, resistance value R) t ). And angular frequency omega 1 And omega 2 The corresponding impedances are the same and are also pure resistors, but the resistance values are different from the target impedance. After derivation, the cut-off angle frequency ω of the EMC filter 102 satisfying the above conditions is obtained r0 In the range of
Then, the cut-off angle frequency ω is further processed by the EMC filter 102 r0 And inductance value L 0 Capacitance value C 0 And a capacitance value C 2 The inductance value satisfying the above conditions can be obtained
Capacitance value
And a capacitance value
Thus, in designing the antenna network 100, the cut-off angular frequency ω is set at the above-mentioned cut-off angular frequency ω according to known requirements r0 By selecting an angular frequency within the range of (1), the inductance value L can be obtained quickly 0 Capacitance value C 0 And a capacitance value C 2 。
In addition, due to the capacitance C 1 Only used for balancing impedance mismatch and has no influence on realizing symmetric tuning. In this embodiment, the capacitance C can be set 1 Is set as
Wherein R is 1 、G 2 And X 1 Can be obtained via the following equation:
in some cases it may be desirable to control the Q of antenna network 100, for example, when the Q is too high, the Q may need to be decreased. Fig. 4 is a diagram illustrating a second embodiment of the antenna network of the present application, and the difference between the antenna network 200 and the antenna network 100 is that a Q-reduction circuit 106 is additionally added to the antenna network 200 to control the Q-value. Specifically, the Q-down circuit 106 comprises a positive input terminal Ip2, a negative input terminal In2, a positive output terminal Op2 and a negative output terminal On2, the positive input terminal Ip2 of the Q-down circuit 106 is coupled to the positive output terminal Op1 of the matching circuit 104, and the negative input terminal In2 of the Q-down circuit 106 is coupled to the negative output terminal On1 of the matching circuit 104. And the equivalent model of the de-Q circuit 106 includes a second positive side resistor 1062 and a second negative side resistor 1064. Wherein the second positive side resistor 1062 is equivalently coupled between the positive input terminal Ip2 of the Q-down circuit 106 and the positive output terminal Op2 of the Q-down circuit 106; the second negative side resistor 1064 is equivalently coupled between the negative input terminal In2 of the Q-down circuit 106 and the negative output terminal On2 of the Q-down circuit 106; the second positive side resistor 1062 and the second negative side resistor 1064 both have a resistance R q 。
With the Q-reduction circuit 106, the cut-off angular frequency ω of the antenna network 200 is symmetrically tuned r0 Inductance L 0 Capacitance value C 0 Capacitance value C 1 And a capacitance value C 2 Will be different from antenna network 100. After a derivation similar to the foregoing, the cut-off angle frequency ω of the EMC filter 102 is obtained r0 In the range of
Inductance value
Capacitance value
And a capacitance value
And a capacitance value C 1 Is arranged as
Wherein R is 1 、G 2 And X 1 Can be obtained via the following equation:
the present application further provides an electronic device comprising a chip and an antenna network 100/200, wherein a positive output of the chip is coupled to a positive input Ip0 of the EMC filter 102 of the antenna network 100/200 and a negative output of the chip is coupled to a negative input In0 of the EMC filter 102 of the antenna network 100/200.
The foregoing description has set forth briefly the features of certain embodiments of the present application so that those skilled in the art may more fully appreciate the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (11)
1. An antenna network for receiving a chip transmit side positive signal and a chip transmit side negative signal from a chip to generate an antenna signal, comprising:
electromagnetic compatibility (EMC) filter, including positive input end, negative input end, positive output end and negative output end, wherein positive input end is used for receiving chip transmitting terminal positive end signal, the negative input end is used for receiving chip transmitting terminal negative end signal, EMC filter's equivalent model includes:
a first positive side inductance is equivalently coupled between the positive input terminal of the EMC filter and the positive output terminal of the EMC filter;
a first negative side inductance is equivalently coupled between the negative input terminal of the EMC filter and the negative output terminal of the EMC filter;
a first positive side capacitor is equivalently coupled between the positive output terminal of the EMC filter and a ground voltage; and
a first negative side capacitor is equivalently coupled between the negative output terminal of the EMC filter and the ground voltage;
wherein the first positive side inductor and the first negative side inductor both have inductance values L 0 The first positive side capacitor and the first negative side capacitor both have capacitance C 0 ；
A matching circuit comprising a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal, the positive input terminal of the matching circuit being coupled to the positive output terminal of the EMC filter, the negative input terminal of the matching circuit being coupled to the negative output terminal of the EMC filter, wherein an equivalent model of the matching circuit comprises:
a second positive side capacitor is equivalently coupled between the positive input terminal of the matching circuit and the positive output terminal of the matching circuit;
a second negative end capacitor is equivalently coupled between the negative input end of the matching circuit and the negative output end of the matching circuit;
a third positive side capacitor is equivalently coupled between the positive output terminal of the matching circuit and the ground voltage; and
a third negative side capacitor is equivalently coupled between the negative output terminal of the matching circuit and the ground voltage;
wherein the second positive side capacitor and the second negative side capacitor both have a capacitance C 1 The third positive side capacitor and the third negative side capacitor both have a capacitance C 2 ；
An antenna comprising a positive input terminal and a negative input terminal, the positive input terminal of the antenna being coupled to the positive output terminal of the matching circuit, the negative input terminal of the antenna being coupled to the negative output terminal of the matching circuit, wherein an equivalent model of the antenna comprises:
a fourth capacitor is equivalently coupled between the positive input terminal of the antenna and the negative input terminal of the antenna; and
a first resistor and an antenna inductor are equivalently connected in series between the positive input end of the antenna and the negative input end of the antenna;
wherein the fourth capacitor has a capacitance value C a The first resistor has a resistance value R a The antenna inductor has an inductance value L a ；
Wherein the working angular frequency of the antenna network is omega, and the target impedance is a resistance value R t Said EMC filter having a cut-off angular frequency ω r0 And is and
2. an antenna network according to claim 1 wherein the inductance value
3. An antenna network according to claim 1, wherein the capacitance value is
4. An antenna network according to claim 1, wherein the capacitance value is
5. An antenna network according to claim 1, wherein the capacitance value is
Wherein
And
6. an antenna network for receiving a chip transmit side positive signal and a chip transmit side negative signal from a chip to generate an antenna signal, comprising:
electromagnetic compatibility EMC wave filter, including positive input, negative input, positive output and negative output, wherein positive input is used for receiving chip transmitting terminal positive end signal, the negative input is used for receiving chip transmitting terminal negative end signal, EMC wave filter's equivalent model includes:
a first positive side inductance is equivalently coupled between the positive input terminal of the EMC filter and the positive output terminal of the EMC filter;
a first negative side inductance is equivalently coupled between the negative input terminal of the EMC filter and the negative output terminal of the EMC filter;
a first positive side capacitor is equivalently coupled between the positive output terminal of the EMC filter and a ground voltage; and
a first negative side capacitor is equivalently coupled between the negative output terminal of the EMC filter and the ground voltage;
wherein the first positive side inductor and the first negative side inductor both have inductance values L 0 The first positive side capacitor and the first negative side capacitor both have a capacitance C 0 ；
A matching circuit comprising a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal, the positive input terminal of the matching circuit being coupled to the positive output terminal of the EMC filter, the negative input terminal of the matching circuit being coupled to the negative output terminal of the EMC filter, wherein an equivalent model of the matching circuit comprises:
a second positive side capacitor is equivalently coupled between the positive input terminal of the matching circuit and the positive output terminal of the matching circuit;
a second negative side capacitor is equivalently coupled between the negative input terminal of the matching circuit and the negative output terminal of the matching circuit;
a third positive side capacitor is equivalently coupled between the positive output terminal of the matching circuit and the ground voltage; and
a third negative side capacitor is equivalently coupled between the negative output terminal of the matching circuit and the ground voltage;
wherein the second positive side capacitor and the second negative side capacitor both have a capacitance C 1 The third positive side capacitor and the third negative side capacitor both have capacitance C 2 ；
A quality factor (Q) reduction circuit comprising a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal, the positive input terminal of the Q reduction circuit coupled to the positive output terminal of the matching circuit, the negative input terminal of the Q reduction circuit coupled to the negative output terminal of the matching circuit, wherein an equivalent model of the Q reduction circuit comprises:
a second positive side resistor is equivalently coupled between the positive input terminal of the Q-down circuit and the positive output terminal of the Q-down circuit; and
a second negative side resistor is equivalently coupled between the negative input terminal of the Q-drop circuit and the negative output terminal of the Q-drop circuit;
wherein the second positive end resistor and the second negative end resistor both have a resistance R q ；
An antenna comprising a positive input terminal and a negative input terminal, the positive input terminal of the antenna being coupled to the positive output terminal of the Q-drop circuit, the negative input terminal of the antenna being coupled to the negative output terminal of the Q-drop circuit, wherein an equivalent model of the antenna comprises:
a fourth capacitor is equivalently coupled between the positive input terminal of the antenna and the negative input terminal of the antenna; and
a first resistor and an antenna inductor are equivalently connected in series between the positive input end of the antenna and the negative input end of the antenna;
wherein the fourth capacitor has a capacitance value C a The first resistor has a resistance value R a The antenna inductor has an inductance value L a ；
Wherein the working angular frequency of the antenna network is omega, and the target impedance is a resistance value R t Said EMC filter having a cut-off angular frequency ω r0 And is and
7. an antenna network according to claim 6 wherein the inductance value is
8. An antenna network according to claim 6, wherein the capacitance value is
9. An antenna network according to claim 6, wherein the capacitance value is
10. An antenna network according to claim 6, wherein the capacitance value is
Wherein
And
11. an electronic device, comprising:
the chip is provided with a positive output end and a negative output end, wherein the positive output end is used for outputting a positive end signal of an emission end of the chip, and the negative output end is used for outputting a negative end signal of the emission end of the chip; and
an antenna network according to any of claims 1-10, wherein the positive output of the chip is coupled to the positive input of the EMC filter of the antenna network and the negative output of the chip is coupled to the negative input of the EMC filter of the antenna network.
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| CN202110378200.0A CN115208441B (en) | 2021-04-08 | 2021-04-08 | Antenna network and related electronic device |
| PCT/CN2021/137429 WO2022213649A1 (en) | 2021-04-08 | 2021-12-13 | Antenna network and related electronic device |
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| CN202110378200.0A CN115208441B (en) | 2021-04-08 | 2021-04-08 | Antenna network and related electronic device |
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| CN (1) | CN115208441B (en) |
| WO (1) | WO2022213649A1 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100321128A1 (en) * | 2006-10-19 | 2010-12-23 | Nxp, B.V. | Transceiving circuit for contactless communication |
| CN102999670A (en) * | 2012-11-30 | 2013-03-27 | 复旦大学 | Design method of 13.56MHz RFID (Radio Frequency Identification) card reader near-field antenna |
| CN207691797U (en) * | 2017-12-25 | 2018-08-03 | 江苏航天大为科技股份有限公司 | A kind of low potato masher antenna circuit |
| CN108399345A (en) * | 2017-02-06 | 2018-08-14 | 恩智浦有限公司 | NFC reader with self-seeker |
| US20180276426A1 (en) * | 2017-03-22 | 2018-09-27 | Nxp B.V. | Nfc reader with remote antenna |
-
2021
- 2021-04-08 CN CN202110378200.0A patent/CN115208441B/en active Active
- 2021-12-13 WO PCT/CN2021/137429 patent/WO2022213649A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100321128A1 (en) * | 2006-10-19 | 2010-12-23 | Nxp, B.V. | Transceiving circuit for contactless communication |
| CN102999670A (en) * | 2012-11-30 | 2013-03-27 | 复旦大学 | Design method of 13.56MHz RFID (Radio Frequency Identification) card reader near-field antenna |
| CN108399345A (en) * | 2017-02-06 | 2018-08-14 | 恩智浦有限公司 | NFC reader with self-seeker |
| US20180276426A1 (en) * | 2017-03-22 | 2018-09-27 | Nxp B.V. | Nfc reader with remote antenna |
| CN207691797U (en) * | 2017-12-25 | 2018-08-03 | 江苏航天大为科技股份有限公司 | A kind of low potato masher antenna circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2022213649A1 (en) | 2022-10-13 |
| CN115208441B (en) | 2023-10-27 |
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