CN216437159U - Rail-to-rail transconductance operational amplifier circuit - Google Patents
Rail-to-rail transconductance operational amplifier circuit Download PDFInfo
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- CN216437159U CN216437159U CN202123035071.XU CN202123035071U CN216437159U CN 216437159 U CN216437159 U CN 216437159U CN 202123035071 U CN202123035071 U CN 202123035071U CN 216437159 U CN216437159 U CN 216437159U
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Abstract
The utility model discloses a rail-to-rail transconductance operational amplifier circuit, which relates to the technical field of circuits and comprises a P-type MOS tube MP1, a P-type MOS tube MP2, a P-type MOS tube MP3, a P-type MOS tube MP4, a P-type MOS tube MP5, a P-type MOS tube MP6, a P-type MOS tube MP7, a P-type MOS tube MP8, a P-type MOS tube MP9, a P-type MOS tube MP10, a P-type MOS tube MP11, a P-type MOS tube MP12, an N-type MOS tube MN1, an N-type MOS tube MN2, an N-type MOS tube MN3, an N-type MOS tube MN4, an N-type MOS tube MN5, an N-type MOS tube MN6, an N-type MOS tube MN7, an N-type MOS tube MN8, an N-type MOS tube MN9, an N-type MOS tube MN10, an N-type MOS tube MN11, an N-type MOS tube MN12, an N-type MOS tube MN13, the rail-to-rail transconductance operational amplifier is a simple double-input-stage structure, one is an N-type input pair, the other is a P-type input pair, the rail-to-rail input is realized, and the outputs of the two input pairs are combined on one output node in a simple mode to realize the rail-to-rail output.
Description
Technical Field
The utility model relates to the technical field of circuits, especially, relate to a rail is to rail transconductance operational amplifier circuit.
Background
In recent years, along with the continuous development of integrated circuit design technology, transconductance amplifiers are increasingly applied to the field of analog integrated circuit design, along with the continuous progress of integrated circuit manufacturing process, power supply voltage is continuously reduced, the voltage swing of the traditional sleeve type gain stage structure formed by connecting a plurality of MOS (metal oxide semiconductor) tubes in series can be obviously compressed, the application under low power supply voltage is not suitable, the cascade structure of the plurality of gain stages can effectively realize the purpose of high gain, and meanwhile, under the low power supply voltage, larger voltage swing can be effectively kept. However, the cascade structure of multiple gain stages has great difficulty in compensation technology, and in most of the application occasions of the multi-stage transconductance amplifiers, in order to make the transconductance amplifier obtain a large phase margin and ensure the stability of the transconductance amplifier, the frequency compensation is performed on the transconductance amplifier.
However, the conventional frequency compensation technology for the transconductance amplifier still obtains an ideal phase margin by reducing the frequency of the main pole in the frequency domain through pole splitting, but the reduced main pole can reduce the-3 dB bandwidth, thereby greatly reducing the unit gain bandwidth of the transconductance amplifier. Meanwhile, the traditional compensation technology cannot change the fact that the voltage slew rate of the transconductance amplifier is low. Or, a left half-plane zero point with a higher frequency and a first non-dominant pole are introduced to offset, so that a larger phase margin is obtained, and meanwhile, a three-stage transconductance amplifier structure is utilized to realize a ClassAB output stage and improve the voltage slew rate of the transconductance amplifier.
However, the frequency of the first non-dominant pole is usually low, and the frequency of the left half-plane zero generated by the conventional method is relatively high, which requires that the capacitance value of the compensation capacitor is designed to be very large, so that on one hand, the layout area is increased, and on the other hand, the frequency of the dominant pole is also reduced, thereby reducing the-3 dB bandwidth and the unit gain bandwidth, so that the voltage slew rate of the transconductance amplifier is still low, and the current situation that the quality factor of the transconductance amplifier is still not high cannot be changed.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problem that not enough to the background art provides a rail to rail transconductance fortune and puts circuit, and this rail is put to rail transconductance fortune is simple dual input level structure, and one is N type input right, and one is P type input right, has realized that the input rail is to the rail, and two inputs output right combine on an output node with simple mode, realize that the output rail is to the rail.
The utility model discloses a solve above-mentioned technical problem and adopt following technical scheme:
a rail-to-rail transconductance operational amplifier circuit comprises a P-type MOS tube MP1, a P-type MOS tube MP2, a P-type MOS tube MP3, a P-type MOS tube MP4, a P-type MOS tube MP5, a P-type MOS tube MP6, a P-type MOS tube MP7, a P-type MOS tube MP8, a P-type MOS tube MP9, a P-type MOS tube MP10, a P-type MOS tube MP11, a P-type MOS tube MP12, an N-type MOS tube MN1, an N-type MOS tube MN2, an N-type MOS tube MN3, an N-type MOS tube MN4, an N-type MOS tube MN5, an N-type MOS tube MN6, an N-type MOS tube 7, an N-type MOS tube 8, an N-type MOS tube MN9, an N-type MOS tube MN10, an N-type MOS tube MN11, an N-type MOS tube MN12, an N-type MOS tube MN13, a VDD, a voltage end, a voltage V voltage end, an IAUT voltage V end 1, a V end 36 2 and a V end 36 2,
wherein, the VBIAS voltage end is respectively connected with the grid of the N-type MOS transistor MN1 and the grid of the N-type MOS transistor MN5, the drain of the N-type MOS transistor MN1 is connected with the source of the N-type MOS transistor MN2, the grid of the N-type MOS transistor MN2 is connected with the VB voltage end, the drain of the N-type MOS transistor MN2 is respectively connected with the grid of the P-type MOS transistor MP1, the drain of the P-type MOS transistor MP1 and the grid of the P-type MOS transistor MP7, the source of the P-type MOS transistor MP1 is respectively connected with the source of the P-type MOS transistor MP2, the source of the P-type MOS transistor MP3, the source of the P-type MOS transistor MP4, the source of the P-type MOS transistor MP5, the source of the P-type MOS transistor MP6, the source of the P-type MOS transistor MP6, the source of the P-type MOS transistor MP8, the drain of the P-type MOS transistor MP2 is respectively connected with the drain of the N-type MOS transistor MN3, the grid of the N-type MOS transistor MN, the gate of the N-type MOS transistor MN3, the source of the N-type MOS transistor MN 5475, the source of the N-type MOS transistor MN1, and the source of the N1 are respectively connected with the source of the N-type MOS transistor MN1, the drain of the N1 and the N-type MOS transistor MN1, A source electrode of an N-type MOS transistor MN11, a source electrode of an N-type MOS transistor MN12, a source electrode of an N-type MOS transistor MN13, a drain electrode of the N-type MOS transistor MN5 is connected with a source electrode of an N-type MOS transistor MN6 and a source electrode of an N-type MOS transistor MN7, a drain electrode of the N-type MOS transistor MN6 is connected with a source electrode of an N-type MOS transistor MN8, a gate electrode of the N-type MOS transistor MN6 is connected with a V1 voltage terminal, a gate electrode of the N-type MOS transistor MN8 is connected with a VB voltage terminal, a drain electrode of the N-type MOS transistor MN8 is connected with a gate electrode of a P-type MOS transistor MP2, a gate electrode of a P-type MOS transistor MP3 and a drain electrode of a P-type MOS transistor MP3, a gate electrode of the N-type MOS transistor MN 38723 voltage terminal is connected with the VB gate electrode of the N-type MOS transistor MN 466, a drain electrode of the N-type MOS transistor MN7 is connected with a source electrode of the N-type MOS transistor MN9, a gate electrode of the N-type MOS transistor MN2 is connected with a P-type MOS transistor MP voltage terminal, a drain electrode of the N-type MOS transistor MN4 is connected with a drain electrode of the P-type MOS transistor MN4, a drain electrode of the MN4, and a drain electrode of the MN4, and a P-type MOS transistor MN4, and a drain electrode of the MOS transistor MN4 of the MN4, and a drain electrode of the MOS transistor MN4, a transistor MN4 are connected with an MN4, and a drain electrode of the MOS transistor MN4, and an MOS transistor MN4, and a drain electrode of the MOS transistor MN4, and a MOS transistor MN4, a drain electrode of the MOS transistor MN4, a drain electrode of the MOS transistor MN4, a drain electrode of an MN4, a drain electrode of a MOS transistor MN4, a drain electrode of a MOS transistor MN4, a MOS transistor, The drain electrode of the P-type MOS tube MP6, the drain electrode of the N-type MOS tube MN10, the grid electrode of the P-type MOS tube MP6 is respectively connected with the grid electrode of the P-type MOS tube MP8, the drain electrode of the P-type MOS tube MP8 and the drain electrode of the N-type MOS tube MN13, the grid electrode of the N-type MOS tube MN13 is respectively connected with the grid electrode of the N-type MOS tube MN12, the drain electrode of the N-type MOS tube MN12, the drain electrode of the P-type MOS tube MP12, the gate electrode of the P-type MOS tube MP12 is connected with the VC voltage end, the source electrode of the P-type MOS tube MP12 is connected with the drain electrode of the P-type MOS tube MP10, the gate electrode of the P-type MOS tube MP10 is connected with the V1 voltage end, the source electrode of the P-type MOS tube MP10 is respectively connected with the drain electrode of the P-type MOS tube MP7 and the source electrode of the P-type MOS tube MP9, the gate electrode of the P-type MOS tube MP9 is connected with the V2 voltage end, the drain electrode of the P-type MOS tube MP9 is connected with the source electrode of the P-type MOS tube MP11, the gate electrode of the P-type MOS tube 11 is connected with the VC voltage end, and the drain electrode of the P-type MOS tube MP11 is respectively connected with the gate electrode of the N-type MOS tube MN10, the gate electrode of the N-type MOS tube MN11 and the drain electrode of the N-type MOS tube MN 11.
As a further preferred scheme of the rail-to-rail transconductance operational amplifier circuit of the utility model, VB voltage end, VC voltage end, VBIAS voltage end are three bias voltage, constitute bias circuit by N type MOS pipe MN1, N type MOS pipe MN2 and P type MOS pipe MP 1.
The utility model adopts the above technical scheme to compare with prior art, have following technological effect:
the utility model relates to a rail is to rail transconductance operational amplifier circuit, this rail is to rail transconductance operational amplifier is simple dual input level structure, one is that N type input is right, one is P type input right, it is right to have realized the input rail, the output that two inputs are right combines on an output node with simple mode, realize that the output rail is to the rail, its rail is to rail transconductance operational amplifier circuit total gain does not have two-stage operational amplifier circuit height, but power consumption can be much lower than two-stage operational amplifier circuit, this circuit also need not the miller compensation, also there is very wide bandwidth.
Drawings
Fig. 1 is a circuit diagram of a rail-to-rail transconductance operational amplifier circuit according to the present invention.
Detailed Description
The technical scheme of the utility model is further explained in detail with the attached drawings as follows:
the technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
A rail-to-rail transconductance operational amplifier circuit comprises a P-type MOS tube MP1, a P-type MOS tube MP2, a P-type MOS tube MP3, a P-type MOS tube MP4, a P-type MOS tube MP5, a P-type MOS tube MP6, a P-type MOS tube MP7, a P-type MOS tube MP8, a P-type MOS tube MP9, a P-type MOS tube MP10, a P-type MOS tube MP11, a P-type MOS tube MP12, an N-type MOS tube MN1, an N-type MOS tube MN2, an N-type MOS tube MN3, an N-type MOS tube MN4, an N-type MOS tube MN5, an N-type MOS tube MN6, an N-type MOS tube 7, an N-type MOS tube 8, an N-type MOS tube MN9, an N-type MOS tube MN10, an N-type MOS tube MN11, an N-type MOS tube MN12, an N-type MOS tube MN13, a VDD, a voltage end, a voltage V voltage end, an IAUT voltage V end 1, a V end 36 2 and a V end 36 2,
wherein, the VBIAS voltage end is respectively connected with the grid of the N-type MOS transistor MN1 and the grid of the N-type MOS transistor MN5, the drain of the N-type MOS transistor MN1 is connected with the source of the N-type MOS transistor MN2, the grid of the N-type MOS transistor MN2 is connected with the VB voltage end, the drain of the N-type MOS transistor MN2 is respectively connected with the grid of the P-type MOS transistor MP1, the drain of the P-type MOS transistor MP1 and the grid of the P-type MOS transistor MP7, the source of the P-type MOS transistor MP1 is respectively connected with the source of the P-type MOS transistor MP2, the source of the P-type MOS transistor MP3, the source of the P-type MOS transistor MP4, the source of the P-type MOS transistor MP5, the source of the P-type MOS transistor MP6, the source of the P-type MOS transistor MP6, the source of the P-type MOS transistor MP8, the drain of the P-type MOS transistor MP2 is respectively connected with the drain of the N-type MOS transistor MN3, the grid of the N-type MOS transistor MN, the gate of the N-type MOS transistor MN3, the source of the N-type MOS transistor MN 5475, the source of the N-type MOS transistor MN1, and the source of the N1 are respectively connected with the source of the N-type MOS transistor MN1, the drain of the N1 and the N-type MOS transistor MN1, A source electrode of an N-type MOS transistor MN11, a source electrode of an N-type MOS transistor MN12, a source electrode of an N-type MOS transistor MN13, a drain electrode of the N-type MOS transistor MN5 is connected with a source electrode of an N-type MOS transistor MN6 and a source electrode of an N-type MOS transistor MN7, a drain electrode of the N-type MOS transistor MN6 is connected with a source electrode of an N-type MOS transistor MN8, a gate electrode of the N-type MOS transistor MN6 is connected with a V1 voltage terminal, a gate electrode of the N-type MOS transistor MN8 is connected with a VB voltage terminal, a drain electrode of the N-type MOS transistor MN8 is connected with a gate electrode of a P-type MOS transistor MP2, a gate electrode of a P-type MOS transistor MP3 and a drain electrode of a P-type MOS transistor MP3, a gate electrode of the N-type MOS transistor MN 38723 voltage terminal is connected with the VB gate electrode of the N-type MOS transistor MN 466, a drain electrode of the N-type MOS transistor MN7 is connected with a source electrode of the N-type MOS transistor MN9, a gate electrode of the N-type MOS transistor MN2 is connected with a P-type MOS transistor MP voltage terminal, a drain electrode of the N-type MOS transistor MN4 is connected with a drain electrode of the P-type MOS transistor MN4, a drain electrode of the MN4, and a drain electrode of the MN4, and a P-type MOS transistor MN4, and a drain electrode of the MOS transistor MN4 of the MN4, and a drain electrode of the MOS transistor MN4, a transistor MN4 are connected with an MN4, and a drain electrode of the MOS transistor MN4, and an MOS transistor MN4, and a drain electrode of the MOS transistor MN4, and a MOS transistor MN4, a drain electrode of the MOS transistor MN4, a drain electrode of the MOS transistor MN4, a drain electrode of an MN4, a drain electrode of a MOS transistor MN4, a drain electrode of a MOS transistor MN4, a MOS transistor, The drain electrode of the P-type MOS tube MP6, the drain electrode of the N-type MOS tube MN10, the grid electrode of the P-type MOS tube MP6 is respectively connected with the grid electrode of the P-type MOS tube MP8, the drain electrode of the P-type MOS tube MP8 and the drain electrode of the N-type MOS tube MN13, the grid electrode of the N-type MOS tube MN13 is respectively connected with the grid electrode of the N-type MOS tube MN12, the drain electrode of the N-type MOS tube MN12, the drain electrode of the P-type MOS tube MP12, the gate electrode of the P-type MOS tube MP12 is connected with the VC voltage end, the source electrode of the P-type MOS tube MP12 is connected with the drain electrode of the P-type MOS tube MP10, the gate electrode of the P-type MOS tube MP10 is connected with the V1 voltage end, the source electrode of the P-type MOS tube MP10 is respectively connected with the drain electrode of the P-type MOS tube MP7 and the source electrode of the P-type MOS tube MP9, the gate electrode of the P-type MOS tube MP9 is connected with the V2 voltage end, the drain electrode of the P-type MOS tube MP9 is connected with the source electrode of the P-type MOS tube MP11, the gate electrode of the P-type MOS tube 11 is connected with the VC voltage end, and the drain electrode of the P-type MOS tube MP11 is respectively connected with the gate electrode of the N-type MOS tube MN10, the gate electrode of the N-type MOS tube MN11 and the drain electrode of the N-type MOS tube MN 11.
The rail-to-rail transconductance operational amplifier is a simple double-input-stage structure, one is an N-type input pair, the other is a P-type input pair, the rail-to-rail input is realized, and the outputs of the two input pairs are combined on one output node in a simple mode to realize the rail-to-rail output.
The VB voltage end, the VC voltage end and the VBIAS voltage end are three bias voltages, and an N-type MOS tube MN1, an N-type MOS tube MN2 and a P-type MOS tube MP1 form a bias circuit. After power-on, the bias circuit provides bias current for respective differential pair transistors through a current mirror P-type MOS transistor MP10 and a transistor P-type MOS transistor MP5, the output transistor is connected with drains of the P-type MOS transistor MP5, the N-type MOS transistor MN4 and the N-type MOS transistor MN10, and output current is superposed.
The utility model discloses when utilizing N type and P type transconductance amplifier hybrid circuit, this circuit has increased common mode input voltage range effectively.
The single-side N-type transconductance amplifier circuit comprises an input differential pair, three current mirrors and a current source: the cascode differential pair transistor comprises a cascode differential pair transistor N-type MOS transistor MN6, an N-type MOS transistor MN8, an N-type MOS transistor MN7 and an N-type MOS transistor MN 9; the ratio of the current mirror P-type MOS tube MP2, the P-type MOS tube MP3, the P-type MOS tube MP4 and the P-type MOS tube MP5 is 1: B, the ratio of the current mirror P-type MOS tube MP5 and the N-type MOS tube MN10 is 1:1, and the current source N-type MOS tube MN5 provides bias current.
The total gain of the rail-to-rail transconductance operational amplifier circuit is not higher than that of a two-stage operational amplifier circuit, but the power consumption of the rail-to-rail transconductance operational amplifier circuit is much lower than that of the two-stage operational amplifier circuit, the rail-to-rail transconductance operational amplifier circuit does not need Miller compensation, and the rail-to-rail transconductance operational amplifier circuit has wide bandwidth.
While certain exemplary embodiments of the present invention have been described above by way of illustration only, it will be apparent to those of ordinary skill in the art that the described embodiments may be modified in various different ways without departing from the spirit and scope of the present invention. Accordingly, the drawings and description are illustrative in nature and should not be construed as limiting the scope of the invention.
Claims (2)
1. A rail-to-rail transconductance operational amplifier circuit, comprising: comprises a P-type MOS tube MP1, a P-type MOS tube MP2, a P-type MOS tube MP3, a P-type MOS tube MP4, a P-type MOS tube MP5, a P-type MOS tube MP6, a P-type MOS tube MP7, a P-type MOS tube MP8, a P-type MOS tube MP9, a P-type MOS tube MP10, a P-type MOS tube MP11, a P-type MOS tube MP12, an N-type MOS tube MN1, an N-type MOS tube MN2, an N-type MOS tube MN3, an N-type MOS tube MN4, an N-type MOS tube MN5, an N-type MOS tube MN6, an N-type MOS tube MN7, an N-type MOS tube MN8, an N-type MOS tube MN9, an N-type MOS tube MN10, an N-type MOS tube MN11, an N-type MOS tube MN12, an N-type MOS tube MN13, a voltage end VDD, a VB voltage end, a VBS voltage end, a V voltage end, an IAS voltage end, a V voltage end 1, a V current output end and a VC 2,
wherein, the VBIAS voltage end is respectively connected with the grid of the N-type MOS transistor MN1 and the grid of the N-type MOS transistor MN5, the drain of the N-type MOS transistor MN1 is connected with the source of the N-type MOS transistor MN2, the grid of the N-type MOS transistor MN2 is connected with the VB voltage end, the drain of the N-type MOS transistor MN2 is respectively connected with the grid of the P-type MOS transistor MP1, the drain of the P-type MOS transistor MP1 and the grid of the P-type MOS transistor MP7, the source of the P-type MOS transistor MP1 is respectively connected with the source of the P-type MOS transistor MP2, the source of the P-type MOS transistor MP3, the source of the P-type MOS transistor MP4, the source of the P-type MOS transistor MP5, the source of the P-type MOS transistor MP6, the source of the P-type MOS transistor MP6, the source of the P-type MOS transistor MP8, the drain of the P-type MOS transistor MP2 is respectively connected with the drain of the N-type MOS transistor MN3, the grid of the N-type MOS transistor MN, the gate of the N-type MOS transistor MN3, the source of the N-type MOS transistor MN 5475, the source of the N-type MOS transistor MN1, and the source of the N1 are respectively connected with the source of the N-type MOS transistor MN1, the drain of the N1 and the N-type MOS transistor MN1, A source of an N-type MOS transistor MN11, a source of an N-type MOS transistor MN12, a source of an N-type MOS transistor MN13, a drain of the N-type MOS transistor MN5 is connected to the source of the N-type MOS transistor MN6 and the source of the N-type MOS transistor MN7, a drain of the N-type MOS transistor MN6 is connected to the source of the N-type MOS transistor MN8, a gate of the N-type MOS transistor MN6 is connected to the V1 voltage terminal, a gate of the N-type MOS transistor MN8 is connected to the VB voltage terminal, a drain of the N-type MOS transistor MN8 is connected to the gate of the P-type MOS transistor MP2, a gate of the P-type MOS transistor MP3 and a drain of the P-type MOS transistor MP3, a gate of the N-type MOS transistor MN7 is connected to the V2 voltage terminal, a drain of the N-type MOS transistor MN7 is connected to the source of the N-type MOS transistor MN9, a gate of the N-type MOS transistor MN2 is connected to the VB voltage terminal, a drain of the N-type MOS transistor MN 5475, a drain of the P-type MOS transistor MN4 is connected to the P-type MOS transistor MN4, a drain of the P-type MOS transistor MN4 and a drain of the P-type MOS transistor MN4, and a drain of the P-type MOS transistor MN4 and a drain of the MOS transistor MN4 and an output terminal of the P-type MOS transistor MN4, The drain electrode of the P-type MOS tube MP6, the drain electrode of the N-type MOS tube MN10, the grid electrode of the P-type MOS tube MP6 is respectively connected with the grid electrode of the P-type MOS tube MP8, the drain electrode of the P-type MOS tube MP8 and the drain electrode of the N-type MOS tube MN13, the grid electrode of the N-type MOS tube MN13 is respectively connected with the grid electrode of the N-type MOS tube MN12, the drain electrode of the N-type MOS tube MN12, the drain electrode of the P-type MOS tube MP12, the gate electrode of the P-type MOS tube MP12 is connected with the VC voltage end, the source electrode of the P-type MOS tube MP12 is connected with the drain electrode of the P-type MOS tube MP10, the gate electrode of the P-type MOS tube MP10 is connected with the V1 voltage end, the source electrode of the P-type MOS tube MP10 is respectively connected with the drain electrode of the P-type MOS tube MP7 and the source electrode of the P-type MOS tube MP9, the gate electrode of the P-type MOS tube MP9 is connected with the V2 voltage end, the drain electrode of the P-type MOS tube MP9 is connected with the source electrode of the P-type MOS tube MP11, the gate electrode of the P-type MOS tube 11 is connected with the VC voltage end, and the drain electrode of the P-type MOS tube MP11 is respectively connected with the gate electrode of the N-type MOS tube MN10, the gate electrode of the N-type MOS tube MN11 and the drain electrode of the N-type MOS tube MN 11.
2. A rail-to-rail transconductance operational amplifier circuit according to claim 1, wherein: the VB voltage end, the VC voltage end and the VBIAS voltage end are three bias voltages, and a bias circuit is formed by an N-type MOS tube MN1, an N-type MOS tube MN2 and a P-type MOS tube MP 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202123035071.XU CN216437159U (en) | 2021-12-06 | 2021-12-06 | Rail-to-rail transconductance operational amplifier circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123035071.XU CN216437159U (en) | 2021-12-06 | 2021-12-06 | Rail-to-rail transconductance operational amplifier circuit |
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| CN216437159U true CN216437159U (en) | 2022-05-03 |
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| CN202123035071.XU Active CN216437159U (en) | 2021-12-06 | 2021-12-06 | Rail-to-rail transconductance operational amplifier circuit |
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