CN216435444U - Drive chip, drive chip assembly and display device - Google Patents
Drive chip, drive chip assembly and display device Download PDFInfo
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- CN216435444U CN216435444U CN202122530247.2U CN202122530247U CN216435444U CN 216435444 U CN216435444 U CN 216435444U CN 202122530247 U CN202122530247 U CN 202122530247U CN 216435444 U CN216435444 U CN 216435444U
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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Abstract
The application discloses driver chip, driver chip subassembly and display device, driver chip include first base plate and set up in the voltage input pin and the voltage output pin of first base plate, and the voltage input pin is connected through first wire electricity with the voltage output pin, and the voltage of voltage input pin equals the voltage of voltage output pin. When the driving chips are used in a cascade mode, the voltage output pin of one driving chip is electrically connected with the voltage input pin of another adjacent driving chip, and after one driving chip is connected with a power supply, electric energy can be transmitted to the voltage input pin of another driving chip through the first wire, so that the input voltages of the two adjacent driving chips are equal. The driving chip provided by the embodiment of the application is provided with the voltage input pin, the voltage output pin and the first wire, the pins are utilized to carry out electric connection, normal power supply of the chip can be guaranteed, a chip power supply line does not need to be arranged at the edge of a PCB, and the problems of line crossing and the like in PCB typesetting can be reduced.
Description
Technical Field
The application belongs to the display field, and particularly relates to a driving chip and a display device.
Background
The LED display screen (Light Emitting Diode) is popular with consumers, and the LED display screen directly uses array LED devices (such as LED chips and LED lamp beads) as display pixels, and has the advantages of high brightness and long service life. The LED display screen is generally internally provided with a driving chip for driving an LED device to emit light, under the condition that the driving capability of a single chip is limited, the LED display screen is usually driven by partitions to improve the resolution, the display area of the display screen is divided into a plurality of driving partitions by partition driving, and each driving partition is driven by one or a plurality of driving chips.
A plurality of driver chips need to be used in a cascade connection manner, in the related art, each driver chip is usually supplied with power independently, a chip power supply line is usually arranged at the edge of a PCB, and each driver chip is connected with the chip power supply line, which causes the problems of line crossing and the like in PCB typesetting, and can cause the reliability reduction and the manufacturing cost increase of the PCB.
SUMMERY OF THE UTILITY MODEL
The embodiment of the application provides a driving chip, a driving chip assembly and a display device, which can reduce the problems of crossed wires and the like.
In a first aspect, an embodiment of the present application provides a driving chip, including:
a first substrate;
the voltage input pin is arranged on the first substrate;
the voltage output pin is arranged on the first substrate;
the voltage input pin is electrically connected with the voltage output pin through a first wire, and the voltage of the voltage input pin is equal to that of the voltage output pin.
Optionally, the driving chip further includes a load, the load is disposed on the first substrate, a voltage output point is disposed on the first wire, and the voltage output point is configured to output a voltage to the load.
Optionally, the first conductive line is disposed on a surface of the first substrate; alternatively, the first conductive line is disposed inside the first substrate.
Optionally, the driving chip further includes:
the first grounding pin is used for grounding;
and the first grounding pin is connected with the second grounding pin through a second wire, and the first wire and the second wire are insulated from each other.
Optionally, the second wire is provided with a ground point, and when the driving chip includes the load, the ground point is connected to the load.
Optionally, the driving chip further includes:
a data input pin for receiving a first control signal;
the data output pin is used for outputting a second control signal, the load comprises a data registering unit, and the data input pin is electrically connected with the data output pin through the data registering unit;
the first control signal comprises an address of the driving chip, the driving chip obtains a corresponding current-stage control signal through addressing, and the first control signal is processed by the data registering unit and then output as the second control signal.
Optionally, the driving chip further includes a constant current output pin, the first substrate further includes a first end portion and a second end portion that are disposed opposite to each other, the first conducting wire and the second conducting wire are both disposed between the first end portion and the second end portion, and the constant current output pin is disposed on the first end portion and/or the second end portion.
Optionally, the load further includes a constant current control unit and a voltage detection unit, the data register unit is electrically connected to the constant current control unit through the voltage detection unit, the constant current output pin is electrically connected to the constant current control unit, the constant current control unit controls the current at the constant current output pin to be in a first preset range according to the current-level control signal, the voltage detection unit is configured to detect a voltage value at the constant current output pin, and the voltage value is used to generate a feedback signal to control the voltage of the light emitting element to be in a second preset range.
In a second aspect, an embodiment of the present application provides a driving chip assembly, which includes the driving chips as described above, the driving chips are adjacently disposed along a first direction, and a voltage output pin of one driving chip is disposed opposite to a voltage input pin of another adjacent driving chip and electrically connected through a fourth wire.
Optionally, when the driving chips include a first ground pin and a second ground pin, a voltage output pin of one driving chip is electrically connected to a voltage input pin of another adjacent driving chip through a fifth wire, and the fourth wire and the fifth wire are arranged at an interval.
Optionally, when the driving chips include a data input pin and a data output pin, the data output pin of one driving chip is electrically connected to the data input pin of another adjacent driving chip through a sixth wire, the sixth wire and the fifth wire are arranged at an interval, and the sixth wire and the fourth wire are arranged at an interval.
Optionally, the driving chip assembly further includes a light emitting element, when the driving chip includes a constant current output pin, a first end portion and a second end portion, the light emitting element is electrically connected to the constant current output pin, and the first end portion of one driving chip is disposed opposite to the first end portion of another adjacent driving chip;
the light emitting element junction connected to the first end of each driving chip is connected with the same light emitting element power supply line, and/or the light emitting element junction connected to the second end of each driving chip is connected with the same light emitting element power supply line.
In a third aspect, an embodiment of the present application provides a display device, further including a plurality of driving chip assemblies as described above, the driving chip assemblies being disposed adjacent to each other along the second direction, and a light emitting element electrically connected to the first end portion in one of the driving chip assemblies and a light emitting element electrically connected to the second end portion in another of the adjacent driving chip assemblies being connected to a same light emitting element power supply line in a junction manner.
In the embodiment of the application, the driving chip comprises a first substrate, and a voltage input pin and a voltage output pin which are arranged on the first substrate, wherein the voltage input pin and the voltage output pin are electrically connected through a first wire, and the voltage of the voltage input pin is equal to the voltage of the voltage output pin. When the driving chips are used in a cascade mode, the voltage output pin of one driving chip is electrically connected with the voltage input pin of another adjacent driving chip, and after one driving chip is connected with a power supply, electric energy can be transmitted to the voltage input pin of another driving chip through the first wire, so that the input voltages of the two adjacent driving chips are equal. The driving chip provided by the embodiment of the application is provided with the voltage input pin, the voltage output pin and the first wire, the pins are utilized to carry out electric connection, normal power supply of the chip can be guaranteed, a chip power supply line does not need to be arranged at the edge of a PCB, and the problems of line crossing and the like in PCB typesetting can be reduced.
Drawings
The technical solutions and advantages of the present application will become apparent from the following detailed description of specific embodiments of the present application when taken in conjunction with the accompanying drawings.
Fig. 1 is a schematic view of a first structure of a display device according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of a display device in the prior art.
Fig. 3 is a schematic structural diagram of a first driving chip according to an embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of a driving chip in cascade use.
Fig. 5 is a schematic structural diagram of a second driving chip according to an embodiment of the present disclosure.
Fig. 6 is a schematic structural diagram of a third driving chip provided in the embodiment of the present application.
Fig. 7 is a schematic structural diagram of a fourth driving chip provided in the embodiment of the present application.
Fig. 8 is a schematic structural diagram of a load in the embodiment of the present application.
Fig. 9 is another schematic structural diagram of a display device in the embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the related art, a driving chip is built in the LED display screen to drive the LED devices to emit light, but the number of the LED devices that can be driven by the LED driving chip is limited. In order to realize large-scale application or improve resolution, the LED display screen is often driven by partitions. The partition driving technology divides a display area of a display screen into a plurality of sub-areas, each sub-area is driven by one or a plurality of driving chips, then the driving chips are connected, and then the driving chips are controlled. The cascade connection of the driving chips can control more LED devices to emit light, so that large-screen display or high-resolution display is realized.
Referring to fig. 1, fig. 1 is a first structural schematic diagram of a display device according to an embodiment of the present disclosure. The display device 100 includes a second substrate 1 and a driving chip assembly 2, the second substrate 1 includes a third surface 13 and a fourth surface 15 disposed opposite to each other, and the driving chip assembly 2 includes a light emitting element 22 and a driving chip 21. In order to realize the divisional driving, the divisional driving LED display generally needs to use a double-sided printed circuit board as a substrate, and the light emitting element 22 and the driving chip 21 are respectively soldered on two sides of the printed circuit board and are electrically connected through a conductive hole on the printed circuit board. Therefore, the third surface 13 can be used as a display surface, and the light emitting element 22 is disposed on the third surface 13. The driving chips 21 are disposed on the fourth surface 15, each driving chip 21 is electrically connected to the plurality of light emitting elements 22, and each driving chip 21 controls a certain display area. The driving chips 21 in the driving chip assembly 2 are adjacently arranged in the first direction X, and the display device 100 generally includes a plurality of driving chip assemblies 2, the plurality of driving chip assemblies 2 are adjacently arranged in the second direction Y to form an array of driving chips 21 on the second substrate 1, and the driving chips 21 are electrically connected.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a display device in the prior art. In the related art, during the divisional driving, the LED driving chips 31 are arranged in an array on the PCB 3 (which is equivalent to the second substrate 1 in the present application), and the LED driving chips 31 are electrically connected to realize the centralized control of the array of the LED driving chips 31. The LED driving chip 31 is usually provided with only one power pin 32, and each LED driving chip 31 needs to be individually powered. A chip supply line 33 is generally provided at the edge of the PCB board 3, and the power supply pin 32 of each LED driving chip 31 is electrically connected to the chip supply line 33. It can be understood that when the number of the LED driving chips 31 is large, the power supply method may cause problems such as line crossing in the PCB layout, which may result in reduced reliability and increased manufacturing cost of the PCB 3.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a first driving chip according to an embodiment of the present disclosure. The embodiment of the application provides a driving chip 21, and the driving chip 21 includes a first substrate 213, a voltage input pin Vi, and a voltage output pin Vo. The voltage input pin Vi is disposed on the first substrate 213, and the voltage output pin Vo is disposed on the first substrate 213. The voltage input pin Vi is electrically connected to the voltage output pin Vo through a first wire L1, and the voltage of the voltage input pin Vi is equal to the voltage of the voltage output pin Vo. When the driving chips 21 are used in cascade, the voltage output pin Vo of one driving chip 21 is electrically connected to the voltage input pin Vi of another driving chip 21 adjacent thereto, so that the input voltages of two adjacent driving chips 21 are equal.
The driving chip 21 provided by the embodiment of the application is provided with a voltage input pin Vi, a voltage output pin Vo and a first wire L1, and when the driving chips 21 are used in a cascade connection mode, the voltage output pin Vo of one driving chip 21 is electrically connected with the voltage input pin Vi of another driving chip 21 adjacent to the voltage output pin Vo. After one driver chip 21 is powered on, the power can be transmitted to the voltage input pin Vi of another driver chip 21 through the first wire L1, so that the input voltages of two adjacent driver chips 21 are equal. The driving chip 21 that this application embodiment provided is provided with voltage input pin Vi, voltage output pin Vo and first wire L1, utilizes the pin to carry out the electricity and connects and can guarantee that each driving chip 21 normally supplies power, need not set up the chip power supply line at the edge of PCB board, can reduce the line cross scheduling problem in the PCB typesetting.
The first substrate 213 includes a first surface 2131 and a second surface 2132, the driving chip 21 further includes a load 217, the load 217 is disposed on the first surface 2131 of the first substrate 213, and the second surface 2132 of the first substrate 213 is used for connecting with the fourth surface 15 of the second substrate 1. It will be appreciated that the load 217 needs to be powered on to perform various control functions. For example, a voltage output point P may be provided on the first conductor L1, the voltage output point P being configured to output a voltage to the load 217. Of course, the load 217 may be directly electrically connected to the voltage input pin Vi.
It can be understood that the voltage input pin Vi and the voltage output pin Vo are directly connected through the first wire L1, please refer to fig. 4, and fig. 4 is a schematic structural diagram when the driving chips are used in cascade. The following explanation will take two adjacent driving chips 21 (e.g., the first chip 21a and the second chip 21b) as an example. When the driving chips 21 are cascade-connected, the voltage output pin Vo of the first chip 21a is electrically connected to the voltage input pin Vi of the second chip 21 b. After the voltage input pin Vi of the first chip 21a is connected to the power supply, the power can be transmitted to another adjacent driving chip 21 through the first wire L1 and the voltage output pin Vo, and the voltage input pin Vi of the second chip 21b is connected to the first driving chip 21, but the voltage input pin Vi of the second chip 21b is actually connected to the power supply. This kind of setting makes two adjacent driver chips 21 "concatenate" together in structure, and in electricity, two adjacent driver chips 21 are parallelly connected, can realize driver chip 21 array and concentrate the power supply when, avoided setting up extra power supply line at the edge of second base plate 1.
It should be noted that, the display screen technology is gradually developing towards more individuation and humanization, although the driving chips 21 connected in series are convenient to perform "centralized power supply", there are also special areas in the display screen that need to be controlled individually. For example, a news scroll bar may be required at the edge of the display screen, or the time may be displayed at the corner of the display screen. These special areas are different from the main display area, and need to be controlled individually, and accordingly, the chip controlling the special areas can be powered and controlled individually. A power supply pin 32 can be additionally provided on the driving chip 21 for controlling a specific area for separate power supply. For the convenience of wiring, the voltage input pin Vi and the voltage output pin Vo of the driving chip 21 controlling the special area may still be electrically connected to the driving chips 21 of the upper and lower stages.
It is understood that the position of the first conductive line L1 can affect the usage, manufacturing, and routing of the driving chip 21. For convenience of manufacturing, the first conductive line L1 may be disposed on the first surface 2131 of the first substrate 213. Of course, the first wire L1 may also be disposed inside the first substrate 213, for example, please refer to fig. 5, and fig. 5 is a schematic structural diagram of a second driving chip according to an embodiment of the present disclosure. The first substrate 213 may be internally perforated and then copper may be injected into the hole, thereby implementing internal routing of the substrate. This arrangement does not occupy the surface area of the first substrate 213, and can make the structure of the driver chip 21 compact and reduce the area of the driver chip 21.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a third driving chip according to an embodiment of the present disclosure. The driving chip 21 further includes a first ground pin G1 and a second ground pin G2 for grounding, the first ground pin G1 is connected to the second ground pin G2 through a second wire L2, and the load 217 may be electrically connected to the first ground pin G1 or the second ground pin G2 to achieve grounding. Of course, the second conducting line L2 may also be provided with a grounding point H, the grounding point H is connected to the load 217, and the specific connection mode of the load 217 to ground is not limited herein. It will be appreciated that in order to ensure that the voltages at the voltage input pin Vi and the voltage output pin Vo are equal, the resistance of the first conductor L1 between the voltage input pin Vi and the voltage output pin Vo needs to be as low as possible. When grounding the load 217, the voltage at the grounding pin is not required to be equal, and depending on the actual condition of the load 217 on the driver chip 21, an element such as a resistor may be connected in series between the load 217 and the grounding point H as appropriate. Similar to the first wire L1, the first ground pin G1, the second ground pin G2 and the second wire L2 can also achieve "serial connection" of the driving chip 21, which serves to simplify the routing. In order to avoid the influence of the second conducting wire L2 on the power supply of the first conducting wire L1, the first conducting wire L1 needs to be insulated from the second conducting wire L2. For example, the first conductive line L1 may be spaced apart from the second conductive line L2. The first conductive line L1 may be disposed inside the first substrate 213, and the second conductive line L2 may be disposed on the first surface 2131 of the first substrate 213.
It should be noted that a grounding point may also be disposed on the second substrate 1, and the grounding pin (e.g., the first grounding pin G1 and the second grounding pin G2) on each driving chip 21 may be directly electrically connected to the second substrate 1 through the grounding point, for example, the grounding pin may be soldered to the grounding point on the second substrate 1. Each driving chip 21 corresponds to a grounding point on the second substrate 1, and this grounding manner can reduce the wiring connection between the driving chips 21 and reduce the bad phenomena such as short circuit.
The driving chip 21 may further include a data input pin Di and a data output pin Do. The data input pin Di is used for receiving a first control signal, and the data output pin Do is used for outputting a second control signal. The load 217 includes a data register unit 2171, and the data input pin Di is electrically connected to the data output pin Do through the data register unit 2171.
It should be noted that the driver chip 21 in the embodiment of the present application may obtain the current-stage control signal corresponding to the driver chip 21 by using an addressing technique. Illustratively, the load 217 may further include an address memory, and the address of each driver chip 21 is fetched and stored in the address memory when the driver chip 21 is powered on. When the driver chip is used, the data input pin Di receives the first control signal and then transmits the first control signal to the data register unit 2171, and each driver chip 21 obtains the current-level control signal in the first control signal according with its own address through the address, so as to light the light emitting element 22 controlled by the driver chip. After acquiring the current-stage control signal, the data register unit 2171 processes the first control signal into a second control signal, and outputs the second control signal through the data output pin Do.
Of course, the driving chip 21 may also obtain the current-level control signal in other manners, for example, after the first chip 21a receives the first control signal, the first chip decodes the first control signal, and lights the light emitting element 22 with the decoded signal. Meanwhile, the first chip 21a re-encodes the decoded signal and transmits it to the second chip 21b, and the second chip 21b repeats the decoding and encoding processes of the first chip 21 a. With this cascade connection, the control signal can be transmitted to all the driver chips 21 in sequence. Each driver chip 21 repeats the same processing procedure to realize the cascade lighting of the light emitting elements 22.
In order to realize the centralized control of a plurality of driving chips 21 connected in series, when the driving chips 21 are used in cascade, the data input pin Di of one driving chip 21 may be electrically connected to the data output pin Do of the driving chip 21 at the previous stage, and the data output pin Do may be electrically connected to the data input pin Di of the driving chip 21 at the next stage. It is understood that, for the driver chip of the present stage, the first control signal is output by the driver chip of the upper stage, and the second control signal output by the driver chip of the present stage is transmitted to the driver chip of the lower stage. Structurally, the data input pins Di and the data output pins Do can enable the driving chips 21 to be connected in series, so that the effect of simplifying wiring is achieved, and the problems of wiring intersection and the like are avoided as much as possible.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a fourth driving chip according to an embodiment of the present disclosure. The first substrate 213 further includes a first end portion 2133 and a second end portion 2134 disposed oppositely, and each of the first lead wire L1 and the second lead wire L2 is disposed between the first end portion 2133 and the second end portion 2134. The first and second conductive lines L1 and L2 are disposed at the middle portion of the driving chip 21.
It should be noted that the driving chip 21 may include a first edge 2135 and a second edge 2136 which are oppositely disposed, the first voltage input pin Vi, the first ground pin G1 and the data input pin Di are disposed on the first edge 2135, and the voltage output pin Vo, the second ground pin G2 and the data output pin Do are disposed on the second edge 2136. When the driving chips 21 are cascaded, the edge of each driving chip is provided with the pins, so that wiring between two adjacent driving chips 21 can be shortened, the two driving chips 21 can be conveniently connected, the material of a connecting wire is reduced, and the raw material cost is saved.
The first end portion 2133 and/or the second end portion 2134 is provided with the constant current output pin 215, and the constant current output pin 215 is electrically connected to the light emitting element 22. It can be understood that the constant current output pin 215 is disposed at two ends of the driving chip 21, and the first conductive line L1 and the second conductive line L2 are disposed at a middle portion of the driving chip 21, such arrangement can make the routing on the second substrate 1 simple and orderly, and reduce the problems of crossing and jumping of the routing on the second substrate 1 as much as possible.
In each driving chip 21, the number of the constant current output pins 215 is plural, for example, four constant current output pins 215 are arranged on each driving chip 21, two of the constant current output pins 215 are arranged at the first end portion 2133, the other two constant current output pins 215 are arranged at the second end portion 2134, and the four constant current output pins 215 may be symmetrically arranged.
Referring to fig. 8, fig. 8 is a schematic structural diagram of a load according to an embodiment of the present application. The load 217 further includes a constant current control unit 2173 and a voltage detection unit 2172, the data register unit 2171 is electrically connected with the constant current control unit 2173 through the voltage detection unit 2172, the constant current output pin 215 is electrically connected with the constant current control unit 2173, and the constant current control unit 2173 controls the current at the constant current output pin 215 to be in a first preset range according to the current-stage control signal. The voltage detection unit 2172 is configured to detect a voltage value at the constant current output pin 215, compare the voltage value detected by the voltage detection unit 2172 with a set value, perform error amplification, and then use the voltage value as a feedback signal of the power supply to control the voltage value of the light emitting element 22, so as to ensure that the voltage of the light emitting element 22 is within a second preset range, and the power supply supplies power to the light emitting element 22 through the light emitting element power supply line L7. It is understood that the luminance of the light emitting element 22 can be controlled by controlling the voltage and current of the light emitting element 22.
It should be noted that the load 217 may further include a counting unit 2174 and a clock oscillation unit 2175, the radix unit is electrically connected to the voltage detection unit 2172, one end of the clock oscillation unit 2175 is electrically connected to the technical unit, and the other end of the clock oscillation unit 2175 is electrically connected to the data register, thereby implementing control of timing in the circuit. Other functional units, such as a compensation unit, a correction unit, etc., may be provided between the data register unit 2171 and the constant current control unit 2173 to make the control of the display screen more precise.
Referring to fig. 9, fig. 9 is a schematic structural diagram of a display device in an embodiment of the present application. In the driving chip assembly 2, the plurality of driving chips 21 are adjacently disposed along the first direction X, and one of the voltage output pins Vo of the driving chips 21 is opposite to another of the voltage output pins Vi of the driving chips 21 and electrically connected to each other through the fourth wire L4. The voltage output pin Vo of one of the driving chips 21 is electrically connected to the voltage input pin Vi of another adjacent driving chip 21 through a fifth conductive line L5, and the fourth conductive line L4 is spaced apart from the fifth conductive line L5. The data output pin Do of one of the driver chips 21 is electrically connected to the data input pin Di of another adjacent driver chip 21 through a sixth wire L6.
The second edge 2136 of one driver chip 21 may be opposite to the first edge 2135 of the next driver chip 21, so as to avoid the crossing among the fourth conducting wire L4, the fifth conducting wire L5 and the sixth conducting wire L6 as much as possible. That is, the sixth wire L6 is spaced apart from the fifth wire L5, and the sixth wire L6 is spaced apart from the fourth wire L4.
In the driving chip assembly 2, the first end portion 2133 of one driving chip 21 is disposed to face the first end portion 2133 of another adjacent driving chip 21, and the second end portion 2134 of one driving chip 21 is disposed to face the second end portion 2134 of another adjacent driving chip 21. The first end portion 2133 and the second end portion 2134 are provided with a constant current output pin 215, and the constant current output pin 215 is electrically connected to the light emitting element 22. The light emitting elements 22 connected to the first end portions 2133 of the driving chips 21 are connected to the same light emitting element power supply line L7, and/or the light emitting elements 22 connected to the second end portions 2134 of the driving chips 21 are connected to the same light emitting element power supply line L7. In the display device 100, the driving chip assemblies 2 are disposed adjacent to each other in the second direction Y, and the light emitting element 22 electrically connected to the first end portion 2133 of one of the driving chip assemblies 2 and the light emitting element 22 electrically connected to the second end portion 2134 of the other adjacent driving chip assembly 2 are connected to the same light emitting element supply line L7. It can be understood that such a junction of the light emitting elements 22 is beneficial to reduce the crossing of traces on the second substrate 1.
The driving chip, the driving chip assembly and the display device provided in the embodiments of the present application are described in detail above, and specific examples are applied herein to explain the principles and embodiments of the present application, and the description of the embodiments above is only used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (13)
1. A driver chip, comprising:
a first substrate;
the voltage input pin is arranged on the first substrate;
the voltage output pin is arranged on the first substrate;
the voltage input pin is electrically connected with the voltage output pin through a first wire, and the voltage of the voltage input pin is equal to that of the voltage output pin.
2. The driver chip of claim 1, further comprising a load disposed on the first substrate, wherein a voltage output point is disposed on the first conductive line, and wherein the voltage output point is configured to output a voltage to the load.
3. The driving chip according to claim 1 or 2, wherein the first conductive line is disposed on a surface of the first substrate; alternatively, the first conductive line is disposed inside the first substrate.
4. The driver chip of claim 2, further comprising:
the first grounding pin is used for grounding;
and the first grounding pin is connected with the second grounding pin through a second wire, and the first wire and the second wire are insulated from each other.
5. The driver chip according to claim 4, wherein the second conductive line has a ground point disposed thereon, and when the driver chip includes the load, the ground point is connected to the load.
6. The driver chip of claim 4, further comprising:
a data input pin for receiving a first control signal;
the data output pin is used for outputting a second control signal, the load comprises a data registering unit, and the data input pin is electrically connected with the data output pin through the data registering unit;
the first control signal comprises an address of the driving chip, the driving chip obtains a corresponding current-stage control signal through addressing, and the first control signal is processed by the data registering unit and then output as the second control signal.
7. The driving chip according to claim 6, further comprising a constant current output pin, wherein the first substrate further comprises a first end portion and a second end portion which are oppositely arranged, the first conducting wire and the second conducting wire are arranged between the first end portion and the second end portion, and the constant current output pin is arranged on the first end portion and/or the second end portion.
8. The driver chip according to claim 7, wherein the load further includes a constant current control unit and a voltage detection unit, the data register unit is electrically connected to the constant current control unit through the voltage detection unit, the constant current output pin is electrically connected to the constant current control unit, the constant current control unit controls a current at the constant current output pin to be in a first preset range according to the current-level control signal, the voltage detection unit is configured to detect a voltage value at the constant current output pin, and the voltage value is configured to generate a feedback signal to control a voltage of the light emitting element to be in a second preset range.
9. A driver chip assembly comprising a plurality of driver chips according to any one of claims 1 to 8, wherein the plurality of driver chips are adjacently disposed in a first direction, and a voltage output pin of one of the driver chips is disposed opposite to a voltage input pin of another of the adjacent driver chips and is electrically connected thereto through a fourth wire.
10. The driver chip assembly as claimed in claim 9, wherein when the driver chip includes a first ground pin and a second ground pin, the voltage output pin of one of the driver chips is electrically connected to the voltage input pin of another adjacent driver chip through a fifth conductive wire, and the fourth conductive wire is spaced apart from the fifth conductive wire.
11. The driving chip assembly according to claim 10, wherein when the driving chips include data input pins and data output pins, the data output pin of one driving chip is electrically connected to the data input pin of another adjacent driving chip through a sixth conductive line, the sixth conductive line is spaced apart from the fifth conductive line, and the sixth conductive line is spaced apart from the fourth conductive line.
12. The driving chip assembly according to claim 11, further comprising a light emitting element electrically connected to the constant current output pin when the driving chips include a constant current output pin, a first end portion and a second end portion, the first end portion of one of the driving chips being disposed opposite to a first end portion of another adjacent one of the driving chips;
the light emitting element junction connected to the first end of each driving chip is connected with the same light emitting element power supply line, and/or the light emitting element junction connected to the second end of each driving chip is connected with the same light emitting element power supply line.
13. A display device, further comprising a plurality of driving chip assemblies according to claim 12, wherein the driving chip assemblies are disposed adjacent to each other in the second direction, and a light emitting element electrically connected to the first end portion of one of the driving chip assemblies and a light emitting element electrically connected to the second end portion of another adjacent driving chip assembly are connected to a same light emitting element power supply line.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122530247.2U CN216435444U (en) | 2021-10-20 | 2021-10-20 | Drive chip, drive chip assembly and display device |
| PCT/CN2022/107154 WO2023065745A1 (en) | 2021-10-20 | 2022-07-21 | Drive chip, drive chip assembly, and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122530247.2U CN216435444U (en) | 2021-10-20 | 2021-10-20 | Drive chip, drive chip assembly and display device |
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| CN216435444U true CN216435444U (en) | 2022-05-03 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202122530247.2U Active CN216435444U (en) | 2021-10-20 | 2021-10-20 | Drive chip, drive chip assembly and display device |
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| Country | Link |
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| CN (1) | CN216435444U (en) |
| WO (1) | WO2023065745A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023065745A1 (en) * | 2021-10-20 | 2023-04-27 | 惠州视维新技术有限公司 | Drive chip, drive chip assembly, and display device |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202258258U (en) * | 2011-07-25 | 2012-05-30 | 深圳市华星光电技术有限公司 | Led backlight drive circuit |
| JP5807550B2 (en) * | 2012-01-10 | 2015-11-10 | 株式会社ソシオネクスト | Semiconductor device |
| CN103857106B (en) * | 2012-11-29 | 2016-05-18 | 利亚德光电股份有限公司 | Led drive circuit and control system |
| CN104299593B (en) * | 2014-11-07 | 2017-01-25 | 深圳市华星光电技术有限公司 | Liquid crystal display device |
| CN205211380U (en) * | 2015-12-24 | 2016-05-04 | 大连集思特科技有限公司 | LED drive arrangement and LED display system |
| CN108133685B (en) * | 2018-01-03 | 2021-03-26 | 京东方科技集团股份有限公司 | Amplitude control unit, voltage supply module, display device and amplitude control method |
| CN109360526B (en) * | 2018-11-16 | 2023-11-28 | 上海得倍电子技术有限公司 | LED high efficiency constant current control device |
| CN211457461U (en) * | 2020-01-19 | 2020-09-08 | 酷矽半导体科技(上海)有限公司 | Light emitting diode driving chip |
| CN216435444U (en) * | 2021-10-20 | 2022-05-03 | 惠州视维新技术有限公司 | Drive chip, drive chip assembly and display device |
-
2021
- 2021-10-20 CN CN202122530247.2U patent/CN216435444U/en active Active
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2022
- 2022-07-21 WO PCT/CN2022/107154 patent/WO2023065745A1/en unknown
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023065745A1 (en) * | 2021-10-20 | 2023-04-27 | 惠州视维新技术有限公司 | Drive chip, drive chip assembly, and display device |
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| WO2023065745A1 (en) | 2023-04-27 |
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