CN116189583A

CN116189583A - Backlight module and display device

Info

Publication number: CN116189583A
Application number: CN202111424817.8A
Authority: CN
Inventors: 杜强; 张玉欣
Original assignee: Hisense Visual Technology Co Ltd
Current assignee: Hisense Visual Technology Co Ltd
Priority date: 2021-11-26
Filing date: 2021-11-26
Publication date: 2023-05-30

Abstract

The application provides a backlight module and display equipment, wherein, include the circuit board in the backlight module, set up the drive chip on the circuit board to and a plurality of lamp areas that correspond with the drive chip. The driving chip is provided with a first pin, a third pin and a second pin and a fourth pin which are positioned on the first side of the driving chip and the second side of the driving chip; the first pin and the second pin are electrically communicated in the driving chip, and the third pin and the fourth pin are electrically communicated in the driving chip; the first side is arranged opposite to the second side; the driving chip is also provided with a plurality of control ends positioned at the third side of the driving chip; the plurality of control ends are correspondingly connected with the plurality of lamp areas. Based on the design of the driving chips, when a plurality of driving chips are cascaded, wires for bypassing lamp areas connected with the driving chips are not needed, and further, when the backlight module integrated with the lamp driver is arranged on a single panel, the wiring complexity of the plurality of driving chips is reduced.

Description

Backlight module and display device

Technical Field

The application relates to the technical field of electronics, in particular to a backlight module and display equipment.

Background

A display device generally includes a lamp panel provided with a plurality of lamp regions and a driving panel for driving the lamp regions to emit light. In the display device, in order to reduce the driving boards in the display device and the lamp boards carrying a plurality of lamp areas, the lamp boards can be arranged on the same single-sided circuit board, so that the lamp driving is integrated.

At present, one driving chip can drive 32 partitioned lamp areas, however, with the increasing number of lamp areas, when more lamp areas need to be driven, more driving chip cascades need to be considered. However, in the cascade connection process of the driving chips, the signal lines of the driving chips at all levels need to be connected together, and the connection lines between the driving chips and the lamp areas are very many, so that the driving chips often need to cross a plurality of lamp areas when connected, which results in complex wiring of a circuit board carrying the driving chips and relatively complex manufacturing.

Disclosure of Invention

The application provides a backlight module and display equipment for solve among the prior art realize lamp and drive the complicated problem of walking of integrative design on single panel.

In a first aspect, the present application provides a circuit board, a driving chip disposed on the circuit board, and a plurality of light areas corresponding to the driving chip;

The driving chip is provided with a first pin and a third pin which are positioned on the first side of the driving chip, and a second pin and a fourth pin which are positioned on the second side of the driving chip; wherein the first pin is electrically communicated with the second pin in the driving chip, and the third pin is electrically communicated with the fourth pin in the driving chip; the first side is arranged opposite to the second side;

the driving chip is further provided with a plurality of control ends positioned on the third side of the driving chip; the plurality of control ends are correspondingly connected with the plurality of lamp areas.

In some embodiments, the circuit board is provided with a plurality of driving chips arranged in an array;

the first pins and the second pins among the plurality of driving chips positioned in the same row are sequentially connected, and the third pins and the fourth pins are sequentially connected;

when the driving chips positioned at the tail of different rows are connected, the second pins among the driving chips are connected with the second pins, and the fourth pins among the driving chips are connected with the fourth pins; the second pins among the driving chips are connected with the second pins by using cross wires, or the fourth pins among the driving chips are connected with the fourth pins by using cross wires;

When the first driving chips positioned in different rows are connected, a first pin among the driving chips is connected with the first pin, and a third pin among the driving chips is connected with the third pin; and the first pins among the driving chips are connected by using cross wires, or the third pins among the driving chips are connected by using cross wires.

In some embodiments, the driving chip is further provided with a fifth pin and a sixth pin; the first pin, the third pin and the fifth pin are sequentially arranged on the first side of the driving chip, and the second pin, the fourth pin and the sixth pin are sequentially arranged on the second side of the driving chip; the first pin, the second pin, the fifth pin and the sixth pin are electrically communicated inside the driving chip.

when the driving chips positioned in the same row are connected, a third pin and a fourth pin among the driving chips are sequentially connected; the first pin and the second pin between the driving chips are sequentially connected, or the fifth pin and the sixth pin are sequentially connected;

When the driving chips positioned at the tail of different rows are connected, a fourth pin among the driving chips is connected with the fourth pin, and a second pin among the driving chips is connected with the sixth pin;

when the first driving chips in different rows are connected, the third pins among the driving chips are connected with the third pins, and the first pins among the driving chips are connected with the fifth pins.

In some embodiments, the first pin, the second pin, the fifth pin and the sixth pin are used for transmitting a control signal of a lamp area in the backlight module; the third pin and the fourth pin are used for transmitting clock signals of the lamp area in the backlight module;

or the first pin, the second pin, the fifth pin and the sixth pin are used for transmitting clock signals of the lamp area in the backlight module, and the third pin and the fourth pin are used for transmitting control signals of the lamp area in the backlight module.

In some embodiments, the plurality of control terminals includes a common terminal and a plurality of output terminals;

one end of the plurality of lamp areas corresponding to the driving chip is connected to the common end of the driving chip, and the other end of the plurality of lamp areas corresponding to the driving chip is respectively connected to the plurality of output ends of the driving chip.

In some embodiments, the driving chip is further provided with a plurality of control terminals located at a fourth side of the driving chip; the control ends are correspondingly connected with the lamp area.

In some embodiments, the plurality of control terminals of the driving chip on the third side of the driving chip include a first common terminal, a first output terminal, and a second output terminal; the driving chip is positioned at a plurality of control ends of the fourth side of the driving chip and comprises a second common end, a third output end and a fourth output end;

the driving chip is correspondingly provided with a first lamp area, a second lamp area, a third lamp area and a fourth lamp area; one end of the first lamp area and one end of the second lamp area are respectively connected to the first common end; the other end of the first lamp area is connected to the first output end; the other end of the second lamp area is connected to the second output end; one end of the third lamp area and one end of the fourth lamp area are respectively connected to a second common end; the other end of the third lamp area is connected to the third output end; the other end of the second light area is connected to the fourth output end.

In some embodiments, the first common terminal is located between the first output terminal and the second output terminal; the second common terminal is located between the third output terminal and the fourth output terminal.

In some embodiments, one end of the light section is a positive common terminal of the light section, or one end of the light section is a negative common terminal of the light section.

In a second aspect, the present application provides a display device, comprising: the backlight module, the main board and the power supply according to any one of the first aspect; the power supply is connected with the backlight module and the main board and is used for providing power supply signals; the main board is connected with the backlight module and is used for sending control signals and clock signals to the backlight module so that the backlight module emits light based on the clock signals and the control signals.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

Fig. 1 is a schematic structural diagram of a display device provided in the present application;

fig. 2 is a schematic design diagram of a driving chip provided in the present application;

FIG. 3 is a schematic diagram of a driving chip cascade provided in the present application;

fig. 4 is a schematic structural diagram of a backlight module according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a driving chip cascade provided in an embodiment of the present application;

fig. 6 is a schematic structural diagram of another cascade connection of driving chips according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of still another cascade of driving chips according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of another backlight module according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of a fourth cascade of driving chips according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of a fifth cascade of driving chips according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of another backlight module according to an embodiment of the present disclosure;

fig. 12 is a schematic structural diagram of a backlight module according to an embodiment of the present application.

Specific embodiments thereof have been shown by way of example in the drawings and will herein be described in more detail. These drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.

The terms "first," "second," "third," "fourth" and the like in the description and in the claims and drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be capable of operation in sequences other than those illustrated or described herein, for example. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

At present, with the development of information technology, various display devices are widely used in order to facilitate people to acquire information.

Fig. 1 is a schematic structural diagram of a display device provided in the present application, where the display device includes: the panel 10, the backlight assembly 20, the main board 30, the power board 40, the rear case 50, and the base 60. Wherein the panel 10 is used for presenting a picture to a user; the backlight assembly 20 is located below the panel 10, and is usually some optical assemblies, and is used for providing enough brightness and uniformly distributed light sources to enable the panel 10 to display images normally, the backlight assembly 20 further comprises a backboard 201, a main board 30 and a power board 40 are arranged on the backboard 201, convex hull structures are usually punched on the backboard 201, and the main board 3 and the power board 4 are fixed on the convex hulls through screws or hooks; the rear case 50 is arranged on the panel 10 in a covering manner to hide the parts of the display device such as the backlight assembly 20, the main board 30, the power panel 40 and the like, thereby having an attractive effect; and a base 60 for supporting the display device.

In some embodiments, the display device further includes a driving board. The power panel is used for supplying power to the driving panel, the backlight assembly and the main board. And the main board is used for receiving the image signals transmitted by the external server or the optical fiber and the like, generating driving signals through processing the image signals, and sending the driving signals to the driving board so that the driving board drives the backlight assembly to emit light.

In some embodiments, as display panels in display devices are increasing, it is common to divide a backlight assembly into a plurality of light regions in the display devices, and thus to implement image display by multi-zone dimming.

In some embodiments, the backlight assembly and the driving board may be disposed on the same single panel, i.e., in a lamp driving integrated design.

Fig. 2 is a schematic design diagram of a driving chip provided in the present application. The driving chip in the figure is used for receiving the driving signal sent by the main board and controlling the backlight assembly to emit light according to the driving signal. In some examples, the drive signal includes a control signal and a clock signal. As shown in fig. 2, the driving chip includes two data signal interfaces (labeled MOSI and MISO in the figure) disposed on the left side of the chip, and a clock signal interface (labeled CLK in the figure), and 32 lamp area terminals (labeled LEDn in the figure), where n is an integer in the interval from 1 to 32 are disposed on the right side of the driving chip. In the figure, MOSI and CLK are used to receive control signals and clock signals for driving the lamp area, respectively. LEDs 1-32 are each configured to be connected to a corresponding light area. The MISO may output the control signal as an input signal to the MOSI interface in the next driver chip. When the number of the partitions of the light area in the display device is large and the number of the single driving chip light area shown in fig. 2 is insufficient, although the data signal interfaces of the plurality of driving chips and the clock signal interfaces can be theoretically connected, that is, the connection manner shown in fig. 3 is adopted, fig. 3 is a schematic diagram of a cascade connection of the driving chips provided in the application. When the scheme of realizing lamp driving integration on a single panel, the cascade connection of the driving chips can be connected with the MOSI port of another driving chip by bypassing the arrangement of the lamp area on the right side of the chip by the lead wires of the MISO interface of the current chip, meanwhile, at the CLK input port of the current chip, one end connecting wire is required to be connected with the CLK port of the next driving chip, and the number of the lamp areas is matched with the number of the lamp areas in the display device, but when the cascade connection of the driving chips is carried out on the actual single panel, the number of the lamp areas is more because the connecting wires for transmitting signals are required to be designed between the single driving chip and the single lamp area, and therefore, when the connecting wires between the data signal interfaces and the connecting wires between the clock signal interfaces when the driving chips are cascaded are designed, the connecting wires between the driving chips and the lamp areas and the space between the lamp areas are required to be considered, so that the layout of the wiring on the single-sided board circuit board is more complicated.

The application provides a backlight unit and display device, aims at solving prior art's above technical problem.

The following describes the technical solutions of the present application and how the technical solutions of the present application solve the above technical problems in detail with specific embodiments. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.

Fig. 4 is a schematic structural diagram of a backlight module according to an embodiment of the present application, where a display device includes a circuit board, a driving chip disposed on the circuit board, and a plurality of lamp areas corresponding to the driving chip.

The pins in the driving chip in this embodiment are used for receiving and transmitting the control signal or the clock signal sent by the motherboard. As shown in the figure, the driving chip in this embodiment is provided with a first pin 1 and a third pin 3 located on a first side, and a second pin 2 and a fourth pin 4 located on a second side; wherein, the first pin 1 and the second pin 2 are in electrical communication inside the driving chip, and the third pin 3 and the fourth pin 4 are in electrical communication inside the driving chip.

For example, as shown in fig. 4, in order to avoid that the driver chip needs to cross over multiple light zones when cascading, in designing the driver chip interface in this embodiment, it may be considered that pins for transmitting the control signal and the clock signal are respectively located on a first side and a second side opposite to the driver chip. And, a control terminal for connecting the lamp area is disposed at the third side of the driving chip. Specifically, as shown in the drawing, the first pin 1 is used for transmitting a control signal, and the third pin 3 is used for transmitting a clock signal in the driving chip. In order to facilitate wiring on the circuit board, when designing the pins of the driving chip, it is considered that the first pin 1 and the second pin 2 transmitting the control signal are respectively disposed at both sides of the driving chip, and the first pin 1 and the second pin 2 are electrically connected inside the driving chip. For example, in one example, it is conceivable to provide two leads at the control signal interface of the internal circuit of the driver chip, the end of one of the two leads forming the first pin 1 of the driver chip, leading from the first side of the driver chip; the end of the other lead forms a second pin 2 of the driver chip, leading out from the second side of the driver chip.

Likewise, a third pin 3 and a fourth pin 4, which are provided in the driving chip for transmitting the clock signal, are also provided at the first side and the second side of the driving chip, respectively, and the third pin 3 and the fourth pin 4 are in electrical communication inside the driving chip.

In addition, control terminals for connecting the lamp areas are also arranged on the driving chip, (3 control terminals are arranged in the figure and correspondingly connected with 3 lamp areas), and the control terminals are arranged on the third side of the driving chip, namely, are not arranged on the same side with the first pin 1 and the second pin 2. Furthermore, when a plurality of driving chips are required to be cascaded later, the driving chips can be directly connected with the pins arranged on the first side and the second side of the driving chips without wiring crossing the lamp area on the third side.

In an example, fig. 5 is a schematic structural diagram of a driving chip cascade provided in an embodiment of the present application, where chips arranged in rows are provided. In the figure, the row includes 4 driving chips, and each driving chip includes two control ends, and the two control ends are respectively connected with two lamp areas for example. The first pin 1 and the third pin 3 of the first driving chip located at the first side of the row are respectively used for receiving control signals and clock signals transmitted from the outside (e.g. a motherboard) of the circuit board. And the first pin 1 and the third pin 3 of the other driving chips in the row are respectively connected with the second pin 2 and the fourth pin 4 of the previous driving chip.

When the backlight module is required to work, after the first driving chip in the row receives the control signals and clock signals input by the main board through the first pin 1 and the second pin 2, the control signals and clock signals corresponding to the lamp areas can be determined from the control signals and clock signals according to the identifiers of the lamp areas connected with the driving chip so as to drive the lamp areas to emit light. And the control signal and the clock signal of the first driving chip are input to the main board, and the control signal and the clock signal for controlling the rest of the lamp areas in the row can be respectively output through the second pin and the fourth pin of the first driving chip, and the output control signal and the clock signal are respectively output to the first pin and the third pin of the second driving chip connected with the second pin and the fourth pin of the first driving chip, so that the control signal and the clock signal are sequentially transmitted to each driving chip to enable the lamp areas corresponding to each driving chip to emit light.

In this embodiment, based on the design of the pins of the driving chips, when the driving chips are cascaded, pins corresponding to clock signals and control signals can be directly connected, and wires bypassing a lamp area connected with the driving chips are not needed when the pins are connected, so that the wiring complexity of the cascade connection of the driving chips is reduced when the integrated design of the driving chips is realized on a single panel.

On the basis of the design of the pins of the driving chips in the embodiment, when a plurality of driving chips arranged in an array are arranged on the circuit board, at this time, the first pins 1 and the second pins 2 between the driving chips in the same row are sequentially connected, and the third pins 3 and the fourth pins 4 are sequentially connected; when the driving chips positioned at the tail of different rows are connected, a second pin 2 and a second pin 2 between the driving chips are connected, a fourth pin 4 and a fourth pin 4 are connected, and the second pin 2 between the driving chips are connected by using a cross wire, or the fourth pin 4 and the fourth pin 4 between the driving chips are connected by using a cross wire; when the first driving chips positioned in different rows are connected, the first pins 1 and the first pins 1 between the driving chips are connected, the third pins 3 and the third pins 3 are connected, and the first pins 1 between the driving chips are connected by using a cross wire or the third pins 3 and the third pins 3 between the driving chips are connected by using a cross wire.

Fig. 6 is a schematic structural diagram of still another cascade of driving chips according to an embodiment of the present application. In the figure, for example, 16 driving chips are arranged in an array, and each driving chip is provided with two control ends on the third side for driving the corresponding lamp area. When the driving chips arranged in the array are connected, the connection mode between the driving chips positioned in the same row still adopts the connection mode that the first pin 1 and the second pin 2 between the adjacent driving chips are connected, and the third pin 3 and the fourth pin 4 are connected. When the driving chips of different rows are connected, if the two driving chips are at the tail of the row, at the moment, the second pin 2 between the two driving chips is correspondingly connected with the second pin 2, and the fourth pin 4 is correspondingly connected with the fourth pin 4. In addition, when wiring is performed on the circuit board, the connection line between the second pins 2 and the connection line between the fourth pins 4 of the two driving chips are overlapped in a crossing manner, so that a cross-line connection manner can be adopted at the crossing point of the two connection lines.

Similarly, when the first driving chips in different rows are connected, the first pin 1 and the first pin 1 between the two chips need to be correspondingly connected, and the third pin 3 correspondingly connected. In addition, when two connecting wires are wired on the circuit board, a wiring cross point is also generated, so that a cross-line connection mode is also needed, and the problem of overlapping of wires on the circuit board is further avoided.

When the overlapping of the traces is avoided by using a cross-wire connection on the circuit board, in one example, the overlapping of the traces may be avoided by providing a cross-wire connection. For example, two wires may be routed directly on a circuit board at a meeting point on the circuit board, and one wire may be routed over the meeting point by a connecting wire such as a wire at the meeting point, thereby avoiding overlapping of the wires. In some examples, the connection lines for crossover may also be replaced with crossover resistors when the crossover is connected.

Taking the first pin 1 and the second pin 2 for transmitting control signals, the third pin 3 and the fourth pin 4 for transmitting clock signals as an example, when the driving chips at the end of the first row and the end of the second row shown in fig. 5 are connected, the wires between the fourth pin 4 and the fourth pin 4 for transmitting clock signals are directly arranged on the circuit board, and the wires between the second pin 2 and the second pin 2 for transmitting control signals adopt a crossover resistor at the intersection point between the two wires so that the wires cross the coincident point. Likewise, between the first driving chips of the second row and the third row, the third pin 3 and the third pin 3 are directly wired on the circuit board, and the first pin 1 are connected by using an overline resistor at a wire overlapping point.

Fig. 7 is a schematic structural diagram of still another cascade connection of driving chips provided in this embodiment, and, compared with fig. 6, when the pin connection of the last driving chip between different rows in fig. 7 is connected by a cross line, the connection between the fourth pins 4 for transmitting clock signals is adopted by the cross line connection. When the pin connection of the first driving chip between different rows is connected in a cross-line mode, the cross-line mode is adopted for connecting the connection between the third pins 3 for transmitting clock signals.

In some embodiments, pins between driving chips of different rows in the backlight module can randomly select wiring between any group of pins for cross-line connection without considering signals transmitted on the pins.

In this embodiment, when more lamp areas need to be driven, multiple driving chips may be arranged in an array, and when pins between driving chips in different rows are connected, a cross-line connection process is required to be performed at an overlapping point when pins of driving chips in different rows are connected, so as to avoid overlapping of wirings on a circuit board. In this embodiment, based on the pin arrangement of the driving chip provided in this embodiment of the present application, when the driving chip is arranged in an array, the operation complexity that the wiring for transmitting control signals and clock signals between the driving chips needs to cross a plurality of light areas can be reduced.

Fig. 8 is a schematic structural diagram of another backlight module according to an embodiment of the present application. On the basis of the pin arrangement of the driving chip shown in fig. 4, the driving chip in this embodiment is further provided with a fifth pin 5 and a sixth pin 6; the first pin 1, the third pin 3 and the fifth pin 5 are sequentially arranged on the first side of the driving chip; the second pin 2, the fourth pin 4 and the sixth pin 6 are sequentially arranged on the second side of the driving chip; the first pin 1, the second pin 2, the fifth pin 5 and the sixth pin 6 are electrically connected inside the driving chip.

As shown in fig. 8, the driving chip in the backlight module provided in the present embodiment is provided with a first pin 1, a second pin 2, a third pin 3, a fourth pin 4, a fifth pin 5, and a sixth pin 6. The first pin 1, the second pin 2, the fifth pin 5 and the sixth pin 6 are electrically connected inside the driving chip and are used for transmitting the same kind of signals. And the third pin 3 and the fourth pin 4 are electrically connected inside the driving chip and used for transmitting the same signals. In addition, when the pins are arranged, the first pin 1, the third pin 3 and the fifth pin 5 are arranged on the first side of the driving chip in sequence, namely, the third pin 3 for transmitting another signal is arranged between the first pin 1 and the fifth pin 5 for transmitting the same signal. Similarly, on the second side of the driving chip, the second pin 2, the fourth pin 4 and the sixth pin 6 are sequentially arranged, that is, the fourth pin 4 for transmitting another signal is disposed between the second pin 2 and the sixth pin 6 for transmitting the same signal.

In some embodiments, the first pin 1, the second pin 2, the fifth pin 5 and the sixth pin 6 are used for transmitting control signals of a lamp area in the backlight module; the third pin 3 and the fourth pin 4 are used for transmitting clock signals of the lamp area in the backlight module.

In some embodiments, the first pin 1, the second pin 2, the fifth pin 5 and the sixth pin 6 are used for transmitting clock signals of a lamp area in the backlight module; the third pin 3 and the fourth pin 4 are used for transmitting control signals of the lamp area in the backlight module.

When cascade connection is performed on the circuit board using the driving chip in the present embodiment, arrangement may be performed in the manner shown in fig. 9. Fig. 9 is a schematic structural diagram of a fourth cascade of driving chips according to an embodiment of the present application. When there are multiple driving chips arranged in a row, at this time, the first driving chip located in the row may use the third pin 3 to receive an externally input clock signal, and use the first pin 1 or the fifth pin 5 of the driving chip to receive an externally input control signal, where the third pins 3 of the remaining driving chips in the row are connected to the fourth pin 4 of the preceding chip, and are used for transmitting the clock signal. When transmitting the control signal, the connection relationship between the driving chips in the row may be that the first pin 1 of the driving chip is connected with the second pin 2 of the previous chip or that the fifth pin 5 of the driving chip is connected with the sixth pin 6 of the previous chip. The control terminal of the third side of the driver chip and the lamp area are not shown in the figure.

According to the pin design of the driving chip in the backlight module, when a plurality of driving chips are cascaded in rows, wiring design of connecting wires for transmitting clock signals and control signals between the driving chips on a circuit board does not need to bypass connecting wires between a lamp area located on the third side of the driving chip and the driving chips, and the problem that wiring design is complex when the driving chips are cascaded on the circuit board in the related art is avoided.

In some embodiments, based on the pin design in the driving chips in the backlight module of fig. 8, when a plurality of driving chips arranged in an array are required to be disposed on the circuit board, at this time, when the plurality of driving chips located in the same row are connected, the third pins 3 and the fourth pins 4 between the driving chips are sequentially connected; the first pin 1 and the second pin 2 between the driving chips are sequentially connected, or the fifth pin 5 and the sixth pin 6 are sequentially connected; when the driving chips positioned at the tail of different rows are connected, a fourth pin 4 among the driving chips is connected with the fourth pin 4, and a second pin 2 among the driving chips is connected with a sixth pin 6; when the first driving chips in different rows are connected, the third pins 3 among the driving chips are connected with the third pins 3, and the first pins 1 among the driving chips are connected with the fifth pins 5.

Fig. 10 is a schematic structural diagram of a fifth cascade of driving chips according to an embodiment of the present application. The figure is provided with 16 driving chips. When the driving chips arranged in the array are connected, the connection mode between the driving chips in the same row still adopts the mode that the third pin 3 and the fourth pin 4 between the adjacent driving chips are connected to transmit one signal (for example, a clock signal) and the other signal (for example, a control signal) is transmitted, and the mode that the first pin 1 and the second pin 2 or the fifth pin 5 and the sixth pin 6 between the adjacent driving chips are connected is considered.

When the driving chips of different rows are connected, if the two driving chips are at the tail of the row, at this time, in order to avoid the coincidence of the wires between the pins when the two driving chips are connected, on the basis that the fourth pin 4 of the two driving chips is connected with the fourth pin 4, the second pin 2 of one driving chip of the two driving chips can be considered to be connected with the sixth pin 6 of the other driving chip, or the sixth pin 6 of one driving chip is connected with the second pin 2 of the other driving chip, so that the phenomenon of cross overlapping of the wires between the connected driving chips on the circuit board can not occur.

Likewise, when the driving chips positioned at the first lines of different rows are connected, in order to avoid the coincidence of the connecting lines between the pins when the two driving chips are connected, on the basis that the third pin 3 of the two driving chips is connected with the third pin 3, the first pin 1 of one driving chip of the two driving chips is considered to be connected with the fifth pin 5 of the other driving chip, or the fifth pin 5 of one driving chip is connected with the first pin 1 of the other driving chip, so that the phenomenon of cross overlapping of the wiring between the connected driving chips on the circuit board can not occur.

In this embodiment, when the driving chip shown in fig. 8 is adopted and a plurality of driving chips arranged in an array are disposed on the driving chip, that is, the driving chips can be directly connected to corresponding pins for transmitting the same signal when being cascaded across rows, a mode that wiring overlaps and needs to be connected across lines does not occur. And when the cross-line resistor is adopted for connection, the reflection plate arranged above the lamp area in the backlight module is prevented from being bulged when the temperature of the cross-line resistor is higher, and the adjustment effect of the reflection plate on the direction of the light of the lamp area is easily affected.

In some embodiments, when the light area is connected to the driving chip, in one possible implementation manner, one end of the light area is connected to the driving chip by adopting a wiring manner on the circuit board, and the other end of the light area is also directly connected to the driving chip through the wiring manner on the circuit board, so that a conductive loop is formed on the driving chip and the light area.

In some embodiments, the plurality of control terminals disposed on the third side of the driving chip includes a common terminal and a plurality of output terminals; one end of a plurality of lamp areas corresponding to the driving chip is connected to the public end of the driving chip, and the other end of the corresponding plurality of lamp areas of the driving chip is respectively connected to a plurality of output ends of the driving chip.

For example, the driving chip in the present embodiment may correspond to a plurality of light areas, and one common terminal and a plurality of output terminals are provided in a plurality of control terminals on the third side of the driving chip when the driving chip is connected to the plurality of light areas. The plurality of output ends are in one-to-one correspondence with the plurality of lamp areas, and the other ends of the plurality of lamp areas are connected to the control ends corresponding to the plurality of output ends. The common terminal of the plurality of control terminals serves as a common wiring port of the plurality of lamp sections, and one end of each of the plurality of lamp sections is connected to the common terminal. For each lamp area, a conductive loop of a control end of the driving chip, the other end of the lamp area, one end of the lamp area and a common end of the driving chip is formed, so that the driving chip can control the lamp area.

That is, the same common terminal may be used between the plurality of lamp regions on the single driving chip in this embodiment. In addition, the multiple lamp regions in the present embodiment may adopt a common anode wiring or a common cathode wiring mode. When the lamp area adopts a common anode wiring mode, one end of the lamp area can be a positive common terminal, and then the positive common terminal of the lamp area is connected with a common terminal on a corresponding driving chip. When the lamp area adopts a common cathode electrode wiring mode, one end of the lamp area can be a negative common terminal, and then the negative common terminal of the lamp area is connected with a common terminal on a corresponding driving chip.

In this embodiment, a common terminal is disposed in the control terminal of the third side of the driving chip, so that one ends of the multiple lamp regions can be connected to the same common terminal, and the other ends of the multiple lamp regions are connected to the output terminals in the control terminal in a one-to-one correspondence manner. Furthermore, through the connection mode, the arrangement of pins in the driving chip can be simplified, and the connection is convenient.

In some embodiments, the driving chip is further provided with a plurality of control terminals located at a fourth side of the driving chip; the plurality of control ends are correspondingly connected with the lamp areas.

As shown in fig. 11, fig. 11 is a schematic structural diagram of another backlight module according to an embodiment of the present disclosure. In the drawing, a driving chip provided on a circuit board includes a first pin 1 and a third pin 3 provided on a first side and a second pin 2 and a fourth pin 4 provided on a second side. In addition, a plurality of control terminals are respectively disposed on the third side and the fourth side of the driving chip, 3 control terminals are disposed on the third side of the driving chip in fig. 9, and 3 control terminals are disposed on the other side of the driving chip. The 6 control terminals may be connected to the corresponding 6 lamp regions provided on the circuit board, respectively.

In this embodiment, a plurality of light areas may be connected to the third side and the fourth side of the driving chip, so that when the number of light areas driven by a single driving chip is increased, the arrangement of the light areas does not affect the connection between the driving chips in rows or in arrays, that is, the connection between the driving chips does not need to span the light areas and the connection lines between the light areas and the driving chips.

Fig. 12 is a schematic structural diagram of a backlight module according to another embodiment of the present application, where a plurality of control terminals disposed on a third side of a driving chip of a circuit board include a first common terminal, a first output terminal and a second output terminal; the plurality of control ends positioned on the fourth side of the driving chip comprise a second common end, a third output end and a fourth output end;

the driving chip is correspondingly provided with a first lamp area, a second lamp area, a third lamp area and a fourth lamp area; one end of the first lamp area and one end of the second lamp area are respectively connected to the first public end; the other end of the first lamp area is connected to the first output end; the other end of the second lamp area is connected to the second output end; one end of the third lamp area and one end of the fourth lamp area are respectively connected to the second common end; the other end of the third lamp area is connected to a third output end; the other end of the second lamp area is connected to the fourth output end.

As shown in fig. 12, the array of 16 driving chips is shown, and each driving chip includes a first common terminal, a first output terminal, a second common terminal, a third output terminal, and a fourth output terminal, which are disposed on a third side of the driving chip, in addition to six pins disposed on the first side and the second side. The first output end and the second output end on the third side of the driving chip are respectively connected with the other end of the first lamp area (lamp area 1 in the figure) and the other end of the second lamp area (lamp area 2 in the figure) corresponding to the driving chip, and the first common end on the third side of the driving chip is connected to one end of the first lamp area and one end of the second lamp area, so that a conductive path is formed between the first lamp area and the second lamp area and the driving chip respectively.

Similarly, the third output end and the fourth output end on the fourth side of the driving chip are respectively connected with the other end of the third lamp area (lamp area 3 in the figure) and the other end of the fourth lamp area (lamp area 4 in the figure) corresponding to the driving chip, and the second common end on the fourth side of the driving chip is connected to one end of the third lamp area and one end of the fourth lamp area, so that a conductive path is formed between the third lamp area and the fourth lamp area and the driving chip respectively.

In some embodiments, when the first common terminal and the second common terminal are provided, in order to avoid that when the lamp area is connected with the first common terminal or the second common terminal, the connection between the lamp area and the common terminal needs to cross the other lamp areas, so that the first common terminal can be arranged between the first output terminal and the second output terminal; the second common terminal is arranged between the third output terminal and the fourth output terminal, so that the wiring design on the circuit board is simplified.

In the backlight module provided in this embodiment, the pins for transmitting clock signals in the driving chip are respectively disposed on the first side and the second side in the driving chip, the pins for transmitting control signals are also respectively disposed on the first side and the second side of the driving chip, and the common end and the output end connected with the light area are respectively disposed on the third side and the fourth side of the driving chip, so that the driving chip does not need to cross the light area connected with the driving chip and the connection line between the driving chip and the light area during cascading, thereby facilitating cascading of the driving chip. In addition, in the driving chip, the third side and the fourth side are respectively provided with a first public end and a second public end, the first public end can be adopted by the first lamp area and the second lamp area which are connected to the third side, the second public end can be adopted by the third lamp area and the fourth lamp area which are connected to the fourth side, the first public end can be arranged between the first output end and the second output end, the second public end can be arranged between the third output end and the fourth output end, and the connection line between the lamp area and the driving chip is facilitated. Through the arrangement, when the number of the lamp areas is divided more, more driving chips can be used for cascading so as to meet the number requirement of the lamp areas.

In an embodiment of the present application, a display device is provided, including: the backlight module, the main board and the power supply in any embodiment; the power supply is connected with the backlight module and the main board and is used for providing power supply signals; the main board is connected with the backlight module and is used for sending control signals and clock signals to the backlight module so that the backlight module emits light based on the clock signals and the control signals.

The above technical description may refer to the accompanying drawings, which form a part of the present application, and in which are shown by way of illustration implementations in accordance with the described embodiments. While these embodiments are described in sufficient detail to enable those skilled in the art to practice them, these embodiments are non-limiting; other embodiments may be used, and changes may be made without departing from the scope of the described embodiments.

Additionally, terminology is used in the above technical description to provide a thorough understanding of the described embodiments. However, no overly detailed details are required to implement the described embodiments. Accordingly, the foregoing description of the embodiments has been presented for purposes of illustration and description. The embodiments presented in the foregoing description and examples disclosed in accordance with these embodiments are provided separately to add context and aid in the understanding of the described embodiments. The foregoing description is not intended to be exhaustive or to limit the described embodiments to the precise form disclosed. Several modifications, alternative adaptations and variations are possible in light of the above teachings. In some instances, well known process steps have not been described in detail in order to avoid unnecessarily obscuring the described embodiments.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A backlight module, comprising:

the LED lamp comprises a circuit board, a driving chip arranged on the circuit board and a plurality of lamp areas corresponding to the driving chip;

2. A backlight module according to claim 1, wherein,

a plurality of driving chips arranged in an array are arranged on the circuit board;

3. A backlight module according to claim 1, wherein,

the driving chip is also provided with a fifth pin and a sixth pin; the first pin, the third pin and the fifth pin are sequentially arranged on the first side of the driving chip, and the second pin, the fourth pin and the sixth pin are sequentially arranged on the second side of the driving chip; the first pin, the second pin, the fifth pin and the sixth pin are electrically communicated inside the driving chip.

4. A backlight module according to claim 3, wherein,

5. The backlight module of claim 4, wherein the first pin, the second pin, the fifth pin, and the sixth pin are used for transmitting control signals of a lamp area in the backlight module; the third pin and the fourth pin are used for transmitting clock signals of the lamp area in the backlight module;

6. A backlight module according to any one of claims 1-5, wherein,

the plurality of control terminals comprise a common terminal and a plurality of output terminals;

7. The backlight module according to claim 6, wherein the driving chip is further provided with a plurality of control ends located at a fourth side of the driving chip; the control ends are correspondingly connected with the lamp area.

8. The backlight module according to claim 7, wherein the plurality of control terminals of the driving chip on the third side of the driving chip include a first common terminal, a first output terminal and a second output terminal; the driving chip is positioned at a plurality of control ends of the fourth side of the driving chip and comprises a second common end, a third output end and a fourth output end;

9. The backlight module according to claim 8, wherein the first common terminal is located between the first output terminal and the second output terminal; the second common terminal is located between the third output terminal and the fourth output terminal.

10. A backlight module according to claim 9, wherein one end of the light section is a positive common terminal of the light section or one end of the light section is a negative common terminal of the light section.

11. A display device, characterized by comprising: the backlight module, the motherboard, the power supply according to any one of claims 1-10; the power supply is connected with the backlight module and the main board and is used for providing power supply signals; the main board is connected with the backlight module and is used for sending control signals and clock signals to the backlight module so that the backlight module emits light based on the clock signals and the control signals.