CN211457461U

CN211457461U - Light emitting diode driving chip

Info

Publication number: CN211457461U
Application number: CN202020124482.2U
Authority: CN
Inventors: 费小泂
Original assignee: Cool Silicon Semiconductor Technology Shanghai Co ltd
Current assignee: Cool Silicon Semiconductor Technology Shanghai Co ltd
Priority date: 2020-01-19
Filing date: 2020-01-19
Publication date: 2020-09-08
Anticipated expiration: 2030-01-19

Abstract

The utility model relates to emitting diode driver chip. The printed circuit board is provided with first to fourth pins arranged at a first side edge and fifth to eighth pins arranged at a second side edge, wherein the first side edge and the second side edge are opposite to each other. The first pin to the fourth pin are respectively a multiplexing pin, a power supply pin, a grounding pin, a signal input pin, and the fifth pin to the eighth pin are respectively a signal output pin and three current-filling pins. The driving chip receives communication data from the signal input pin and forwards the communication data from the signal output pin. And respectively adjusting the duty ratios of the constant currents output by the three current-filling pins according to the gray scale data matched with the red, green and blue light-emitting diodes respectively. When the driving chip is installed on the circuit board, the probability of generating cross between the power supply wiring butted to the power supply pin or the grounding pin and the communication wiring butted to the signal input pin or the signal output pin on the circuit board can be reduced. The driving chip is used for driving the full-color light-emitting diode light source.

Description

Light emitting diode driving chip

Technical Field

The utility model relates to the illumination display field, more specifically say, provide corresponding emitting diode driver chip in the illumination display scene that contains solid state emitting diode light source.

Background

In the field of illumination display, the number of pixels which can be driven by a single driving chip is limited, if an attempt is made to integrate ultra-large-scale pixels in a display system, a plurality of driving chips must be cascaded, and the pixels are provided with three primary color light emitting diodes. The pulse dimming technique is to change the time width of lighting or turning off the light emitting diode within a certain period of time, and simultaneously requires that the current flowing through the light emitting diode during the on-lighting period is a constant current value, thereby realizing the brightness change. According to the Grassmann's law and the standard chromaticity diagram defined by the International Commission on illumination, the reference color components of the pixels need to be allocated in a predetermined intensity range, and the visual system can distinguish that all perceived colors can be obtained almost depending on the gray scale change of three reference colors. The driver chips are usually cascaded by four communication lines, and the use of clock signal lines and data signal lines and load signal lines and output enable signal lines is the most typical four-wire communication example. Whether four-wire communication or two-wire communication using only clock signal lines and data signal lines or other multi-wire communication, the communication process can be realized by requiring very strict timing coordination between signals with different attributes transmitted on different signal lines. The single-wire serial transmission scheme is applied to the field of lighting display instead of the multi-wire communication, only a single independent communication wire is needed, and the advantages of simple wiring and elimination of timing matching elbow caused by traditional multi-wire communication are achieved. In the prior art, the limitation of the led driving chip is that the wires prepared for each pin on the circuit board are easy to cross, and the simplest method is a double-sided board using double-sided wiring or a multi-layer board using multi-layer wiring, but the cost and wiring complexity are sharply multiplied, and other implementation methods include using jumper wires or remote wire winding in the design of single-layer wiring. The present application aims to design the pin layout of the driver chip from the source and try to avoid the crossing of the wiring prepared for each pin on the circuit board.

SUMMERY OF THE UTILITY MODEL

The application relates to a light emitting diode driving chip, comprising:

first to fourth pins arranged at a first side of the driving chip;

fifth to eighth pins arranged at a second side of the driving chip;

the first side edge and the second side edge are opposite to each other;

the first pin, the second pin, the third pin and the fourth pin are arranged in the sequence from small to large in the anticlockwise direction according to the pin numbers, and the sequence is as follows:

the device comprises a multiplexing pin, a power supply pin, a grounding pin and a signal input pin;

the fifth pin to the eighth pin are sorted in the counterclockwise direction according to the sequence of the pin numbers from small to large, and the sequence is as follows:

a signal output pin and three current-filling pins;

the driving chip decodes and forwards the communication data in the single-wire serial format, receives the communication data from the signal input pin and forwards the communication data from the signal output pin, wherein the communication data at least comprises gray data;

the driving chip provides constant current at the current filling pin, three anodes of the red, green and blue light emitting diodes are coupled to the power supply pin, and three cathodes of the red, green and blue light emitting diodes are connected to the three current filling pins one by one;

the constant current is periodically output at a set duty ratio, and the drive chip respectively adjusts the duty ratios of the constant currents output by the three current-pouring pins according to gray data matched with the red, green and blue light-emitting diodes respectively;

when the driving chip is installed on the circuit board, the probability of the cross between the power supply wiring butted to the power supply pin or the grounding pin and the communication wiring butted to the signal input pin or the signal output pin on the circuit board is reduced.

The above led driving chip, wherein: multiplexing pin is vacant, for example, red, green and blue three-way light emitting diodes use red, green and blue three-in-one lamp beads; or when the white light emitting diode is used, the multiplexing pin is started, the driving chip also provides constant current at the multiplexing pin, and the anode and the cathode of the white light emitting diode are respectively coupled to the power supply pin and the multiplexing pin, for example, the red, green and blue three-way light emitting diode and the white light emitting diode use a red, green, blue and white four-in-one lamp bead.

The above led driving chip, wherein: on the premise of starting the multiplexing pin, when none of the three red, green and blue LEDs is lighted, the white LED is lighted by a constant current through the driving chip.

The above led driving chip, wherein: on the premise of starting the multiplexing pin, when the duty ratios of the constant currents output by the three current-sinking pins are adjusted in each cycle period, the current-on periods of the three current-sinking pins are set to be not overlapped with each other, and if the constant currents at the three current-sinking pins are all turned off, the current is turned on at the multiplexing pin.

The above led driving chip, wherein:

the butt joint relation between the sixth pin, the eighth pin and the red, green and blue light-emitting diodes comprises the following steps:

the sixth pin, the seventh pin and the eighth pin are respectively coupled to the cathode of the red light-emitting diode, the cathode of the green light-emitting diode and the cathode of the blue light-emitting diode; or

The sixth pin, the seventh pin and the eighth pin are respectively coupled to the cathode of the red light-emitting diode, the cathode of the blue light-emitting diode and the cathode of the green light-emitting diode; or

The sixth pin, the seventh pin and the eighth pin are respectively coupled to the cathode of the green light-emitting diode, the cathode of the blue light-emitting diode and the cathode of the red light-emitting diode; or

The sixth pin, the seventh pin and the eighth pin are respectively coupled to the cathode of the green light-emitting diode, the cathode of the red light-emitting diode and the cathode of the blue light-emitting diode; or

The sixth pin, the seventh pin and the eighth pin are respectively coupled to the cathode of the blue light-emitting diode, the cathode of the red light-emitting diode and the cathode of the green light-emitting diode; or

The sixth pin, the seventh pin and the eighth pin are respectively coupled to the cathode of the blue light-emitting diode, the cathode of the green light-emitting diode and the cathode of the red light-emitting diode.

The above led driving chip, wherein: the driving chip adjusts the duty ratio of constant current output by a current filling pin butted with the red light emitting diode according to the gray data matched with the red light emitting diode; the driving chip adjusts the duty ratio of constant current output by a current filling pin butted with the green light emitting diode according to the gray data matched with the green light emitting diode; the drive chip adjusts the duty ratio of the constant current output by the current filling pin butted with the blue light emitting diode according to the gray scale data matched with the blue light emitting diode.

The above led driving chip, wherein: the plurality of driving chips arranged in a long strip structure are connected in series between the positive electrode and the negative electrode of the power supply, the power supply pin of the first driving chip is coupled to the positive electrode, the ground pin of the last driving chip is coupled to the negative electrode, and the circuit board is provided with a power supply wiring and a communication wiring which extend along the long strip structure:

the power supply pin of the latter driving chip is coupled to the grounding pin of the adjacent former driving chip through power supply wiring;

the signal output pin of the latter driver chip is coupled to the signal input pin of the adjacent former driver chip through the communication wiring.

The above led driving chip, wherein: an energy storage capacitor is connected between a power supply pin and a grounding pin of each driving chip; and a coupling capacitor is connected to the signal input pin of each driving chip so that the communication data can be transmitted to the driving chip through the coupling capacitor.

The above led driving chip, wherein: the plurality of driving chips connected in series between the anode and the cathode of the power supply are connected in series with the current source chip and used for maintaining the total input current of each driving chip at a preset value determined by the current source chip.

The above led driving chip, wherein: the power supply wiring and the communication wiring between any two adjacent driving chips are arranged in a side-by-side wiring layout.

The application relates to another light emitting diode driving chip, which comprises:

first to fourth pins arranged at a first side of the driving chip;

fifth to eighth pins arranged at a second side of the driving chip;

the first side edge and the second side edge are opposite to each other;

three current-sinking pins and a signal output pin;

the device comprises a signal input pin, a grounding pin, a power supply pin and a multiplexing pin;

The above led driving chip, wherein:

the butt joint relation between the first pin, the second pin, the third pin and the red, green and blue light-emitting diodes comprises the following steps:

the first pin, the second pin and the third pin are respectively coupled to the cathode of the red light-emitting diode, the cathode of the green light-emitting diode and the cathode of the blue light-emitting diode; or

The first pin, the second pin and the third pin are respectively coupled to the cathode of the red light-emitting diode, the cathode of the blue light-emitting diode and the cathode of the green light-emitting diode; or

The first pin, the second pin and the third pin are respectively coupled to the cathode of the green light-emitting diode, the cathode of the blue light-emitting diode and the cathode of the red light-emitting diode; or

The first pin, the second pin and the third pin are respectively coupled to the cathode of the green light-emitting diode, the cathode of the red light-emitting diode and the cathode of the blue light-emitting diode; or

The first pin, the second pin and the third pin are respectively coupled to the cathode of the blue light-emitting diode, the cathode of the red light-emitting diode and the cathode of the green light-emitting diode; or

The first pin, the second pin and the third pin are respectively coupled to the cathode of the blue light-emitting diode, the cathode of the green light-emitting diode and the cathode of the red light-emitting diode.

Drawings

To make the above objects, features and advantages more comprehensible, embodiments accompanied with figures are described in detail below, and features and advantages of the present invention will become apparent upon reading the following detailed description and referring to the figures.

Fig. 1 shows that the gray scale data sent by the master node is distributed to the slave nodes which need to drive three light emitting diodes.

Fig. 2 is a schematic circuit topology of a driving chip for driving rgb leds.

Fig. 3 shows that the gray scale data sent by the master node is distributed to the slave nodes which need to drive four paths of light emitting diodes.

Fig. 4 is a driving chip for driving rgb leds and driving white leds.

Fig. 5 shows a layout of three current-sinking pins designed to interface red, green and blue leds.

Fig. 6 shows a layout of three current-sinking pins designed to be red, blue, green and butt-jointed with red, green and blue leds.

Fig. 7 shows a layout of three current-sinking pins designed to be green, red and blue to interface with rgb leds.

Fig. 8 shows a layout of three current-sinking pins designed to be green, blue and red to interface with rgb leds.

Fig. 9 shows a layout of three current-sinking pins designed to be blue-red-green to interface with rgb leds.

Fig. 10 shows three current-sinking pins designed to interface with rgb leds in a blue-green-red layout.

FIG. 11 shows four current-sinking pins designed to interface with RGB and white light LEDs.

Fig. 12 shows a plurality of cascade-connected driver chips connected in series between the positive pole of the power supply and the negative pole of the power supply.

Fig. 13 shows an example of the layout of the pins on the first side and the second side of the driver chip opposite to each other.

Fig. 14 is an example in which driving chips in a red, green, and blue three-way light emitting diode mode are cascade-connected.

Fig. 15 is an example of cascade connection of driving chips in a driving rgb and white led mode.

Fig. 16 is an example of four pin swapping locations at the first side and the second side.

Fig. 17 is an example of a driving chip with a pin-adjusted position being cascade-connected when driving a three-way diode.

Fig. 18 is an example of cascade connection of the driver chips after the pin-modulation position when driving the four-way diode.

Fig. 19 is a topology of the driving chip after the pin adjusting position when driving three light emitting diodes.

Fig. 20 is a topology of the driving chip with the pin-adjusted position when driving the four-way light emitting diode.

Detailed Description

The present invention will be described more fully hereinafter with reference to various embodiments, which are provided as illustrations of examples and not all embodiments, and all embodiments that can be obtained without creative efforts by those skilled in the art are within the scope of the present invention.

Referring to fig. 1, the screen resolution of the display system refers to the precision of the screen image, and generally refers to the number of pixels that the display system can display at maximum. Because the points, lines and planes on the screen are all composed of pixel points, the more pixels the display system can display, the finer the picture is, and the more and clearer the information can be displayed in the screen area, so that the screen resolution is an important performance index for the display system. The cascade driving chips are arranged on the pixel points in occasions such as building lightening and commercial lighting, and the master node MST sends communication data to the slave node IC1-ICN of the chips. Communication between the master node and the slave nodes allows the use of standardized communication protocols or customized non-standardized communication protocols, the master and slave nodes each being provided with interface circuits for enabling data communication, the number N of slave nodes being a positive integer exceeding 1. The communication with the more general display technology is to adopt a plurality of transmission lines, for example, four, to realize the transmission of communication signals: the clock signal line and the data signal line and the loading signal line and the output enable signal line work together, communication data are sequentially transmitted in series and are matched with each other through four-line signals to control the slave nodes of all levels of connection. A communication protocol using only data lines and a clock line and a latch line for a total of three lines is also a mainstream communication scheme of the display technology. When the pixel spacing is larger, double-line transmission is adopted, and the double-line transmission of a data line and a clock line is the compromise between the number of the data lines and the transmission rate. Although the general multi-wire protocol is suitable for communication between a master node and a plurality of cascade-connected slave nodes and communication data is transmitted, the alternative single-wire communication is more suitable for transmission of display data as a preferred embodiment, and the advantage of the single-wire protocol is that only a single data wire is required for transmission of cascade data.

Referring to fig. 1, in the display field, pixels or lamp beads LAP are used as display units, and each independent pixel adopts three primary colors of red, green and blue to mix colors to obtain full color. Three primary color mixing can constitute about sixteen million colors, provided that each color has eight bits of grayscale data, and the reference color of any single color will have 256 levels of grayscale. Further, assuming that each color has up to ten bits of gray scale data, and a reference color of any single color has 1024-step gray scale, approximately one billion colors can be formed after three primary colors are mixed. The grayscale data of an image often carries duty cycle information. The fields of display screens, illumination, decoration and the like widely use the RGB-LED three-in-one lamp bead LAP as a full-color solid-state light source, and the three primary colors serving as examples can be replaced by other arbitrary colors in pixel points. The slave node IC is often a constant current driving chip in the industry and has both functions of adjusting gray scales and adjusting brightness, and output current channels provided by the constant current driving chip to the solid-state light source are all provided with a function of dimming by using a pulse width modulation signal. The slave node IC does not need an additional communication function if it is set to directly perform the gray-scale adjustment using the locally stored gray-scale data, and the slave node IC needs to be equipped with a communication function if it needs to receive external communication data and perform the gray-scale adjustment by on-line retrieving and refreshing the gray-scale data.

Referring to fig. 1, after receiving data of the current stage, any slave node can automatically shape the subsequent data and forward the subsequent data to the next stage by a data forwarding function, and the data is not distorted or attenuated as the cascade becomes farther. If the master node MST passes a first data source to the first slave node IC1 and a second data source to the second slave node IC2, and so on, the nth data source is passed to the nth slave node ICN, provided that N is a positive integer greater than 1. The slave nodes comprise, for example, led driver chips and the data sources contain respective gray scale data of the three primary colors red, green and blue. The controller included in the master node MST is selected from a field programmable gate array, a processor, a state machine, a microprocessor, a logic circuit, a software-driven control device or a complex programmable logic device, a semi-customized ASIC or a single chip microcomputer and the like, and is used for processing communication data. The transmission mode of the data source comprises multi-line transmission or single-line serial transmission. Data transmission in the form of a return-to-one code or zero code is the most common in the case of single-wire transmission, and manchester coding is also associated with the single-wire transmission scheme. The communication mode under single-wire transmission conditions typically requires the slave node to have a data forwarding function: for example, each slave node receives the communication data transmitted from the master node, and needs to extract the data source belonging to its own unit first and forward the other data sources not belonging to its own unit to the subsequent slave nodes connected in cascade, so that the slave nodes IC1 to ICN are required to be in cascade connection.

Referring to fig. 1, it is set for convenience of explanation that each driving chip only illustrates three light emitting diodes as a supporting driving light source. The number of light sources specified is not in any way limiting in nature. Assuming that each slave node decodes three gray scale data of red, green and blue from the communication data sent by the master node, the first pulse width modulation module in each slave node forms a first pulse width modulation signal corresponding to the first light emitting diode LED1 according to the gray scale data allocated to the first light emitting diode LED 1. The second pwm module forms a second pwm signal corresponding to the second LED2 from the gray scale data assigned to the second LED 2. The third pwm module generates a third pwm signal corresponding to the third LED3 based on the gray scale data distributed to the third LED 3. The three light emitting diodes are, for example, red, green and blue light emitting diodes, and the gray scale data assigned to the three light emitting diodes are red gray scale data, green gray scale data and blue gray scale data, respectively. The duty ratio information carried by the gray scale data, which is customary in the field of illumination displays, is reflected in the duty ratio of the pulse width modulated signal.

Referring to fig. 2, although a driving chip 100 in the form of an integrated circuit is illustrated as a typical example of driving the light-emitting diode light source to light up. It is to be emphasized that this does not mean that the driver circuit can only be designed as an integrated circuit since discrete electronic components can also build up a functionally equivalent driver circuit. The driver circuit can be designed either as a semiconductor chip or be constructed from discrete electronic components. The most central role of the data transmission module TRAN of the driver chip 100 is to implement the above-mentioned data transmission and have the decoding function: the driver chip decodes the gray data from the received communication data or decodes the current adjusting data from the communication data, and in fact, the decoder restores the signal having the preset encoding rule in the communication data into the common binary data no matter the current adjusting data or the gray data, that is, the data transmission module decodes the serial data according to the preset communication protocol. This also supports the diversity of the communication data: which may be either current adjustment data or grayscale data. The output currents of the constant current units CS1 to CS3 of the driver chip 100 can also be adjusted online according to the current adjustment data. Circuits, such as over-temperature protection, start-up protection, electrostatic protection, transient voltage protection, and peak current leakage circuit, etc., which play a basic protection role, as well as oscillators, power-on reset circuits, and even clock circuits, etc., all belong to optional or necessary functions of the chip, and are well known by those skilled in the art and therefore will not be described in detail.

Referring to fig. 2, the essence of pulse width modulation is to convert the amplitude of a signal into the time of the signal, and the implementation mechanism of pulse width modulation roughly includes technical routes such as a count comparison mode, a delay unit mode, a shift mode, a mixed mode of count comparison and delay, and the like, and the pulse width signal with a certain duty ratio is obtained in any route. The so-called digital pulse width modulation, DPWM, in the industry is within the scope of the prior art. The pulse width modulation module of the driving chip 100 may form a pulse width modulation signal according to the gray data, and the gray data is used to determine the duty ratio of the pulse width modulation signal, i.e., the pulse width modulation signal is considered to represent the duty ratio information carried by the gray data. The driving chip is also called as a display control chip, and drives the red, green and blue three-primary-color light emitting diodes to light and color and drives the solid-state light source to realize full-color display.

Referring to fig. 2, only three current sinking pins are illustrated for convenience of explanation, and it should be understood that the number of current sinking pins and the number of light sources are illustrated for reference only. The driving chip 100 decodes the communication data to obtain the required gray data, and the first pulse width modulation module of the pulse width modulation module PWM forms the first pulse width modulation signal D1 corresponding to the first light emitting diode LED1 according to the gray data allocated to the first light emitting diode LED 1. The second pwm module forms a second pwm signal D2 corresponding to the second LED2 from the gray data assigned to the second LED 2. The third pwm module forms a third pwm signal D3 corresponding to the third LED3 from the gray scale data assigned to the third LED 3. Each specific pulse width modulation module in the pulse width modulation modules forms a corresponding path of pulse width modulation signal according to the gray scale data matched with the corresponding path of light emitting diode: that is, a pulse width modulation signal corresponding to each light emitting diode is formed based on the gray scale data assigned to each light emitting diode, and the duty ratio of the pulse width modulation signal is determined corresponding to the gray scale data. The light sources LED 1-LED 3 may be illustrated directly as multiplexed light emitting diodes RGB of the three primary colors red, green and blue. In an alternative example, a shunt branch may be further disposed between the power pin terminal and the ground pin terminal, and a series structure of the light emitting diode and the constant current unit and the shunt branch are coupled between the power pin terminal and the ground pin terminal in parallel. The shunt branch is, for example, a three-terminal shunt regulator having a cathode coupled to the power pin terminal and an anode coupled to the ground pin terminal, and a reference terminal of the three-terminal shunt regulator is coupled to a voltage dividing node of a voltage divider, for example, if the voltage divider can be a resistor voltage divider connected between the power pin and the ground pin, an interconnection node between two voltage dividing resistors of the resistor voltage divider is regarded as a voltage dividing node of the voltage divider. The three-terminal parallel voltage regulator can be integrated into the driving chip and used as an internal functional module, and can also be independent of the driving chip. Other names of three-terminal shunt regulators in the industry include three-terminal adjustable shunt reference sources or three-terminal adjustable precision reference circuits, etc.

Referring to fig. 2, a first light emitting diode LED1 is connected in series with a constant current unit CS1, and it is noted that the constant current unit CS1 generating a constant current is controlled by a first pulse width modulation signal D1. The first pwm signal D1 determines the constant current lighting time of the first led in the period of the first pwm signal D1. A constant current of full amplitude is applied to the light source in a repetitive pulse train that is on or off: when the current is on, for example, the first pwm signal D1 has a high logic level, the constant current is applied to the first LED1, and when the current is off, the constant current is disconnected from the first LED1, for example, the first pwm signal D1 has a low logic level. The cathode of the first light emitting diode LED1 is coupled to the eighth pin OUT1 of the driving chip 100, and a constant current unit CS1 in the form of sink current is disposed between the eighth pin OUT1 and the ground pin GND of the driving chip.

Referring to fig. 2, a second light emitting diode LED2 is provided in series with a constant current unit CS2, noting that the constant current unit CS2 generating a constant current is controlled by a second pulse width modulation signal D2. The second pwm signal D2 determines the constant current lighting time of the second led in the period of the second pwm signal D2. A constant current of full amplitude is applied to the light source in a repetitive pulse train that is on or off: when the current is on, for example, the second pwm signal D2 has a high logic level, the constant current is applied to the second LED2, and when the current is off, the constant current is disconnected from the second LED2, for example, the second pwm signal D2 has a low logic level. The cathode of the second light emitting diode LED2 is coupled to the seventh pin OUT2 of the driving chip 100, and a constant current unit CS2 in the form of sink current is disposed between the seventh pin OUT2 and the ground pin GND of the driving chip.

Referring to fig. 2, the third light emitting diode LED3 is provided in series with the constant current unit CS3, note that the constant current unit CS3 generating a constant current is controlled by the third pulse width modulation signal D3. The third pwm signal D3 determines the constant current lighting time of the third led in the cycle of the second pwm signal D3. A constant current of full amplitude is applied to the light source in a repetitive pulse train that is on or off: when the current is on, for example, the third pwm signal D3 has a high logic level, the constant current is applied to the third LED3, and when the current is off, the constant current is disconnected from the third LED3, for example, the third pwm signal D3 has a low logic level. The cathode of the third light emitting diode LED3 is coupled to the sixth pin OUT3 of the driving chip 100, and a constant current unit CS3 in the form of sink current is disposed between the sixth pin OUT3 and the ground pin GND of the driving chip.

Referring to fig. 2, a simple scheme is that each light emitting diode and one constant current unit are coupled in series between a power pin terminal and a ground pin terminal. It is shown that the first path of light emitting diode and constant current unit CS1 is connected in series between the power supply pin terminal VDD and the ground pin terminal GND, the second path of light emitting diode and constant current unit CS2 is connected in series between the power supply pin terminal VDD and the ground pin terminal GND, and the third path of light emitting diode and constant current unit CS3 is connected in series between the power supply pin terminal VDD and the ground pin terminal GND. Note that the common anode of each light emitting diode receives power at the power pin VDD of the driver chip, so that the power supply voltage at the power pin VDD can be directly utilized to supply power to each light emitting diode such as red, green, blue, and the like. The power supply voltage at the power pin terminal VDD is also a power supply for driving other functional modules in the chip, in addition to being used as a power supply for the light source. The stable voltage obtained by linear or switch type or charge pump type voltage conversion of the power supply voltage at the power supply pin terminal can also supply power to each path of light emitting diode.

Referring to fig. 2, the foregoing driving circuit topology is by no means the only solution, for example, the positions of each light emitting diode and the corresponding constant current unit may be interchanged to meet the requirements of the driving chip for sourcing or sinking current. Except that the power supply voltage or the power supply at the power pin end VDD can be directly used for supplying power to the light source, the partial pressure of the power supply voltage input at the power pin end VDD can also supply power to each path of light emitting diode. In an alternative example, each of the led light sources and the corresponding one of the constant current units are coupled in series between the divided voltage of the power supply voltage and the ground pin terminal. Other examples allow to perform a linear or switch-type or charge pump-type voltage conversion of the supply voltage at the power pin terminal VDD, the stable voltage obtained by the voltage conversion being used to power the light emitting diodes: each path of light emitting diode light source and the corresponding path of constant current unit are coupled in series between the stable voltage obtained by voltage conversion and the grounding pin end.

Referring to fig. 2, allowing the driving chips and the current source modules described later to be cascade-connected to each other also allows the driving chips to be cascade-connected to each other so that they should have a data forwarding function. The core function of the driving chip is to drive the multiple paths of light emitting diodes matched with the driving chip to light up according to the display requirement. Changing the lighting time of the red, green and blue light emitting diodes in the period can change the brightness ratio of the light emitting diodes with various colors, which is equivalent to changing the relative brightness ratio of three primary colors, thereby obtaining different colors when the gray scale of the light emitting diodes changes. The data transmission module TRAN of the driver chip 100 decodes the input serial data according to a predetermined communication protocol, decodes the gray data and the like from the received communication data, and adjusts the color of the pixel points according to the gray data assigned to the rgb leds. The signal input end DI receives communication data provided from outside and the data transmission module TRAN needs to decode data information carried in the communication data, and the meaning of data decoding is that data in a pre-coding format which cannot be directly displayed by the light emitting diode can be restored to a conventional binary code element which is easy to recognize and execute. The decoded binary code is temporarily stored in a shift register, usually the data of the register is refreshed quickly and needs to be updated frequently, a buffer or a latch is used for storing the decoded data and the gray data is read from the latch by a pulse width modulation module PWM, and then the pulse width modulation module PWM generates a pulse width signal according to the gray data. The protocol schemes such as a return-to-one code, a return-to-zero code or a Manchester code are the common single-wire communication protocols for communication data transmission, coding and decoding.

Referring to fig. 2, the driver chip 100 is assumed by the data transmission module TRAN to perform data regeneration or data reconstruction to complete data forwarding tasks such as transmitting communication data to the rear driver chip. Although not shown in the figure, the simplest forwarding mode is transparent transmission or direct transmission, which allows the communication data received by the signal input terminal DI to be directly output from the signal output terminal DO, and then the driving chip 100 or the current source ICS connected in cascade are used to extract the communication data corresponding to its own address and belonging to its own address from the single data line according to their respective address allocation rules. In the transparent transmission mode, communication data seen by each slave node is identical, and each slave node only intercepts own data. The alternative forwarding scheme needs to be matched with statistics of communication data belonging to each level of driving chip, each level of driving chip forwards the rest other received communication data to a next level of communication data receiver cascaded with the driving chip after extracting the communication data belonging to the driving chip from each frame of communication data, and the next level of communication data receiver can be a next level of driving chip or a current source module and the like. In this forwarding mode, each driver chip will count whether the total number of bits of the communication data belonging to the driver chip is completely received, and if the communication data belonging to a certain driver chip is decoded by the driver chip and completely received, that is, the count result of the total number of bits reaches the expected number, the driver chip 100 will forward the communication data received by the signal input terminal DI of the driver chip from the signal output terminal DO. The data transmission module at this time acts as a switch for allowing the received communication data to be forwarded and output: the data forwarding is forbidden before the total bit number required by the driving chip reaches the expected number, and the data forwarding is enabled when the total bit number reaches the expected number.

Referring to fig. 3, it is convenient for explanation to set each driving chip to drive a schematic four-way led as a supporting driving light source. The number of light sources specified is not in any way limiting in nature. Assuming that each slave node decodes three gray scale data of red, green and blue from the communication data sent by the master node, the first pulse width modulation module in each slave node forms a first pulse width modulation signal corresponding to the first light emitting diode LED1 according to the gray scale data allocated to the first light emitting diode LED 1. The second pwm module forms a second pwm signal corresponding to the second LED2 from the gray scale data assigned to the second LED 2. The third pwm module generates a third pwm signal corresponding to the third LED3 based on the gray scale data distributed to the third LED 3. There are various ways of controlling the fourth LED 4. For example, each slave node decodes three sets of gray scale data of red, green and blue as well as another set of additional gray scale data, and the fourth pulse width modulation module of the slave node forms a fourth pulse width modulation signal corresponding to the fourth light emitting diode from the gray scale data distributed to the fourth light emitting diode LED 4. But still for example three instead of four sets of gray data. The cycle period shared by the first to third pulse width modulation signals is divided into three sub-time periods: the effective logic values, such as high level, of the first pwm signal are distributed in the corresponding first sub-period, the effective logic values, such as high level, of the second pwm signal are distributed in the corresponding second sub-period, and the effective logic values, such as high level, of the third pwm signal are distributed in the corresponding third sub-period. The end of the first sub-period is followed by the second sub-period and the end of the second sub-period is followed by the third sub-period within each cycle period, and the total time length of the first to third sub-periods is exactly equal to the cycle period common to the first to third pwm signals. And switching the fourth pulse width modulation signal to high level in the first sub-period when the first pulse width modulation signal has an invalid logic value such as low level in the first sub-period. Similarly, when the second pwm signal has an inactive logic value, such as low level, in the second sub-period, the fourth pwm signal switches to high level in the second sub-period. And when the third pulse width modulation signal has an invalid logic value such as low level in the third sub-period, the fourth pulse width modulation signal is switched to high level in the third sub-period. However, when any one of the first to third pwm signals has a valid logic value, such as a high level, the fourth pwm signal switches to a low level. In this example, the RGBW-LED four-in-one lamp bead LAP is widely used as a pixel point in the fields of display screens, lighting, decoration and the like.

Referring to fig. 4, only four current sinking pins are illustrated for convenience of explanation, and it should be understood that the number of current sinking pins and the number of light sources are illustrated for reference only. The driving chip 100 decodes the communication data to obtain the required gray data, and the first pulse width modulation module of the pulse width modulation module PWM forms the first pulse width modulation signal D1 corresponding to the first light emitting diode LED1 according to the gray data allocated to the first light emitting diode LED 1. The second pwm module forms a second pwm signal D2 corresponding to the second LED2 from the gray data assigned to the second LED 2. The third pwm module forms a third pwm signal D3 corresponding to the third LED3 from the gray scale data assigned to the third LED 3. The fourth pwm module forms a fourth pwm signal D4 corresponding to the fourth LED4 from the gray data assigned to the fourth LED 4. In an example where four sets of gray-scale data form four pulse width modulation signals, the fourth light emitting diode can be not only a red or green or blue light source but also other color light sources such as a white light source.

Referring to fig. 4, compared with the foregoing driving chip, a constant current unit CS4 is mainly added, and a fourth light emitting diode LED4 is added. The fourth light emitting diode LED4 is connected in series with the constant current unit CS4, and the constant current unit CS4 generating the constant current is controlled by the fourth pulse width modulation signal D4. The fourth pwm signal D4 determines the constant current lighting time of the fourth led in the period of the fourth pwm signal D4. A constant current of full amplitude is applied to the light source in a sequence of repeated pulses that are on or off: when the current is on, for example, the fourth pwm signal D4 has a high logic level, the constant current is applied to the fourth LED4, and when the current is off, the constant current is disconnected from the fourth LED4 when the fourth pwm signal D4 has a low logic level. The cathode of the fourth light emitting diode LED4 is coupled to a multiplexing pin OUT4/NC of the driving chip, and a constant current unit CS4 in a current sinking mode is arranged between the pin OUT4/NC and a grounding pin GND of the driving chip. In comparison with the previous example in which the driving chip forms four pulse width modulation signals according to the respective matched gray data of the four light emitting diodes, the four pulse width modulation signals are respectively used for adjusting the duty ratios of the respective output constant currents of the four current-sinking pins. The forming mechanism of the fourth PWM signal D4 can be seen from the dotted output path of the PWM module PWM in the figure, and the forming mechanisms of the four PWM signals D1-D4 are the same, that is, they all use the gray data to form the PWM signals.

Referring to fig. 4, in an alternative example, the fourth pwm signal D4 is formed by a different mechanism than the first through third pwm signals. For example, each pixel point is assigned three sets of gray data instead of four sets of gray data. Dividing the total time of the single common cycle period T of the first to third PWM signals into three consecutive sub-periods: the first sub-period T1 occurs first within the cycle, the second sub-period T2 follows the end of the first sub-period T1 and the third sub-period T3 follows the end of the second sub-period T2. It can be seen that the total time length of the first to third sub-periods, i.e. the sum T1+ T2+ T3, is exactly equal to the total time of a single cycle period T.

Referring to fig. 4, the effective logic value, e.g., the high logic value, of the first pwm signal D1 is distributed in the first sub-period T1 corresponding thereto. In the first sub-period T1, when the first pwm signal D1 has an active logic value, such as a high level, the first LED1 is turned on, and when the first pwm signal D1 has an inactive logic value, such as a low level, the first LED1 is turned off. And the active logic value, e.g., high level, of the first pwm signal D1 only occurs in the first sub-period T1 and does not occur in the second and third sub-periods.

Referring to fig. 4, the effective logic value, e.g., the high logic value, of the second pwm signal D2 is distributed in the second sub-period T2 corresponding thereto. In the second sub-period T2, the second LED2 is turned on when the second pwm signal D2 has a logic value of active logic, such as high level, and the second LED2 is turned off when the second pwm signal D2 has a logic value of inactive logic, such as low level. And the active logic value, e.g., the high level, of the second pwm signal D2 occurs only in the second sub-period T2 and does not occur in the first and third sub-periods.

Referring to fig. 4, the effective logic values, e.g., high logic, of the third pwm signal D3 are distributed in the third sub-period T3 corresponding thereto. In the third sub-period T3, the third LED3 is turned on when the third pwm signal D3 has an active logic value, such as high level, and the third LED3 is turned off when the third pwm signal D3 has an inactive logic value, such as low level. And the active logic value, e.g., the high level, of the third pulse width modulation signal D3 only occurs during the third sub-period T3 and does not occur during the first and second sub-periods.

Referring to fig. 4, the fourth pwm signal D4 is formed by: the result of the NOR logic operation performed on the three PWM signals D1-D3 is regarded as the fourth PWM signal D4. Specifically, for example, the first to third pwm signals D1 and D2 and D3 are respectively input to the input terminal of the NOR gate NOR, and the result obtained by performing NOR logic operation on the first to third pwm signals is used to control whether the constant current unit CS4 is turned on or off, and the result is regarded as the fourth pwm signal. In the first sub-period T1, as long as the first pwm signal D1 has an inactive logic value, e.g., low level, the fourth pwm signal D4 switches to high level, and when the first pwm signal has an active logic value, e.g., high level, the fourth pwm signal D4 switches to low level. When the second pwm signal D2 is at a low level during the second sub-period T2, the fourth pwm signal D4 is switched to a high level, and when the second pwm signal D4 is at a high level, the fourth pwm signal D4 is switched to a low level. In the third sub-period T3, when the third pwm signal D3 is at a low level, the fourth pwm signal D4 switches to a high level, and when the third pwm signal is at a high level, the fourth pwm signal D4 switches to a low level. The second pwm signal is at a low level as long as any one of the first to third pwm signals is at a valid logic value, such as a high level. The first to third PWM signals are all of non-effective logic values such as low level, and the fourth PWM signal is high level.

Referring to fig. 4, if only three-in-one lamp beads are used, the multiplexing pin OUT4/NC is vacant. If a four-in-one light bulb is used as the light source, the multiplexing pin OUT4/NC can be utilized. The fourth LED4 claim a white LED and the driver chip is required to provide a constant current at the multiplexing pin OUT4/NC, the anode and cathode of the white LED are coupled to the power supply pin and the multiplexing pin, respectively. On the premise of enabling the multiplexing pin OUT4/NC, when the duty ratios of the constant currents output by the three current sinking pins OUT1-OUT3 are adjusted in each cycle period, the current turn-on periods of the three current sinking pins, namely OUT1-OUT3, are set to be not overlapped with each other, and if the constant currents at the three current sinking pins are all turned off, the current is turned on at the multiplexing pin. The explanation is as follows: the current-on period of the pin OUT1 is a high-level period of the first pwm signal D1 in the first sub-period T1, the current-on period of the pin OUT2 is a high-level period of the second pwm signal D2 in the second sub-period T2, and the current-on period of the pin OUT3 is a high-level period of the third pwm signal D3 in the third sub-period T3, so that the current-on periods of the three current-sinking pins do not overlap each other in each cycle.

Referring to fig. 4, if the constant currents of the three sink current pins OUT1-OUT3 are all turned off, i.e., the first to third pwm signals D1-D3 all have an inactive logic value, e.g., a low level, the fourth pwm signal D4 is at a high level and turns on the current at the multiplexing pin OUT 4/NC. The main reasons are that the valid logic value, e.g., the high level, of the first pwm signal D1 only occurs in the first sub-period T1 and does not occur in the second and third sub-periods, the valid logic value, e.g., the high level, of the similar second pwm signal D2 only occurs in the second sub-period T2 and does not occur in the first and third sub-periods, and the valid logic value, e.g., the high level, of the similar third pwm signal D3 only occurs in the third sub-period T3 and does not occur in the first and second sub-periods. The cycle period common to the first to third pulse width modulation signals is divided into three sub-periods such that: in the first sub-period T1, when the first pwm signal D1 is low and the second and third pwm signals D2-D3 are also low, the first to third pwm signals D1-D3 are all low, and the fourth pwm signal is high and turns on the current at the multiplexing pin OUT4/NC to light the LED 4. The second sub-period T2 is when the second pwm signal D2 is low and the first and third pwm signals D1-D3 are also low, so that the first to third pwm signals D1-D3 are all low, and the fourth pwm signal is high and turns on the current at the multiplexing pin OUT4/NC to light the LED 4. The third sub-period T3 is when the third pwm signal D3 goes low and the first and second pwm signals D1-D2 are also low, so that the first to third pwm signals D1-D3 are all low, and the fourth pwm signal goes high and turns on the current at the multiplexing pin OUT4/NC to light the LED 4.

Referring to fig. 5, the first to third LEDs, LEDs 1 to LEDs 3, respectively adopt red LEDs R, green-blue LEDs G and blue LEDs B, that is, the layout of the three current-sinking pins of the driving chip is OUT1-OUT3 respectively corresponding to red, green and blue.

Referring to fig. 6, the first to third LEDs, LEDs 1 to LEDs 3, respectively adopt red LEDs R, blue LEDs B and green-blue LEDs G, that is, the layout of the three current-sinking pins of the driving chip is OUT1-OUT3 respectively corresponding to red, blue, green and blue.

Referring to fig. 7, the first to third LEDs, LEDs 1 to LEDs 3, respectively adopt green LEDs G, red LEDs R and blue LEDs B, that is, the layout of the three current-sinking pins of the driving chip is OUT1-OUT3 respectively corresponding to green, red and blue.

Referring to fig. 8, the first to third LEDs, LEDs 1 to LEDs 3, respectively adopt green LEDs G, blue LEDs B and red LEDs R, that is, the layout of the three current sinking pins of the driving chip is OUT1-OUT3 respectively corresponding to green, blue and red.

Referring to fig. 9, the first to third LEDs, LEDs 1 to LEDs 3, respectively adopt blue LEDs B, red LEDs R and green LEDs G, that is, the layout of the three current-sinking pins of the driving chip is OUT1-OUT3 respectively corresponding to blue and red.

Referring to fig. 10, the first to third LEDs, LEDs 1 to LEDs 3, add up three LEDs, i.e., blue LED B, green LED G and red LED R, respectively, i.e., the layout of the three current sinking pins of the driving chip is OUT1-OUT3, which correspond to cyan and red, respectively.

Referring to fig. 11, the first to third LEDs, LEDs 1 to LEDs 3, add three LEDs, red LED R, green LED G and blue LED B, respectively, i.e. the layout of the three current-sinking pins of the driving chip is OUT1-OUT3 corresponding to red, green and blue, respectively. The layout of the sink current pins OUT1-OUT3 can be changed to red, blue, green, blue, red, green, blue, green, blue. While the layout of the multiplexing pin OUT4/NC is designed to interface to the cathode of the white light emitting diode W or to the cathode of other alternate color light sources.

Referring to fig. 12, explanation is made with a plurality of stages of driving chips connected in cascade. The driving chips are arranged in a single column or a plurality of columns on the power supply path. And a main node MST of a data sending end such as a server or a microprocessor is used for sending communication data to each level of driving chips. When transmitting communication data to a driver chip or a current source or the like in the form of a column: defining that the power pin of the first driving chip in each row is coupled to the positive pole and the ground pin of the last driving chip is coupled to the negative pole, the communication data can be transmitted from the driving chip at the tail of the row to the propagation direction of the driving chip at the head of the row, and for comparison, the communication data can be transmitted from the driving chip at the head of the row to the propagation direction of the driving chip at the tail of the row. The signal output terminal DO of the previous or previous driver chip in the cascade may be configured to be coupled to the signal input terminal DI of the next or next driver chip through a coupling capacitor C. The cascade propagation of the communication data will now be exemplified. Assume that three driver chips are connected in cascade and twenty-four bits of gray data are allocated to each driver chip: after the first driver chip receives the first twenty-four bit data from the master node in advance, the second twenty-four bit data from the master node is received by the first driver chip, and the total number of bits required by the first driver chip reaches the expected number, so that the first driver chip directly forwards the second twenty-four bit data to the second driver chip. The first driver chip subsequently receives the third twenty-four bit data from the master node, and then the third twenty-four bit data is forwarded to the second driver chip according to the forwarding rule, because the total number of bits required by the second driver chip also reaches the expected number, the second driver chip will forward the third twenty-four bit data to the third driver chip.

Referring to fig. 12, the cascade driving chips are arranged in one or more columns in the power supply path. The power pin terminal VDD of the first driver chip 100 at the head of each column is coupled to the positive voltage VP, and the ground pin terminal GND of the last driver chip 100 at the tail of the column is coupled to the negative voltage VN. The power pin terminal of the next driving chip is also arranged in each column and is coupled to the grounding pin terminal of the previous driving circuit. In this example, the power pin terminal VDD of the second driver chip 100 is coupled to the current outlet terminal GND of the adjacent first driver chip 100, which is also the ground pin terminal VDD, as in the first column. The power pin terminal VDD of the third driver chip 100 in the first column is connected to the current outflow terminal, i.e., the ground pin terminal GND, of the adjacent second driver chip 100. And for example, the power pin terminal VDD of the fourth driver chip 100 may be coupled to the current outflow terminal, i.e., the ground pin terminal GND, of the adjacent third driver chip 100 in the first column. The power pin terminal VDD of the last driver chip 100 in the first column is coupled to the current outflow terminal of the second last driver chip 100, i.e., the ground pin terminal GND. For example, the power pin terminal VDD of the second last driver chip 100 may be coupled to the current outlet terminal GND of the third last driver chip 100 in the first column. Thus, it can be seen that: in the power supply relationship, the power pin end of the rear driving chip in each row of the cascade driving chips is coupled to the ground pin end of the adjacent front driving chip until all the driving chips in each row are connected in series or superposed between the positive electrode VP and the negative electrode VN of the external power supply voltage. As a voltage stabilizing option, a capacitor CZ may be disposed between the power pin terminal VDD and the ground pin terminal GND of each driver chip. The total output current of the previous driver chip in each column is considered as the total input current of the adjacent subsequent driver chip, or the total input current of all the driver chips in each column is considered to be equal, which is determined by the series structure of all the driver chips.

Referring to fig. 12, a power supply line of each column of driving chips, such as the first column of driving chips, is provided with a current source ICS module for maintaining the total input current of each driving chip in the column at a predetermined value. The respective driver chip 100 and current source ICS module are connected in series between the positive and negative poles of the supply voltage in the first column on the left. The current inflow terminal, i.e. the power pin terminal VDD, of the first driver chip 100 is not directly connected to the positive supply voltage VP but indirectly coupled to the positive supply voltage via the current source ICS module. The current input terminal of the current source ICS module is connected to the supply voltage positive electrode VP, and the current output terminal of the current source ICS module is connected to the power pin terminal VDD of the first driver chip 100. The current source functions to provide a high accuracy and stable output current to a target object having a constant current demand. The current source ICS may also comprise the aforementioned data transmission module TRAN and have a signal output DI and a signal output DO. The current source ICS decodes the current adjustment data from the received communication data and adjusts the magnitude of the output current according to the current adjustment data. The current source can be adjusted between the ground pin GND of the last driving chip 100 and the negative electrode VN of the external power source, for example, the current input terminal of the current source module is connected to the ground pin GND of the last driving chip 100 and the current output terminal of the current source module is connected to the negative electrode VN of the external power supply voltage. Alternatively, the position of the current source ICS may be adjusted between any two adjacent driver chips 100: for example, among any adjacent two front and rear driver chips: the current input terminal of the current source module is asserted to be connected to the ground pin terminal GND of the previous driver chip 100, and the current output terminal of the current source module is asserted to be connected to the power pin terminal VDD of the next driver chip 100. The definition of current source ICS is that it requires the total value of the input current flowing from its current input to be equal to the total value of the output current flowing from its current output. Therefore, the total input current of any one of the driving chips in each row is equal to the output current of the current source module, the current source module in each row of the driving chips is connected in series with the driving chip 100, and the total input current of any one of the driving chips 100 in each row of the driving chips is limited to a predetermined value determined by the current source ICS module. In an improved example: the current source ICS module has no communication function of receiving current regulation data or communication data, namely, the output current provided by the current source ICS is set to be fixed and not programmable on line, a data transmission module is naturally not needed, the current source does not participate in communication cascade with a driving chip and does not have a signal output end and a signal output end, and the prior art has a current source chip. The communication data is transmitted to the driving chips or the current sources in the form of columns, in the cascade connection relationship, the signal output terminal DO of the upper current source is coupled to the signal input terminal DI of the adjacent lower driving chip by the coupling capacitor, or the signal output terminal DO of the driving chip is coupled to the signal input terminal DI of the adjacent lower current source by the coupling capacitor, and then the current source and the driving chip are cascaded.

Referring to fig. 13, the driver chip is described based on a semiconductor chip or circuit level, which is encapsulated by an epoxy-based material and is shown in a TOP VIEW (TOP VIEW). The metal pins extend from the inside of the package to the outside of the package. For the sake of brevity, the wafer supporting components such as the lead frame or the base for supporting the semiconductor wafer and the connecting components such as the bonding wires for electrically connecting the bonding pads of the semiconductor wafer to the metal leads are not separately illustrated, and the details and technical solutions are not repeated in consideration of the common general knowledge in the semiconductor wafer packaging industry. MARK information is usually required to be marked on the package body by laser or ink to distinguish and distinguish different pins, for example, the illustrated dot MARKs are used to identify the first pin of the chip.

Referring to fig. 13, the first to fourth pins are disposed at a first side of the driver chip, and the fifth to eighth pins are disposed at a second side of the driver chip, the first side and the second side being opposite to each other. The first pin, the second pin, the third pin and the signal input pin DI are sequentially arranged in the anticlockwise direction from small to large according to pin numbers, namely a multiplexing pin OUT4/NC, namely a first pin, a second pin, namely a power supply pin VDD, a grounding pin GND, namely a third pin and a signal input pin DI, namely a fourth pin. The fifth pin, the second pin, the third pin, the fourth pin, the fifth pin, the current sinking pin OUT3, the sixth pin, the current sinking pin OUT2, the seventh pin and the eighth pin, the current sinking pin OUT1 are arranged in the counterclockwise direction according to the sequence of the pin numbers from small to large. The arrow pointing direction of the dotted line with radian in the figure is the counterclockwise direction, and the numbers of the first to fourth pins in the figure are denoted as pins 1-4 and the numbers of the fifth to eighth pins are denoted as pins 5-8.

Referring to fig. 14, referring back to fig. 12, each row of driver chips, i.e., the illustrated plurality of driver chips 100 arranged in a long stripe structure on the circuit board 200, is connected in series between the positive and negative poles of the power supply. Wherein the power pin VDD of the first driver chip 100 of the plurality of driver chips cascaded in each row is coupled to the positive electrode, and the ground pin GND of the last driver chip 100 of the plurality of driver chips cascaded in each row is coupled to the negative electrode. Only three driver chips are illustrated in the space-limited diagram as representative of the many driver chips in the cascade.

Referring to fig. 14, a scheme for implementing power supply and communication with respect to each column of driver chips: the circuit board 200 is provided with power supply wiring 205 and communication wiring 208 extending along the elongated structure. See fig. 15: the power supply pin VDD of a subsequent driver chip is coupled to the ground pin GND of an adjacent previous driver chip through the power supply wiring 205. In contrast, it can be known that the signal output pin DO of the latter driver chip is coupled to the signal input pin DI of the adjacent former driver chip through the communication wiring 208. An energy storage capacitor CZ is connected between a power supply pin VDD and a ground pin GND of each driving chip, and a coupling capacitor C is connected to a signal input pin DI of each driving chip to transmit communication data to the driving chip through the coupling capacitor C. In this example, the cathode of the first LED1 is coupled to the pin OUT1 of the driver chip 100, the cathode of the second LED2 is coupled to the pin OUT2, and the cathodes of the remaining third LED3 are coupled to the pin OUT 3. Among the three driving chips shown in the figure, the driving chip on the right side is closer to the positive electrode of the power supply and the driving chip on the left side is closer to the negative electrode of the power supply, the driving chip which is ranked more forward is closer to the positive electrode of the power supply, and the driving chip which is ranked more backward is closer to the negative electrode of the power supply. The signal output pin DO of the next-to-row driver chip is coupled to the signal input pin DI of the next-to-row adjacent driver chip, which is equivalent to allowing communication data to pass from the last driver chip to the first driver chip. In an alternative example: it is naturally also allowed that the signal output pin DO of the front-ranked driver chip is coupled to the signal input pin DI of the adjacent, rear-ranked driver chip via the communication wiring 208, in which case there may be some slight crossovers between the communication wirings. No matter the transmission direction of the communication data, for a certain designated driving chip: the probability of the power supply wiring 205 on the circuit board 200 being connected to the power supply pin VDD or the ground pin GND of the designated driver chip crossing the communication wiring 208 connected to the signal input pin DI or the signal output pin DO of the designated driver chip can be reduced, and it is essential to try to avoid or reduce the crossing between the power supply wiring 205 connected to the power supply pin or the ground pin and the communication wiring 208 connected to the signal input pin or the signal output pin. For the entire string of driving chips, the power supply wiring 205 and the communication wiring 208 extending along the strip structure are almost parallel wirings, so that the two wirings can avoid crossing.

Referring to fig. 15, and reviewing fig. 14, one of the goals of the illustrated pin layout approach is: when the driver chip is mounted on a flexible circuit board or a conventional rigid printed circuit board or a similar chip carrier substrate, it is possible to preferably reduce the possibility that the power supply wiring 205 on the circuit board, which is connected to the power supply pin VDD or the ground pin GND, crosses the communication wiring 208 connected to the signal input pin DI or the signal output pin DO. The cathode of the first LED1 is coupled to the pin OUT1 of the driver chip 100, the cathode of the second LED2 is coupled to the pin OUT2, and the cathode of the remaining third LED3 is coupled to the pin OUT 3. The difference from fig. 14 is that: the cathode of an additional fourth LED4 is coupled to pin OUT 4/NC. The common anodes of the four paths of light emitting diodes are all coupled to the power supply pin VDD of the driving chip. The power supply wiring between the common anode and the power supply pin VDD needs to be routed from the second side to the first side along the third side near the first and eighth pins, although the distance of this power supply wiring appears to be slightly elongated but without crossing. The fourth side edge is close to the fourth pin and the fifth pin, and the third side edge and the fourth side edge which are opposite to each other are the other group of opposite edges of the driving chip. The cathode of the fourth light emitting diode LED4 is also routed along the third side to the first side by a connective wiring.

Referring to fig. 16, the main differences compared to fig. 13 are: the original four pins at the first side edge and the original four pins at the second side edge are exchanged in a mirror symmetry mode. The first to fourth pins are arranged at the first side edge of the driving chip, and the fifth to eighth pins are arranged at the second side edge of the driving chip. The first pin, the second pin, the third pin and the fourth pin are arranged in the sequence from small to large in the anticlockwise direction and respectively comprise: the current sinking pin OUT1 is a first pin, the current sinking pin OUT2 is a second pin, the current sinking pin OUT3 is a third pin, and the signal output pin DO is a fourth pin. The fifth pin, the eighth pin and the fourth pin are arranged in the sequence from small to large in the anticlockwise direction: the signal input pin DI is a fifth pin, the sixth pin is a ground pin GND, the power supply pin VDD is a seventh pin, and the multiplexing pin OUT4/NC is an eighth pin. The arrow of the dotted line with radian in the figure indicates the counterclockwise direction, and the numbers of the first to fourth pins are labeled as pins 1-4 and the numbers of the fifth to eighth pins are labeled as pins 5-8 corresponding to the pin numbers. The arrow with the arc of the dotted line in the figure points to the counterclockwise direction, and usually MARK is printed on the package of the semiconductor chip with laser or ink to facilitate distinguishing and distinguishing different pins, for example, the illustrated dot MARK is used to identify the first pin of the chip.

Referring to fig. 17, referring back to fig. 12, each column of driver chips, i.e., the illustrated plurality of driver chips 100 arranged in a long stripe structure on the circuit board 200, is connected in series between the positive and negative poles of the power supply. Wherein the power pin VDD of the first driver chip 100 of the plurality of driver chips cascaded in each row is coupled to the positive electrode, and the ground pin GND of the last driver chip 100 of the plurality of driver chips cascaded in each row is coupled to the negative electrode. Only three driver chips are illustrated in the space-limited diagram as representative of the many driver chips in the cascade.

Referring to fig. 17, a scheme for implementing power supply and communication with respect to each column of driver chips: the circuit board 200 is provided with power supply wiring 205 and communication wiring 208 extending along the elongated structure. See fig. 18: the power supply pin VDD of a subsequent driver chip is coupled to the ground pin GND of an adjacent previous driver chip through the power supply wiring 205. In contrast, it can be known that the signal output pin DO of the latter driver chip is coupled to the signal input pin DI of the adjacent former driver chip through the communication wiring 208. An energy storage capacitor CZ is connected between a power supply pin VDD and a ground pin GND of each driving chip, and a coupling capacitor C is connected to a signal input pin DI of each driving chip to transmit communication data to the driving chip through the coupling capacitor C. In this example, the cathode of the first LED1 is coupled to the pin OUT1 of the driver chip 100, the cathode of the second LED2 is coupled to the pin OUT2, and the cathodes of the remaining third LED3 are coupled to the pin OUT 3. Among the three driving chips shown in the figure, the driving chip positioned on the left side is closer to the positive electrode of the power supply, the driving chip positioned on the right side is closer to the negative electrode of the power supply, the driving chip positioned on the front side is closer to the positive electrode of the power supply, and the driving chip positioned on the back side is closer to the negative electrode of the power supply. The signal output pin DO of the next-to-row driver chip is coupled to the signal input pin DI of the next-to-row adjacent driver chip, which is equivalent to allowing communication data to pass from the last driver chip to the first driver chip. In an alternative example: it is of course also permissible for the signal output pin DO of the front-ranked driver chip to be coupled to the signal input pin DI of the adjacent, rear-ranked driver chip via the communication wiring 208, in which case there may be some slight crossovers between the communication wirings. No matter the transmission direction of the communication data, for a certain designated driving chip: the probability of the power supply wiring 205 on the circuit board 200 being connected to the power supply pin VDD or the ground pin GND of the designated driver chip crossing the communication wiring 208 connected to the signal input pin DI or the signal output pin DO of the designated driver chip can be reduced, and it is essential to try to avoid or reduce the crossing between the power supply wiring 205 connected to the power supply pin or the ground pin and the communication wiring 208 connected to the signal input pin or the signal output pin. For the entire string of driving chips, the power supply wiring 205 and the communication wiring 208 extending along the strip structure are almost parallel wirings, so that the two wirings can avoid crossing.

Referring to fig. 18, and reviewing fig. 17, one of the goals of the illustrated pin layout approach is: when the driver chip is mounted on a flexible circuit board or a conventional rigid printed circuit board or a similar chip carrier substrate, it is possible to preferably reduce the possibility that the power supply wiring 205 on the circuit board, which is connected to the power supply pin VDD or the ground pin GND, crosses the communication wiring 208 connected to the signal input pin DI or the signal output pin DO. The cathode of the first LED1 is coupled to the pin OUT1 of the driver chip 100, the cathode of the second LED2 is coupled to the pin OUT2, and the cathode of the remaining third LED3 is coupled to the pin OUT 3. The difference from fig. 17 is that: the cathode of an additional fourth LED4 is coupled to pin OUT 4/NC. The common anodes of the four paths of light emitting diodes are all coupled to the power supply pin VDD of the driver chip, and the power supply wiring between the common anode and the power supply pin VDD needs to be routed from the first side to the second side along the third side close to the first and eighth pins, although the distance of the power supply wiring is slightly elongated but has no crossing phenomenon. The fourth side edge is close to the fourth pin and the fifth pin, and the third side edge and the fourth side edge which are opposite to each other are the other group of opposite edges of the driving chip. The cathode of the fourth light emitting diode LED4 is also routed along the third side to the second side by connective wiring.

Referring to fig. 19, the main differences compared to fig. 2 are: the original four pins of the first side edge and the original four pins of the second side edge are in mirror symmetry. The first light emitting diode LED1 and the constant current unit CS1 are arranged in series, and it is noted that the constant current unit CS1 generating the constant current is controlled by the first pulse width modulation signal D1. The first pwm signal D1 determines the constant current lighting time of the first led in the period of the first pwm signal D1. A constant current of full amplitude is applied to the light source in a repetitive pulse train that is on or off: when the current is on, for example, the first pwm signal D1 has a high logic level, the constant current is applied to the first LED1, and when the current is off, the constant current is disconnected from the first LED1, for example, the first pwm signal D1 has a low logic level. The cathode of the first light emitting diode LED1 is coupled to the first pin OUT1 of the driver chip 100, and a constant current unit CS1 in the form of sink current is disposed between the first pin OUT1 and the ground pin GND of the driver chip.

Referring to fig. 19, a second light emitting diode LED2 is provided in series with a constant current unit CS2, noting that the constant current unit CS2 generating a constant current is controlled by a second pulse width modulation signal D2. The second pwm signal D2 determines the constant current lighting time of the second led in the period of the second pwm signal D2. A constant current of full amplitude is applied to the light source in a repetitive pulse train that is on or off: when the current is on, for example, the second pwm signal D2 has a high logic level, the constant current is applied to the second LED2, and when the current is off, the constant current is disconnected from the second LED2, for example, the second pwm signal D2 has a low logic level. The cathode of the second light emitting diode LED2 is coupled to the second pin OUT2 of the driving chip 100, and a constant current unit CS2 in the form of sink current is disposed between the second pin OUT2 and the ground pin GND of the driving chip.

Referring to fig. 19, the third light emitting diode LED3 is provided in series with the constant current unit CS3, note that the constant current unit CS3 generating a constant current is controlled by the third pulse width modulation signal D3. The third pwm signal D3 determines the constant current lighting time of the third led in the cycle of the second pwm signal D3. A constant current of full amplitude is applied to the light source in a repetitive pulse train that is on or off: when the current is on, for example, the third pwm signal D3 has a high logic level, the constant current is applied to the third LED3, and when the current is off, the constant current is disconnected from the third LED3, for example, the third pwm signal D3 has a low logic level. The cathode of the third light emitting diode LED3 is coupled to the third pin OUT3 of the driving chip 100, and a constant current unit CS3 in the form of sink current is disposed between the third pin OUT3 and the ground pin GND of the driving chip. Note that the aforementioned leds are not repeatedly depicted in fig. 19 because fig. 17-18 have already been illustrated. The driver chip is illustrated in fig. 16 at the chip package level and in fig. 19 at the semiconductor die or circuit level.

Referring to fig. 20, compared with the foregoing driving chip, a constant current unit CS4 is mainly added, and a fourth light emitting diode LED4 is added. The fourth light emitting diode LED4 is connected in series with the constant current unit CS4, and the constant current unit CS4 generating the constant current is controlled by the fourth pulse width modulation signal D4. The fourth pwm signal D4 determines the constant current lighting time of the fourth led in the period of the fourth pwm signal D4. A constant current of full amplitude is applied to the light source in a sequence of repeated pulses that are on or off: when the current is on, for example, the fourth pwm signal D4 has a high logic level, the constant current is applied to the fourth LED4, and when the current is off, the constant current is disconnected from the fourth LED4 when the fourth pwm signal D4 has a low logic level. The cathode of the fourth light emitting diode LED4 is coupled to a multiplexing pin OUT4/NC of the driving chip, and a constant current unit CS4 in a current sinking mode is arranged between the pin OUT4/NC and a grounding pin GND of the driving chip. Various mechanisms for forming the fourth pwm signal are explained in detail above: for example, each slave node decodes another set of extra gray scale data in addition to the three sets of gray scale data of red, green and blue, and the fourth pulse width modulation module forms a fourth pulse width modulation signal corresponding to the fourth light emitting diode from the gray scale data distributed to the fourth light emitting diode. Or the cycle period shared by the first path to the third path of pulse width modulation signals is divided into three sub-time periods: the effective logic values, such as high level, of the first pwm signal are distributed in the corresponding first sub-period, the effective logic values, such as high level, of the second pwm signal are distributed in the corresponding second sub-period, the effective logic values, such as high level, of the third pwm signal are distributed in the corresponding third sub-period, and the results of the nor-logic operations performed on the first to third pwm signals D1-D3 are regarded as the fourth pwm signal. The example of fig. 20 is applicable to the chip package level of fig. 16.

While the above description and drawings represent a typical example of a particular arrangement of the embodiments, the present invention is illustrative of the presently preferred embodiments, and is not to be construed as limited to the specific embodiments shown. Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. It is therefore intended that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to be within the intent and scope of the present invention.

Claims

1. A driving chip for driving a light emitting diode, comprising:

first to fourth pins arranged at a first side of the driving chip;

fifth to eighth pins arranged at a second side of the driving chip;

the first side edge and the second side edge are opposite to each other;

a signal output pin and three current-filling pins;

the constant current is periodically switched on and off at a set duty ratio, and the drive chip respectively adjusts the duty ratios of the constant currents output by the three current-pouring pins according to gray data matched with the red, green and blue light-emitting diodes respectively;

2. The driver chip of claim 1, wherein:

the multiplexing pin is left vacant; or

The multiplexing pin is enabled when a white light emitting diode is used, the driver chip also provides a constant current at the multiplexing pin, and the anode and cathode of the white light emitting diode are coupled to the power supply pin and the multiplexing pin, respectively.

3. The driving chip of claim 2, wherein:

on the premise of starting the multiplexing pin, when the duty ratios of the constant currents output by the three current-sinking pins are adjusted in each cycle period, the current-on periods of the three current-sinking pins are set to be not overlapped with each other, and if the constant currents at the three current-sinking pins are all turned off, the current is turned on at the multiplexing pin.

4. The driver chip of claim 1, wherein:

5. The driver chip of claim 1, wherein:

the driving chip adjusts the duty ratio of constant current output by a current filling pin butted with the red light emitting diode according to the gray data matched with the red light emitting diode;

the driving chip adjusts the duty ratio of constant current output by a current filling pin butted with the green light emitting diode according to the gray data matched with the green light emitting diode;

the drive chip adjusts the duty ratio of the constant current output by the current filling pin butted with the blue light emitting diode according to the gray scale data matched with the blue light emitting diode.

6. The driver chip of claim 1, wherein:

the circuit board is provided with a plurality of driving chips which are arranged into a long strip structure and are connected in series between the positive pole and the negative pole of a power supply, wherein the power supply pin of the first driving chip is coupled to the positive pole, the grounding pin of the last driving chip is coupled to the negative pole, and the circuit board is provided with a power supply wiring and a communication wiring which extend along the long strip structure:

7. The driver chip of claim 1, wherein:

an energy storage capacitor is connected between the power supply pin and the grounding pin;

the signal input pin is connected with a coupling capacitor so that the communication data can be transmitted to the driving chip through the coupling capacitor.

8. The driver chip of claim 6, wherein:

the plurality of driving chips connected in series between the positive electrode and the negative electrode of the power supply are also arranged to be connected in series with the current source chip for maintaining the total input current of each driving chip at a preset value determined by the current source chip.

9. The driver chip of claim 6, wherein:

the power supply wiring and the communication wiring between any two adjacent driving chips are arranged in a side-by-side wiring layout.

10. A driving chip for driving a light emitting diode, comprising:

first to fourth pins arranged at a first side of the driving chip;

fifth to eighth pins arranged at a second side of the driving chip;

the first side edge and the second side edge are opposite to each other;

three current-sinking pins and a signal output pin;

11. The driver chip of claim 10, wherein:

the multiplexing pin is left vacant; or

12. The driver chip of claim 11, wherein:

13. The driver chip of claim 10, wherein:

14. The driver chip of claim 10, wherein:

15. The driver chip of claim 10, wherein:

16. The driver chip of claim 10, wherein:

17. The driver chip of claim 15, wherein:

the plurality of driving chips connected in series between the anode and the cathode of the power supply are also connected in series with the current source chip and used for maintaining the total input current of each driving chip at a preset value determined by the current source chip.

18. The driver chip of claim 15, wherein: