CN216434274U - Testing tool for chip type semiconductor device - Google Patents
Testing tool for chip type semiconductor device Download PDFInfo
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- CN216434274U CN216434274U CN202122726807.1U CN202122726807U CN216434274U CN 216434274 U CN216434274 U CN 216434274U CN 202122726807 U CN202122726807 U CN 202122726807U CN 216434274 U CN216434274 U CN 216434274U
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- daughter board
- board
- contact pin
- mother board
- semiconductor device
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Abstract
The utility model relates to a test fixture of piece formula semiconductor device, daughter board more than mother board and 3, characterized by is female, the daughter board is double-deck PCB board, the mother board is including the installation through-hole, daughter board socket and first, the second contact pin seat, set up on the daughter board and be surveyed device station and contact pin subassembly, it includes the recess to be surveyed the device station, probe and gland, probe and the pin of being surveyed the device are corresponding, probe and contact pin subassembly's contact pin one-to-one are connected, daughter board socket's quantity is corresponding with contact pin subassembly's quantity, the daughter board passes through contact pin subassembly and is connected with the mother board with daughter board socket's cooperation, the mother board passes through the installation through-hole and is connected with the workstation, the positive input of mother board, output and first contact pin seat connection, the input at the mother board back, the output is connected with the second contact pin seat, first contact pin seat, the second contact pin seat is connected with test system respectively. The utility model aims at providing a simple structure, low cost, convenient to use, efficiency of software testing are high and be favorable to avoiding the maloperation.
Description
Technical Field
The utility model relates to a semiconductor device's test, particularly, piece formula semiconductor device's test fixture.
Background
The chip type semiconductor device is widely applied to the aerospace field. In the process of developing and producing chip semiconductor devices, defective products (commonly called inferior-quality products) may appear due to quality control and the like, and the chip semiconductor devices have short service life and high failure rate, and obviously do not meet the high reliability requirement in the aerospace field. Therefore, the chip type semiconductor device must be subjected to a performance screening test before use. At present, the chip semiconductor devices are generally placed into testing equipment for testing one by using tweezers manually, so that the labor intensity is high, and the testing efficiency is low. Especially for chip semiconductor devices with smaller size such as package, the tester is hard to avoid fatigue caused by long-time work, and the test result may be wrong or even the pin of the device may be damaged due to misoperation. In addition, the existing test fixture is formed by welding a PCB and a test seat, is only suitable for one packaged chip type semiconductor device, and is very complicated because the test fixture needs to be frequently replaced facing to devices to be tested with different packaging types.
The utility model provides a simple structure, low cost, convenient to use, efficiency of software testing are high and be favorable to avoiding the test fixture of the piece formula semiconductor device of maloperation to the above-mentioned not enough of prior art.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a simple structure, low cost, convenient to use, efficiency of software testing are high and be favorable to avoiding the test fixture of maloperation's piece formula semiconductor device.
In order to achieve the above purpose, the utility model adopts the following technical scheme: a test tool for chip semiconductor devices comprises a mother board and more than 3 daughter boards, and is characterized in that the mother board is a double-layer PCB, the front surface of the mother board is wired by a Kelvin test method, the back surface of the mother board is wired by a non-Kelvin test method, the mother board comprises a first pin base, a second pin base, a daughter board socket and an installation through hole, the daughter boards are double-layer PCBs, a station of a device to be tested and a pin assembly are arranged on the daughter boards, the station of the device to be tested comprises a groove, probes and a gland, the number and the arrangement of the probes correspond to the number and the arrangement of the pins of the device to be tested, the probes are connected with the pins of the pin assembly in a one-to-one correspondence manner, the number of the daughter board sockets corresponds to the number of the pin assembly, the daughter boards are connected with the mother board by matching of the daughter board sockets, the mother board is connected with a workbench by the installation through hole, the input end and the output end on the front surface of the mother board are connected with the first pin base, the input end of the mother board, The output end is connected with the second pin seat, and the first pin seat and the second pin seat are respectively connected with the test system through shielded cables.
Further, the top of the probe is of a concave spherical surface shape.
Further, the gland is hinged to the upper edge of the groove.
Further, the number of the sub-boards is 8.
The utility model discloses a work flow as follows: the testing tool is installed on a workbench of testing equipment, a cable is connected into the testing equipment, the testing equipment is opened after the fact that the installation of each component is not mistaken is checked, a testing program is called according to the packaging type of a chip semiconductor device to be tested, the device to be tested is placed into a corresponding testing seat, a gland is covered, and testing buttons on the testing equipment are pressed to complete testing of all parameters.
The utility model discloses a son, mother board structure have a plurality of daughter boards that are fit for different encapsulation forms device to be tested respectively on the mother board, only need during the use according to the encapsulation form of device to be tested put into it corresponding daughter board can, need not frequently to change the test seat, not only effectively avoided because of the damage of long-term plug cable to the test equipment interface, improved test data's stability moreover.
The utility model discloses a design of concave spherical surface formula is adopted at the probe top, and the pin of device under test and the good contact of probe have been guaranteed to the cooperation gland, are favorable to improving the measuring accuracy and the degree of accuracy.
The utility model discloses simple structure, low cost, convenient to use, efficiency of software testing are high and be favorable to avoiding the maloperation.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a top view of FIG. 1;
FIG. 3 is a schematic diagram of the motherboard structure of the present invention;
fig. 4 is a schematic structural diagram of the daughter board of the present invention;
FIG. 5 is a rear view of FIG. 4;
fig. 6 is a schematic diagram of the structure of the device under test station according to the present invention.
In the figure: 1-a mother board; 1.1-a first needle seat; 1.2-second needle seat; 1.3-daughter board sockets; 1.4-installing through holes; 2-daughter boards; 2.1-the device under test station; 2.1.1-grooves; 2.1.2-probe; 2.1.3-gland; 2.2-Pin Assembly.
Detailed Description
The invention will be further described with reference to the following drawings and specific examples, which should not be construed as limiting the invention.
A test tool for a chip type semiconductor device as shown in the figure comprises a mother board 1 and more than 3 daughter boards 2, wherein the mother board 1 is a double-layer PCB, the front surface of the mother board 1 is provided with Kelvin type test method wiring, the back surface of the mother board 1 is provided with non-Kelvin type test method wiring, the mother board 1 comprises a first pin base 1.1, a second pin base 1.2, a daughter board socket 1.3 and a mounting through hole 1.4, the daughter boards 2 are double-layer PCB, a tested device station 2.1 and a pin assembly 2.2 are arranged on the daughter boards 2, the tested device station 2.1 comprises a groove 2.1.1, probes 2.1.2 and a gland 2.1.3, the number and the arrangement of the probes 2.1.1 correspond to the number of the pins of the tested device, the probes 2.1.1 are correspondingly connected with the pins of the daughter board socket 2.2 one by one-to-one, the daughter boards 2 are matched with the daughter board socket 1.3 through the pin assembly 2 and connected with the pin assembly 1.3 through the mounting through the pin assembly 1.4, the input end and the output end of the front surface of the mother board 1 are connected with a first pin base 1.1, the input end and the output end of the back surface of the mother board 1 are connected with a second pin base 1.2, and the first pin base 1.1 and the second pin base 1.2 are respectively connected with a test system through shielded cables.
The preferred embodiments are: in the above solution, the top of the probe 2.1.1 is concave spherical.
The preferred embodiments are: in the above solution, the gland 2.1.3 is hinged at the upper edge of the groove 2.1.1.
The preferred embodiments are: in the above solution, the number of the daughter boards 2 is 8.
Those not described in detail in this specification are prior art to the knowledge of those skilled in the art.
Claims (5)
1. The utility model provides a test fixture of chip semiconductor device, includes mother board (1) and daughter board (2) more than 3, its characterized in that: the motherboard (1) is a double-layer PCB, the front surface of the motherboard (1) is wired by a Kelvin test method, the back surface of the motherboard (1) is wired by a non-Kelvin test method, the motherboard (1) comprises a first pin seat (1.1), a second pin seat (1.2), a daughter board socket (1.3) and an installation through hole (1.4), the daughter board (2) is a double-layer PCB, the daughter board (2) is provided with a tested device station (2.1) and a pin assembly (2.2), the tested device station (2.1) comprises a groove (2.1.1), probes (2.1.2) and a gland (2.1.3), the number and the arrangement of the probes (2.1.2) correspond to the number and the arrangement of pins of the tested device, the probes (2.1.2) are connected with the pins of the pin assembly (2.2) one by one, the number of the daughter board sockets (1.3) corresponds to the number of the pin assembly (2.2), and the daughter board (2) is connected with the motherboard (1.3) through the daughter board assembly (2) in a matching way, the mother board (1) is connected with the workbench through the mounting through hole (1.4), the input end and the output end of the front surface of the mother board (1) are connected with the first pin socket (1.1), the input end and the output end of the back surface of the mother board (1) are connected with the second pin socket (1.2), and the first pin socket (1.1) and the second pin socket (1.2) are respectively connected with the test system through shielded cables.
2. The test tool for the chip semiconductor device according to claim 1, wherein: the top of the probe (2.1.1) is of a concave spherical surface shape.
3. The test tool for the chip semiconductor device according to claim 1 or 2, wherein: the gland (2.1.3) is hinged at the upper edge of the groove (2.1.1).
4. The test tool for the chip semiconductor device according to claim 1 or 2, wherein: the number of the sub-boards (2) is 8.
5. The test tool for the chip semiconductor device according to claim 3, wherein: the number of the sub-boards (2) is 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122726807.1U CN216434274U (en) | 2021-11-09 | 2021-11-09 | Testing tool for chip type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122726807.1U CN216434274U (en) | 2021-11-09 | 2021-11-09 | Testing tool for chip type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216434274U true CN216434274U (en) | 2022-05-03 |
Family
ID=81337415
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122726807.1U Active CN216434274U (en) | 2021-11-09 | 2021-11-09 | Testing tool for chip type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216434274U (en) |
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2021
- 2021-11-09 CN CN202122726807.1U patent/CN216434274U/en active Active
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