CN216352297U - Control circuit based on level conversion chip - Google Patents
Control circuit based on level conversion chip Download PDFInfo
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- CN216352297U CN216352297U CN202122071331.2U CN202122071331U CN216352297U CN 216352297 U CN216352297 U CN 216352297U CN 202122071331 U CN202122071331 U CN 202122071331U CN 216352297 U CN216352297 U CN 216352297U
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Abstract
The utility model provides a control circuit based on a level conversion chip, which comprises the level conversion chip and is characterized by further comprising a phase inverter, wherein the input end of the phase inverter is connected with a TX signal, and the output end of the phase inverter is connected with an enabling signal end of the level conversion chip. The utility model utilizes the characteristic that the UART module keeps high level when sending the data signal TX is idle and the characteristic that the RS485 serial bus is in a high resistance state when no data exists, and controls RE and DE signals by adding an inverter at the end of outputting the TX signal. The idle level conversion chip keeps a receiving state, and the state is changed into a sending state when the output is needed, so that the automatic control of the data transmission direction of the RS485 level conversion module is realized. The GPIO control logic design can be saved, the problem of transmission errors is prevented, the transmission rate is improved, flexible adaptation and use can be realized, and hardware is not required to be changed to adapt to different modes.
Description
Technical Field
The utility model relates to the technical field of electronic circuit design, in particular to a control circuit based on a level conversion chip.
Background
RS485 (a typical serial communication standard) is a standard defined to balance the electrical characteristics of drivers and receivers in digital multipoint systems, the standard being defined by the telecommunications industry association and the electronics industry consortium. The digital communication network using the standard can effectively transmit signals under long-distance conditions and in environments with large electronic noise. RS-485 enables the configuration of connecting local networks and multi-drop communication links. RS485 adopts the balanced transmission and the differential receiving mode to realize communication: the transmitting end converts TTL level signals of the serial port into differential signals A and B for output, and the differential signals are restored into TTL (transistor transistor logic) level signals at the receiving end after cable transmission. Because the transmission line usually uses twisted pair, and is differential transmission, it has strong ability of resisting common mode interference, and the sensitivity of the bus transceiver is very high, and can detect voltage as low as 200 mv. The transmitted signal can be recovered even out of kilometers. The maximum communication distance of the RS485 is about 1219m, the maximum transmission rate is 10mb/s, the transmission rate is inversely proportional to the transmission distance, the maximum communication distance can be reached only at the transmission rate of 10kb/s, and a 485 repeater is required if a longer distance needs to be transmitted. RS485 adopts a half-duplex working mode to support multipoint data communication. The RS485 bus network topology generally adopts a bus type structure with matched terminals. That is, a bus is adopted to connect all the nodes in series, and the ring-shaped or star-shaped network is not supported. If a star configuration is desired, 485 repeaters or 485 hubs must be used. The RS485 bus generally supports 32 nodes at maximum, and can reach 128 or 256 nodes if a special 485 chip is used, and can support 400 nodes at maximum.
RE and DE are RS485 chip internal receive enable signal (active low level) and transmit enable signal (active high level), and can control the high and low level of pin to control the receiving and transmitting data through GPIO (General-purpose input/output control pin). However, the GPIO control has the problem of time delay, which can cause transmission errors and limit the transmission rate.
SUMMERY OF THE UTILITY MODEL
The utility model provides a control circuit based on a level conversion chip, which is used for solving the problems of transmission errors and limitation of transmission rate caused by time delay existing in the conventional GPIO control.
In order to achieve the purpose, the utility model adopts the following technical scheme:
the utility model relates to a control circuit based on a level conversion chip, which comprises the level conversion chip and a phase inverter, wherein the input end of the phase inverter is connected with a TX signal, and the output end of the phase inverter is connected with an enabling signal end of the level conversion chip.
Furthermore, the control circuit further comprises a diode D, wherein the anode of the diode D is connected with the input end of the inverter, and the cathode of the diode D is connected with the TX signal.
Furthermore, the control circuit further comprises an RC circuit, two ends of a resistor R1 in the RC circuit are respectively connected with the input end of the inverter and the TX signal, and two ends of a capacitor C are respectively connected with the input end of the inverter and the ground.
Furthermore, the control circuit further comprises a pull-up resistor R3, a resistor R4 and a resistor R5, two ends of the resistor R3 are respectively connected with the power supply and an RX signal, two ends of the resistor R4 are respectively connected with the power supply and the output end of the inverter, and two ends of the resistor R5 are respectively connected with the power supply and the A port of the level conversion chip.
Further, the control circuit further comprises a pull-down resistor R7, and two ends of the resistor R7 are respectively connected with the B port of the level conversion chip and the ground.
Further, the model of the inverter is SN74LVC1G06 DCKR.
Further, the level conversion chip is a conversion chip for converting UART into RS 485.
The effects provided in the contents of the present invention are only the effects of the embodiments, not all the effects of the present invention, and one of the above technical solutions has the following advantages or advantageous effects:
the utility model utilizes the characteristic that the UART module keeps high level when sending the data signal TX is idle and the characteristic that the RS485 serial bus is in a high resistance state when no data exists, and controls RE and DE signals by adding an inverter at the end of outputting the TX signal. The idle level conversion chip keeps a receiving state, and the state is changed into a sending state when the output is needed, so that the automatic control of the data transmission direction of the RS485 level conversion module is realized. The GPIO control logic design can be saved, the problem of transmission errors is prevented, the transmission rate is improved, flexible adaptation and use can be realized, and hardware is not required to be changed to adapt to different modes.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
Fig. 1 is a block diagram of an embodiment of the control circuit of the present invention.
Detailed Description
In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the utility model. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the utility model.
As shown in FIG. 1, the control circuit based on the level shift chip of the present invention includes a level shift chip and an inverter, wherein an input terminal of the inverter is connected to a TX signal, and an output terminal of the inverter is connected to an enable signal terminal of the level shift chip. The model of the inverter is SN74LVC1G06 DCKR. The level conversion chip is a conversion chip for converting UART into RS 485.
A Schottky diode D is added at the input end of the phase inverter, the anode of the diode D is connected with the input end of the phase inverter, and the cathode of the diode D is connected with a TX signal. A pull-up resistor R5 is added at a of the level shifting chip. Port B adds pull-down resistor R7.
The control circuit further comprises an RC circuit for filtering, two ends of a resistor R1 in the RC circuit are respectively connected with the input end of the inverter and the TX signal, and two ends of a capacitor C are respectively connected with the input end of the inverter and the ground.
The control circuit further comprises a pull-up resistor R3 and a resistor R4, wherein two ends of the resistor R3 are respectively connected with the power supply and an RX signal, and two ends of the resistor R4 are respectively connected with the power supply and the output end of the inverter.
The control circuit further comprises a resistor R2 and a resistor R6, wherein the resistor R2 is respectively connected with a power supply and a Vcc end of the inverter and is a power supply enabling protection resistor; the resistors R6 are respectively connected to the A, B ports of the electrical frequency conversion chips, and serve as load resistors.
The working principle of the control circuit of the utility model is as follows: the output of the phase inverter Y pin is influenced by the input of the phase inverter A pin, and when the input of A is high level, the output of Y is low level; when a is low, Y outputs a high impedance state, RE and DE are high because of the pull-up resistance. The schottky diode D can rapidly complete the switching of the high and low levels of the a terminal, thereby minimizing the influence of delay and generating no error signal.
When the serial port is idle, the RX and TX signals are high level, at the same time, RE and DE are low level, the level conversion chip keeps the receiving state, and if external data input exists, the receiving state can be directly received. When data is transmitted, a TX signal has high-low level pulses, the initial bit is low level, when the initial bit is low level, RE and DE are high level, the level conversion chip is switched to a transmitting state, output A is 0, and B is 1; when the level is high, RE and DE are low, and the level conversion module is switched to the receiving state, since A, B has a pull-up and pull-down resistor, the output a is equal to 1, and B is equal to 0, which is equal to the UART signal being transmitted high.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.
Claims (5)
1. A control circuit based on a level conversion chip comprises the level conversion chip and is characterized by further comprising a phase inverter, wherein the input end of the phase inverter is connected with a TX signal, and the output end of the phase inverter is connected with an enabling signal end of the level conversion chip; the control circuit further comprises a diode D, wherein the anode of the diode D is connected with the input end of the inverter, and the cathode of the diode D is connected with the TX signal;
the control circuit further comprises a pull-up resistor R3, a resistor R4 and a resistor R5, two ends of the resistor R3 are respectively connected with a power supply and an RX signal, two ends of the resistor R4 are respectively connected with the power supply and the output end of the phase inverter, and two ends of the resistor R5 are respectively connected with the power supply and the A port of the level conversion chip.
2. The control circuit based on the level shift chip as claimed in claim 1, wherein the control circuit further comprises an RC circuit, wherein two ends of the resistor R1 are respectively connected to the input terminal of the inverter and the TX signal, and two ends of the capacitor C are respectively connected to the input terminal of the inverter and the ground.
3. The control circuit based on the level shift chip as claimed in claim 1, wherein the control circuit further comprises a pull-down resistor R7, and two ends of the resistor R7 are respectively connected to the B port of the level shift chip and ground.
4. The control circuit based on the level conversion chip as claimed in claim 1, wherein the inverter has a model number SN74LVC1G06 DCKR.
5. The control circuit based on the level shift chip as claimed in any one of claims 1 to 4, wherein the level shift chip is a conversion chip for converting UART to RS 485.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122071331.2U CN216352297U (en) | 2021-08-30 | 2021-08-30 | Control circuit based on level conversion chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122071331.2U CN216352297U (en) | 2021-08-30 | 2021-08-30 | Control circuit based on level conversion chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216352297U true CN216352297U (en) | 2022-04-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122071331.2U Active CN216352297U (en) | 2021-08-30 | 2021-08-30 | Control circuit based on level conversion chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216352297U (en) |
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2021
- 2021-08-30 CN CN202122071331.2U patent/CN216352297U/en active Active
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