CN216313071U - Level conversion driving circuit for data output port of LED color lamp string - Google Patents

Abstract

One embodiment of the utility model discloses a level conversion driving circuit for a data output port of a string of LED colored lamps, which comprises: the low-voltage input signal is converted into a high-voltage data signal through a current reference module, a floating power module, a first level conversion module, a second level conversion module, a first gate driving module, a second gate driving module, a combined control module, a first PMOS (P-channel metal oxide semiconductor) tube and a first NMOS (N-channel metal oxide semiconductor) tube, and then the high-voltage data signal is output. The circuit meets the requirements of the high-voltage LED color lamp string data output port on speed, pulse width distortion and transmission delay at ns level, can be applied to data forwarding of the high-voltage LED color lamp string cascade data output port, and has wide application prospect.

Description

Level conversion driving circuit for data output port of LED color lamp string

Technical Field

The present invention relates to the field of integrated circuits. And more particularly, to a level shift driving circuit for a data output port of a string of LED color lamps.

Background

In sub-micron CMOS integrated circuits, the logic level Vio at the chip pin is typically much higher than the core voltage Vcore inside the integrated circuit for compatible IC logic signals from the system board peripheral power supply. In order to improve the integration level, the integrated circuit core circuit is designed and manufactured by adopting a minimum-size low-threshold MOS tube, and the withstand voltage of the integrated circuit core circuit is also very low. The input/output IO circuit of the integrated circuit is designed and manufactured by adopting a large-size high-threshold MOS tube, and the high withstand voltage of the integrated circuit can meet the requirement of system-level interconnection. Logic signals of the CMOS logic gate constructed by the low-threshold MOS tube cannot correctly control the high-threshold CMOS logic gate, and when the high-voltage logic gate is directly driven, the output logic of the high-voltage logic gate is wrong, and electric leakage is caused. Therefore, a low voltage level to high voltage logic level conversion circuit must be used between the low logic level Vcore and the high logic level Vio to achieve a safe and reliable interconnection.

SUMMERY OF THE UTILITY MODEL

In view of the above, a first embodiment of the present invention provides a level shift driving circuit for a data output port of a string of LED color lamps, including:

a current reference module, a floating power module, a first level conversion module, a second level conversion module, a first gate driving module, a second gate driving module, a combination control module, a first PMOS tube and a first NMOS tube,

the combination control module is used for generating a control signal for controlling the first PMOS tube to be opened or closed according to a low-voltage input signal and a control signal for opening or closing the first NMOS tube generated by the second gate driving module;

the first level conversion module is used for converting a control signal for controlling the opening or closing of the first PMOS tube into a high-voltage pulse signal;

the first gate driving module is used for outputting a high-voltage gate pulse signal according to the high-voltage pulse signal and providing a driving voltage for the first PMOS tube, wherein the floating power supply module receives a reference current generated by the current reference module and outputs a floating ground voltage, and the floating ground voltage is processed and then used as a low level of the first gate driving module;

the second level conversion module is used for converting the high-voltage grid pulse signal into a low-voltage pulse signal;

the second gate driving module is used for generating a control signal for controlling the first NMOS to be turned on or turned off according to the low-voltage input signal and the low-voltage pulse signal;

the first PMOS tube is turned on or turned off according to the driving voltage generated by the first gate driving module;

the first NMOS tube is turned on or turned off according to a control signal which is generated by the second gate driving module and used for driving the PMOS to be turned on or turned off;

and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and outputs a high-voltage data signal.

In one embodiment, the current reference circuit comprises: a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a first triode, a second triode, a first resistor and a first current mirror module,

the source electrode of the second PMOS tube is connected with a low-level power supply, the drain electrode of the second PMOS tube is connected with the source electrode of the fourth PMOS tube, the grid electrode of the second PMOS tube is respectively connected with the grid electrode of the third PMOS tube, the drain electrode of the fourth PMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the tenth PMOS tube,

the source electrode of the third PMOS tube is connected with a low-level power supply, the drain electrode of the third PMOS tube is connected with the source electrode of the fifth PMOS tube,

the drain electrode of the fourth PMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the fourth PMOS tube is respectively connected with the grid electrode of the fifth PMOS tube, the grid electrode of the seventh PMOS tube, the grid electrode and the drain electrode of the eighth PMOS tube, the drain electrode of the seventh NMOS tube and the grid electrode of the eleventh PMOS tube,

the drain electrode of the fifth PMOS tube is respectively connected with the drain electrode and the grid electrode of the third NMOS tube,

the source electrode of the sixth PMOS tube is connected with a low-level power supply, the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube,

the drain electrode of the seventh PMOS tube is connected with the drain electrode of the fourth NMOS tube,

the source electrode of the eighth PMOS tube is connected with a low-level power supply, the drain electrode of the eighth PMOS tube is connected with the drain electrode of the fifth NMOS tube,

the source electrode of the ninth PMOS tube is connected with a low-level power supply, the drain electrode of the ninth PMOS tube is connected with the drain electrode of the sixth NMOS tube, the grid electrode of the ninth PMOS tube is connected with the ground wire,

the source electrode of the tenth PMOS tube is connected with a low-level power supply, the drain electrode of the tenth PMOS tube is connected with the source electrode of the eleventh PMOS tube, the grid electrode of the tenth PMOS tube is connected with the drain electrode of the eighth NMOS tube,

the drain electrode of the eleventh PMOS tube is connected with the first end of the first current mirror module,

the source electrode of the second NMOS tube is connected with the emitter electrode of the first triode through the first resistor, the grid electrode of the second NMOS tube is connected with the grid electrode of the third NMOS tube,

the source electrode of the third NMOS tube is connected with the emitter electrode of the second triode,

the drain electrode of the fourth NMOS tube is respectively connected with the grid electrode of the fourth NMOS tube and the grid electrode of the sixth NMOS tube, the source electrode of the fourth NMOS tube is connected with the ground wire, the grid electrode of the fourth NMOS tube is connected with the grid electrode of the fifth NMOS tube,

the source electrode of the fifth NMOS tube is connected with the ground wire,

the drain electrode of the sixth NMOS tube is respectively connected with the grid electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube, the source electrode is grounded,

the source electrode of the seventh NMOS tube is connected with the ground wire, the source electrode of the eighth NMOS tube is connected with the ground wire,

the collector of the first triode is respectively connected with the base of the first triode, the collector of the second triode and the ground wire, the base is connected with the base of the second triode,

and the third end of the first current mirror module outputs reference current, and the second end and the fourth end of the first current mirror module are connected with a ground wire.

In a specific embodiment, the floating power module includes:

a ninth NMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a triode module, a second resistor and a third resistor, wherein,

the grid electrode of the ninth NMOS tube is connected with a low-level power supply, the source electrode of the ninth NMOS tube receives the reference current generated by the current reference module, the drain electrode of the ninth NMOS tube is respectively connected with the first end of the triode module and the grid electrode of the thirteenth PMOS tube,

the grid electrode of the twelfth PMOS tube is respectively connected with the drain electrode of the twelfth PMOS tube and the second end of the triode module, the source electrode of the twelfth PMOS tube is connected with the first end of the third resistor,

the drain electrode of the thirteenth PMOS tube is connected with the ground wire, the source electrode of the thirteenth PMOS tube is connected with the first end of the second resistor and outputs a floating ground voltage,

and the second ends of the third resistors are respectively connected with the high-level power supply and the second ends of the second resistors.

In one embodiment, the first level shift circuit includes:

a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a second current mirror module, a first phase inverter and a first current source,

the source electrode of the fourteenth PMOS tube is connected with a high-level power supply, the drain electrode of the fourteenth PMOS tube is respectively connected with the grid electrode of the fourteenth PMOS tube, the drain electrode of the tenth NMOS tube and the grid electrode of the seventeenth PMOS tube,

the source electrode of the fifteenth PMOS tube is connected with a high-level power supply, the drain electrode of the fifteenth PMOS tube is respectively connected with the grid electrode of the fifteenth PMOS tube and the drain electrode of the eleventh NMOS tube, the grid electrode of the fifteenth PMOS tube is connected with the grid electrode of the sixteenth PMOS tube,

the source electrode of the sixteenth PMOS tube is connected with a high-level power supply, the drain electrode of the sixteenth PMOS tube is connected with the first end of the second current mirror,

the source electrode of the seventeenth PMOS tube is connected with a high-level power supply, the drain electrode of the seventeenth PMOS tube is connected with the third end of the second current mirror circuit to output a high-voltage pulse signal,

the grid electrode of the tenth NMOS tube is connected with the input end of the first phase inverter, is connected with the output end of the combined control module and receives a control signal for controlling the opening or closing of the first PMOS tube, the source electrode of the tenth NMOS tube is connected with the source electrode of the eleventh NMOS tube,

the grid electrode of the eleventh NMOS tube is connected with the output end of the first reverser,

the first end of the first current source is connected with the ground wire, the second end of the first current source is respectively connected with the source electrode of the tenth NMOS tube and the source electrode of the eleventh NMOS tube,

the second end and the fourth end of the second current mirror module receive the floating ground voltage output by the floating power supply module.

In a specific embodiment, the second level shift module includes: a second current source, a third current source, an eighteenth PMOS tube, a second inverter and a third current mirror module, wherein,

the first end of the second current source is connected with a high-level power supply, the second end of the second current source is connected with the source electrode of the eighteenth PMOS tube,

the grid electrode of the eighteenth PMOS tube receives the high-voltage grid pulse signal of the first PMOS tube, the drain electrode of the eighteenth PMOS tube is connected with the first end of the third current mirror circuit,

and the second end and the fourth end of the third current mirror module are connected with a ground wire, and the third end of the third current mirror module is connected with the input end of the second reverser.

The input end of the second inverter is connected with the low-level power supply through a third current source, and the output end of the second inverter outputs the control signal for controlling the first NMOS to be turned on or turned off.

In one embodiment, the combination control module includes: a third inverter, a fourth inverter and a first OR gate,

the input end of the third inverter receives a control signal for turning on or off the first NMOS, the output end of the third inverter is connected with the input end of the fourth inverter,

and a first input end of the first or gate is connected with an output end of the fourth inverter, a second input end of the first or gate receives a low-voltage input signal, and an output end of the first or gate outputs an input control signal for controlling the first level conversion module.

In one embodiment, the first gate driving module includes a first driving buffer and a second driving buffer, wherein,

a first terminal of the first driving buffer is connected with a high-level power supply, a second terminal receives the high-voltage pulse signal, a third terminal receives the floating ground voltage, a fourth terminal is connected with a second terminal of the second driving buffer,

and the first end of the second driving buffer is connected with a high-level power supply, the third end of the second driving buffer receives the floating ground voltage, and the fourth end of the second driving buffer outputs the high-voltage grid pulse signal.

In one embodiment, the second gate driving module includes:

a fifth inverter, a first AND gate, a third driving buffer, and a fourth driving buffer, wherein,

the first end of the first AND gate receives the low-voltage pulse signal through a fifth inverter, the second end of the first AND gate receives a low-voltage input signal, the output end of the first AND gate is connected with the second end of the third driving buffer,

the first end of the third driving buffer is connected with the low-level power supply, the third end is connected with the ground wire, the fourth end is connected with the second end of the fourth driving buffer,

and the first end of the fourth driving buffer is connected with the low-level power supply, the third end of the fourth driving buffer is connected with the ground wire, and the fourth end of the fourth driving buffer outputs the control signal for controlling the first NMOS to be turned on or turned off.

In one embodiment, the triode module comprises N triodes,

the base electrode of the nth triode is connected with the self collector electrode, the emitter electrode is connected with the collector electrode of the (N + 1) th triode, wherein N is more than or equal to 2 and less than or equal to N-1,

and the collector electrode of the 1 st triode is connected with the drain electrode of the twelfth PMOS tube, and the emitter electrode of the Nth triode is connected with the drain electrode of the ninth NMOS tube.

In one embodiment, the first driving buffer includes: an eighteenth PMOS transistor MIP4 and a twelfth NMOS transistor MIN0,

and the grid electrode of the eighteenth PMOS tube is connected with the grid electrode of the twelfth NMOS tube and receives the high-voltage pulse signal, the source electrode of the eighteenth PMOS tube is connected with the high-level power supply, and the drain electrode of the eighteenth PMOS tube is connected with the drain electrode of the twelfth NMOS tube and is connected with the second end of the second driving buffer.

The utility model has the following beneficial effects:

the level conversion driving circuit for the data output port of the LED color lamp string can realize level conversion from low-level logic signal input to high-level logic signal output, meets the requirements of the data output port of the high-voltage LED color lamp string on speed, pulse width distortion and transmission delay at ns level, can be applied to data forwarding of the cascaded data output port of the high-voltage LED color lamp string, and has wide application prospect.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 shows a high-voltage low-voltage LED color lamp string application circuit according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a level shift driving circuit for a data output port of a string of LED color lamps according to an embodiment of the present invention.

FIG. 3 shows a schematic diagram of a current reference module according to one embodiment of the utility model.

FIG. 4 shows a schematic diagram of a floating power module according to one embodiment of the utility model.

FIG. 5 illustrates a first level shifting block according to one embodiment of the utility model.

FIG. 6 illustrates a second level shifting block according to one embodiment of the utility model.

FIG. 7 shows a schematic diagram of a combined control module, according to one embodiment of the utility model.

Fig. 8 shows a schematic diagram of a first gate driving module according to an embodiment of the utility model.

Fig. 9 shows a schematic diagram of a second gate driving module according to an embodiment of the utility model.

Detailed Description

In order to make the technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in fig. 1, the low-voltage 5V LED colored lamp string application circuit adopts a single-wire return-to-zero code signal cascade communication mode, a power supply and a ground wire are connected in parallel, and three-channel LEDs are respectively connected to a 5V power supply. The microcontroller MCU is usually used as the main controller of the LED color lamp string. In a specific driving example, the LED colored lamp string main controller sends a string single-wire return-to-zero control code to a first driving chip in the string in a data stream form, and then, after the first driving chip detects and latches bits required by the driving number belonging to its own LED, the first driving chip transfers a subsequent data stream after being shaped and enhanced to a next driving chip through its own signal output terminal DO, and after the next driving chip detects and absorbs the bits required by the driving number belonging to its own LED, the subsequent data stream after being shaped and enhanced is transferred to a next driving chip through its own signal output terminal DO, and so on.

As shown in fig. 1, the 12V high-voltage LED colored lamp string application circuit adopts a single-wire return-to-zero code signal cascade communication mode, a power supply and a ground wire are connected in parallel, and a three-channel LED is connected to a 12V high-voltage power supply in series. In a specific driving example, the LED colored lamp string main controller sends a string single-wire return-to-zero control code to a first driving chip in the string in a data stream form, the first driving chip detects and latches bits required for the number of LEDs belonging to itself, shapes and enhances subsequent data streams, and forwards the shaped and enhanced data streams to a next driving chip through its signal output terminal DO, and finally, the next driving chip detects and absorbs the bits required for the number of LEDs belonging to itself, shapes and enhances subsequent data streams, and forwards the shaped and enhanced data streams to a next driving chip through its signal output terminal DO, and so on.

In the cascade application of the high-voltage LED colored lamp string, the accuracy of data forwarding influences the use of the whole LED lamp string, and in order to improve the accuracy of data forwarding, the utility model provides a level conversion driving circuit for a data output port of the LED colored lamp string.

As shown in fig. 2, a level shift driving circuit for a data output port of a string of LED color lamps includes:

the current reference module PTAT current, the floating power module FGND, the first level conversion module LV to HV shift, the second level conversion module HV to LV shift, the first gate driving module Driver P, the second gate driving module Driver N, the combined control module LV logic, the first PMOS tube and the first NMOS tube, wherein,

the combination control module is used for generating a control signal LVDRP for controlling the first PMOS transistor to be switched on or switched off according to a low-voltage input signal IN and a control signal DRN which is generated by the second gate driving module and used for switching on or switching off the first NMOS transistor;

the first level conversion module is used for converting a control signal LVDRP for controlling the first PMOS tube to be opened or closed into a high-voltage pulse signal HVDRP,

the first gate driving module is used for outputting a high-voltage gate pulse signal DRP according to the high-voltage pulse signal and providing a driving voltage for the first PMOS transistor, wherein the floating power supply module receives a reference current IREF generated by the current reference module and outputs a floating ground voltage FGND, and the floating ground voltage FGND is processed and then serves as a low level of the first gate driving module;

the second level conversion module is used for converting the high-voltage grid pulse signal into a low-voltage pulse signal LVDRP 2;

the second gate driving module is used for generating a control signal DRN for controlling the first NMOS to be turned on or turned off according to the low-voltage input signal and the low-voltage pulse signal;

the first PMOS tube is turned on or turned off according to the driving voltage generated by the first gate driving module;

the first NMOS tube is turned on or off according to a control signal which is generated by the second gate driving module and used for driving the PMOS to be turned on or turned off,

and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and outputs a high-voltage data signal.

In one embodiment, as shown in fig. 3, the current reference circuit PTAT current includes: a second PMOS transistor MP0, a third PMOS transistor MP1, a fourth PMOS transistor MP2, a fifth PMOS transistor MP3, a sixth PMOS transistor MP4, a seventh PMOS transistor MP5, an eighth PMOS transistor MP6, a ninth PMOS transistor MP7, a tenth PMOS transistor MP8, an eleventh PMOS transistor MP9, a second NMOS transistor MN0, a third NMOS transistor MN1, a fourth NMOS transistor MN2, a fifth NMOS transistor MN3, a sixth NMOS transistor MN4, a seventh NMOS transistor MN5, an eighth NMOS transistor MN6, a first triode QP0, a second triode QP1, a first resistor R0, and a first current mirror module, wherein,

the source electrode of the second PMOS tube is connected with a low-level power supply, the drain electrode of the second PMOS tube is connected with the source electrode of the fourth PMOS tube, the grid electrode of the second PMOS tube is respectively connected with the grid electrode of the third PMOS tube, the drain electrode of the fourth POMS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the tenth PMOS tube,

the source electrode of the third PMOS tube is connected with a low-level power supply LVDD, the drain electrode of the third PMOS tube is connected with the source electrode of the fifth PMOS tube,

the drain electrode of the fourth POMS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the fourth POMS tube is respectively connected with the grid electrode of the fifth PMOS tube, the grid electrode of the seventh PMOS tube, the grid electrode and the drain electrode of the eighth PMOS tube, the drain electrode of the seventh NMOS tube and the grid electrode of the eleventh PMOS tube,

the drain electrode of the fifth PMOS tube is respectively connected with the drain electrode and the grid electrode of the third NMOS tube,

the source electrode of the sixth PMOS tube is connected with a low-level power supply, the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube,

the drain electrode of the seventh PMOS tube is connected with the drain electrode of the fourth NMOS tube,

the source electrode of the eighth PMOS tube is connected with a low-level power supply, the drain electrode of the eighth PMOS tube is connected with the drain electrode of the fifth NMOS tube,

the source electrode of the ninth PMOS tube is connected with a low-level power supply, the drain electrode of the ninth PMOS tube is connected with the drain electrode of the sixth NMOS tube, the grid electrode of the ninth PMOS tube is connected with the ground wire,

the source electrode of the tenth PMOS tube is connected with a low-level power supply, the drain electrode of the tenth PMOS tube is connected with the source electrode of the eleventh PMOS tube, the grid electrode of the tenth PMOS tube is connected with the drain electrode of the eighth NMOS tube,

the drain electrode of the eleventh PMOS tube is connected with the first end of the first current mirror module,

the source electrode of the second NMOS tube is connected with the emitter electrode of the first triode through the first resistor, the grid electrode of the second NMOS tube is connected with the grid electrode of the third NMOS tube,

the source electrode of the third NMOS tube is connected with the emitter electrode of the second triode,

the drain electrode of the fourth NMOS tube is respectively connected with the grid electrode of the fourth NMOS tube and the grid electrode of the sixth NMOS tube, the source electrode of the fourth NMOS tube is connected with the ground wire, the grid electrode of the fourth NMOS tube is connected with the grid electrode of the fifth NMOS tube,

the source electrode of the fifth NMOS tube is connected with the ground wire,

the drain electrode of the sixth NMOS tube is respectively connected with the grid electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube, the source electrode is grounded,

the source electrode of the seventh NMOS tube is connected with the ground wire, the source electrode of the eighth NMOS tube is connected with the ground wire,

the collector of the first triode is respectively connected with the base of the first triode, the collector of the second triode and the ground wire, the base is connected with the base of the second triode,

and the third end of the first current mirror module outputs reference current, and the second end and the fourth end of the first current mirror module are connected with a ground wire.

The first current mirror module includes: a first current mirror three-terminal device and a second current mirror three-terminal device,

the first end of the three-terminal device of the first current mirror is respectively connected with the second end of the three-terminal device of the first current mirror and the first end of the three-terminal device of the second current mirror, the second end of the three-terminal device of the first current mirror is connected with the drain electrode of the ninth PMOS tube, the third end of the three-terminal device of the first current mirror is connected with the ground wire,

and the second end of the three-end device of the second current mirror outputs reference current, and the third end of the three-end device is connected with the ground wire.

More preferably, the first three-terminal current mirror device and the second three-terminal current mirror device are NMOS transistors.

In another embodiment, a method of generating a reference current IREF includes:

the reference current IREF is generated using a current reference circuit as shown in figure 3,

the reference current IREF is

Wherein N is the mirror ratio of the first current mirror circuit,

according to

It can be seen that m (Q) is the ratio of the areas of QP0 and QP1, based on

It can be seen that m (P) is the ratio of W/L of MP1 to MP 0.

Since Δ VBE is proportional to absolute temperature, the temperature coefficient of the integrated resistor is much smaller than that of Δ VBE, Δ VBE/R0 still has a positive temperature coefficient, and so on, IREF — N × Δ VBE/R0 also still has a positive temperature coefficient.

In one embodiment, as shown in fig. 4, the floating power module includes:

a ninth NMOS transistor MHN5, a twelfth PMOS transistor NHP0, a thirteenth PMOS transistor MHP1, a triode module, a second resistor R2, and a third resistor R3, wherein,

the grid electrode of the ninth NMOS tube is connected with a low-level power supply, the source electrode of the ninth NMOS tube receives the reference current generated by the current reference module, the drain electrode of the ninth NMOS tube is respectively connected with the first end of the triode module and the grid electrode of the thirteenth PMOS tube,

the grid electrode of the twelfth PMOS tube is respectively connected with the drain electrode of the twelfth PMOS tube and the second end of the triode module, the source electrode of the twelfth PMOS tube is connected with the first end of the third resistor,

the drain electrode of the thirteenth PMOS tube is connected with the ground wire, the source electrode of the thirteenth PMOS tube is connected with the first end of the second resistor and outputs a floating ground voltage,

a second end of the third resistor is connected to a high-level power source HVCC and a second end of the second resistor, respectively.

The triode module comprises N triodes,

the base electrode of the nth triode is connected with the self collector electrode, the emitter electrode is connected with the collector electrode of the (N + 1) th triode, wherein N is more than or equal to 2 and less than or equal to N-1,

and the collector electrode of the 1 st triode is connected with the drain electrode of the twelfth PMOS tube, and the emitter electrode of the Nth triode is connected with the drain electrode of the ninth NMOS tube.

More preferably, n is 4.

In another embodiment, when n is 4, a method of generating a temperature independent floating ground power supply, comprising: the ninth NMOS tube receives the reference current IREF and makes the reference current IREF act on a twelfth PMOS tube NHP0, a thirteenth PMOS tube MHP1 and R0 of the triode module, so that the voltage V _ MHP1g of the gate node of the MHP1 is HVCC-IREF multiplied by R1-VGS _ MHP0-4VBE, and further the voltage of a node FGND is obtained,

FGND＝HVCC-IREF×R2-VGS_MHP0-4VBE+VGS_MHP1，

by adjusting the size of MHP0, MHP1, VGS _ MHP0 can be made approximately equal to VGS _ MHP1, one can obtain:

FGND＝HVCC-(IREF*R2+4VBE)

given that IREF is proportional to absolute temperature and VBE is inversely proportional to absolute temperature, and assuming HVCC is temperature independent, IREF R2+4VBE can be obtained by appropriate weighting of IREF and VBE independent of temperature, and FGND independent of temperature.

The floating ground voltage FGND is equal to HVCC minus four times of band gap voltage, and is used as the low level of the gate drive circuit of PMOS

In one embodiment, as shown in fig. 5, the first level shift circuit includes:

a fourteenth PMOS transistor MIP0, a fifteenth PMOS transistor MIP1, a sixteenth PMOS transistor MIP2, a seventeenth PMOS transistor MIP3, a tenth NMOS transistor MHN0, an eleventh NMOS transistor MHN1, a second current mirror module, a first inverter U5-1 and a first current source I0, wherein,

the source electrode of the fourteenth PMOS tube is connected with a high-level power supply, the drain electrode of the fourteenth PMOS tube is respectively connected with the grid electrode of the fourteenth PMOS tube, the drain electrode of the tenth NMOS tube and the grid electrode of the seventeenth PMOS tube,

the source electrode of the fifteenth PMOS tube is connected with a high-level power supply, the drain electrode of the fifteenth PMOS tube is respectively connected with the grid electrode of the fifteenth PMOS tube and the drain electrode of the eleventh NMOS tube, the grid electrode of the fifteenth PMOS tube is connected with the grid electrode of the sixteenth PMOS tube,

the source electrode of the sixteenth PMOS tube is connected with a high-level power supply, the drain electrode of the sixteenth PMOS tube is connected with the first end of the second current mirror,

the source electrode of the seventeenth PMOS tube is connected with a high-level power supply, the drain electrode of the seventeenth PMOS tube is connected with the third end of the second current mirror circuit to output a high-voltage pulse signal,

the grid electrode of the tenth NMOS tube is connected with the input end of the first phase inverter, is connected with the output end of the combined control module and receives a control signal for controlling the opening or closing of the first PMOS tube, the source electrode of the tenth NMOS tube is connected with the source electrode of the eleventh NMOS tube,

the grid electrode of the eleventh NMOS tube is connected with the output end of the first reverser,

the first end of the first current source is connected with the ground wire, the second end of the first current source is respectively connected with the source electrode of the tenth NMOS tube and the source electrode of the eleventh NMOS tube,

the second end and the fourth end of the second current mirror module receive the floating ground voltage output by the floating power supply module.

The second current mirror module includes: NMOS MIN4 and NMOS MIN 5.

It should be noted that the principle and the working flow of the second current mirror module and the first current mirror module provided in this embodiment are similar, and reference may be made to the above description for related parts, which are not described herein again.

In another embodiment, performing a level shift from a low voltage to a high voltage includes:

when the control signal LVDRP for controlling the first PMOS tube to be switched on or switched off is at a low level, the MHN0 of the tenth NMOS tube is switched off, the MIP0 of the fourteenth PMOS tube has no current, the MHN1 of the eleventh NMOS tube works, the I0 completely flows into MHN1 and MIP1 branches, the MIP2 mirrors the current of the MIP1, the current of the MIP2 flows into MIN4, and the MHN5 mirrors the current of MIN4, as the MIP0 has no current flowing, the grid-source voltage difference Vgs is close to zero, the Vgs of the MIP3 is also close to zero and is in a high-resistance state, and when the current flows in the MIN4, the HVDRP output is infinitely close to FGND; when LVDRP is LVDD, MHN0 is conducted, MHN1 is closed, I0 flows into MIP0 completely, MIP3 mirrors the current of MIP0, MHN1 is closed, MIN5 has no current and is in a high-resistance state, HVDRP is output to be infinitely close to HVCC, and according to the principle, level conversion from low-voltage pulse signal LVDRP to high-voltage pulse signal HVDRP is completed.

In one embodiment, as shown in fig. 6, the second level shift module includes: a second current source I1, a third current source I2, an eighteenth PMOS transistor MHP2, a second inverter U6-1 and a third current mirror module, wherein,

the first end of the second current source is connected with a high-level power supply, the second end of the second current source is connected with the source electrode of the eighteenth PMOS tube,

the grid electrode of the eighteenth PMOS tube receives the high-voltage grid pulse signal of the first PMOS tube, the drain electrode of the eighteenth PMOS tube is connected with the first end of the third current mirror circuit,

and the second end and the fourth end of the third current mirror module are connected with a ground wire, and the third end of the third current mirror module is connected with the input end of the second reverser.

The input end of the second inverter is connected with the low-level power supply through a third current source, and the output end of the second inverter outputs the control signal for controlling the first NMOS to be turned on or turned off.

It should be noted that the principle and the working flow of the third current mirror module provided in this embodiment are similar to those of the first current mirror module, and reference may be made to the above description for relevant points, which are not described herein again.

In another embodiment, the performing the level conversion of the high voltage pulse signal DRP to the low voltage pulse signal LVDRP2 includes:

when DRP is HVCC, MHP0 is turned off, I1 current cannot flow into MN0, MN1 is turned off, and a high impedance state is presented, at this time, I2 can pull up the drain node of MN1 to LVDD, and output LVDRP2 is GND; when DRP is FGND, MHP0 is turned on, I1 current flows through MN0, MN1 mirrors MN0 current, and when compared with I2, the drain voltage of MN1 is lower than the threshold of the gate of the inverter in the next stage, and the output LVDRP2 is LVDD. Based on this principle, the level conversion of the high-voltage pulse signal DRP to the low-voltage pulse signal LVDRP2 is completed.

In one particular embodiment, as shown in FIG. 7, the combination control module includes a third inverter U7-1, a fourth inverter U7-2, and a first OR gate U7-3,

the input end of the third inverter receives a control signal for turning on or off the first NMOS, the output end of the third inverter is connected with the input end of the fourth inverter,

and a first input end of the first or gate is connected with an output end of the fourth inverter, a second input end of the first or gate receives a low-voltage input signal, and an output end of the first or gate outputs an input control signal for controlling the first level conversion module.

In another embodiment, outputting the control signal LVDRP for controlling the first PMOS transistor to be turned on or off includes:

when IN is GND, DRN is GND, LVDRP can be GND, DRP shown IN fig. 7 can be FGND, PMOS pull-up OUT, and DO is HVCC.

In one embodiment, as shown in fig. 8, the first gate driving module includes a first driving buffer and a second driving buffer, wherein,

a first terminal of the first driving buffer is connected with a high-level power supply, a second terminal receives the high-voltage pulse signal, a third terminal receives the floating ground voltage, a fourth terminal is connected with a second terminal of the second driving buffer,

and the first end of the second driving buffer is connected with a high-level power supply, the third end of the second driving buffer receives the floating ground voltage, and the fourth end of the second driving buffer outputs the high-voltage grid pulse signal.

The first driving buffer includes: an eighteenth PMOS transistor MIP4 and a twelfth NMOS transistor MIN0,

and the grid electrode of the eighteenth PMOS tube is connected with the grid electrode of the twelfth NMOS tube and receives the high-voltage pulse signal, the source electrode of the eighteenth PMOS tube is connected with the high-level power supply, and the drain electrode of the eighteenth PMOS tube is connected with the drain electrode of the twelfth NMOS tube and is connected with the second end of the second driving buffer.

It should be noted that the principle and the working flow of the second driving buffer and the first driving buffer provided in the present embodiment are similar, and reference may be made to the above description for related points, which are not described herein again.

The first gate driving module Driver P provided by the utility model not only provides the driving capability for driving the PMOS, but also provides the false triggering capability for resisting the rapid dv/dt change of the output DO.

In one embodiment, as shown in fig. 9, the second gate driving module includes:

a fifth inverter U9-1, a first and gate U9-2, a third drive buffer, and a fourth drive buffer, wherein,

the first end of the first AND gate receives the low-voltage pulse signal through a fifth inverter, the second end of the first AND gate receives a low-voltage input signal, the output end of the first AND gate is connected with the second end of the third driving buffer,

the first end of the third driving buffer is connected with the low-level power supply, the third end is connected with the ground wire, the fourth end is connected with the second end of the fourth driving buffer,

and the first end of the fourth driving buffer is connected with the low-level power supply, the third end of the fourth driving buffer is connected with the ground wire, and the fourth end of the fourth driving buffer outputs the control signal for controlling the first NMOS to be turned on or turned off.

It should be noted that the principles and the work flows of the third driving buffer and the fourth driving buffer provided in this embodiment are similar to those of the first driving buffer, and reference may be made to the above description for related points, which are not described herein again.

The utility model provides that the second gate drive module Driver N can be the high level LVDD only when IN is the high level LVDD, DRP feedback is the high level LVDD, and the output DRN can be the high level LVDD, so that the drive capability of driving the NMOS of the output stage is provided, and the false triggering capability brought by resisting the dv/dt rapid change of the output DO is provided.

The level conversion driving circuit for the data output port of the LED color lamp string can realize level conversion from low-level logic signal input to high-level logic signal output, meets the requirements of the data output port of the high-voltage LED color lamp string on speed, pulse width distortion and transmission delay at ns level, can be applied to data forwarding of the cascaded data output port of the high-voltage LED color lamp string, and has wide application prospect.

It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.

Claims (10)

1. The utility model provides a LED color lamp cluster data output port level switch drive circuit which characterized in that includes:

a current reference module, a floating power module, a first level conversion module, a second level conversion module, a first gate driving module, a second gate driving module, a combination control module, a first PMOS tube and a first NMOS tube,

the combination control module is used for generating a control signal for controlling the first PMOS tube to be opened or closed according to a low-voltage input signal and a control signal for opening or closing the first NMOS tube generated by the second gate driving module;

the first level conversion module is used for converting a control signal for controlling the opening or closing of the first PMOS tube into a high-voltage pulse signal;

the first gate driving module is used for outputting a high-voltage gate pulse signal according to the high-voltage pulse signal and providing a driving voltage for the first PMOS tube, wherein the floating power supply module receives a reference current generated by the current reference module and outputs a floating ground voltage, and the floating ground voltage is processed and then used as a low level of the first gate driving module;

the second level conversion module is used for converting the high-voltage grid pulse signal into a low-voltage pulse signal;

the second gate driving module is used for generating a control signal for controlling the first NMOS to be turned on or turned off according to the low-voltage input signal and the low-voltage pulse signal;

the first PMOS tube is turned on or turned off according to the driving voltage generated by the first gate driving module;

the first NMOS tube is turned on or turned off according to a control signal which is generated by the second gate driving module and used for driving the PMOS to be turned on or turned off;

and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and outputs a high-voltage data signal.

2. The circuit of claim 1, wherein the current reference circuit comprises: a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a first triode, a second triode, a first resistor and a first current mirror module,

the source electrode of the second PMOS tube is connected with a low-level power supply, the drain electrode of the second PMOS tube is connected with the source electrode of the fourth PMOS tube, the grid electrode of the second PMOS tube is respectively connected with the grid electrode of the third PMOS tube, the drain electrode of the fourth PMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the tenth PMOS tube,

the source electrode of the third PMOS tube is connected with a low-level power supply, the drain electrode of the third PMOS tube is connected with the source electrode of the fifth PMOS tube,

the drain electrode of the fourth PMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the fourth PMOS tube is respectively connected with the grid electrode of the fifth PMOS tube, the grid electrode of the seventh PMOS tube, the grid electrode and the drain electrode of the eighth PMOS tube, the drain electrode of the seventh NMOS tube and the grid electrode of the eleventh PMOS tube,

the drain electrode of the fifth PMOS tube is respectively connected with the drain electrode and the grid electrode of the third NMOS tube,

the source electrode of the sixth PMOS tube is connected with a low-level power supply, the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube,

the drain electrode of the seventh PMOS tube is connected with the drain electrode of the fourth NMOS tube,

the source electrode of the eighth PMOS tube is connected with a low-level power supply, the drain electrode of the eighth PMOS tube is connected with the drain electrode of the fifth NMOS tube,

the source electrode of the ninth PMOS tube is connected with a low-level power supply, the drain electrode of the ninth PMOS tube is connected with the drain electrode of the sixth NMOS tube, the grid electrode of the ninth PMOS tube is connected with the ground wire,

the source electrode of the tenth PMOS tube is connected with a low-level power supply, the drain electrode of the tenth PMOS tube is connected with the source electrode of the eleventh PMOS tube, the grid electrode of the tenth PMOS tube is connected with the drain electrode of the eighth NMOS tube,

the drain electrode of the eleventh PMOS tube is connected with the first end of the first current mirror module,

the source electrode of the second NMOS tube is connected with the emitter electrode of the first triode through the first resistor, the grid electrode of the second NMOS tube is connected with the grid electrode of the third NMOS tube,

the source electrode of the third NMOS tube is connected with the emitter electrode of the second triode,

the drain electrode of the fourth NMOS tube is respectively connected with the grid electrode of the fourth NMOS tube and the grid electrode of the sixth NMOS tube, the source electrode of the fourth NMOS tube is connected with the ground wire, the grid electrode of the fourth NMOS tube is connected with the grid electrode of the fifth NMOS tube,

the source electrode of the fifth NMOS tube is connected with the ground wire,

the drain electrode of the sixth NMOS tube is respectively connected with the grid electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube, the source electrode is grounded,

the source electrode of the seventh NMOS tube is connected with the ground wire, the source electrode of the eighth NMOS tube is connected with the ground wire,

the collector of the first triode is respectively connected with the base of the first triode, the collector of the second triode and the ground wire, the base is connected with the base of the second triode,

and the third end of the first current mirror module outputs reference current, and the second end and the fourth end of the first current mirror module are connected with a ground wire.

3. The circuit of claim 1, wherein the floating power module comprises:

a ninth NMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a triode module, a second resistor and a third resistor, wherein,

the grid electrode of the ninth NMOS tube is connected with a low-level power supply, the source electrode of the ninth NMOS tube receives the reference current generated by the current reference module, the drain electrode of the ninth NMOS tube is respectively connected with the first end of the triode module and the grid electrode of the thirteenth PMOS tube,

the grid electrode of the twelfth PMOS tube is respectively connected with the drain electrode of the twelfth PMOS tube and the second end of the triode module, the source electrode of the twelfth PMOS tube is connected with the first end of the third resistor,

the drain electrode of the thirteenth PMOS tube is connected with the ground wire, the source electrode of the thirteenth PMOS tube is connected with the first end of the second resistor and outputs a floating ground voltage,

and the second ends of the third resistors are respectively connected with the high-level power supply and the second ends of the second resistors.

4. The circuit of claim 1, wherein the first level shift circuit comprises:

a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a second current mirror module, a first phase inverter and a first current source,

the source electrode of the fourteenth PMOS tube is connected with a high-level power supply, the drain electrode of the fourteenth PMOS tube is respectively connected with the grid electrode of the fourteenth PMOS tube, the drain electrode of the tenth NMOS tube and the grid electrode of the seventeenth PMOS tube,

the source electrode of the fifteenth PMOS tube is connected with a high-level power supply, the drain electrode of the fifteenth PMOS tube is respectively connected with the grid electrode of the fifteenth PMOS tube and the drain electrode of the eleventh NMOS tube, the grid electrode of the fifteenth PMOS tube is connected with the grid electrode of the sixteenth PMOS tube,

the source electrode of the sixteenth PMOS tube is connected with a high-level power supply, the drain electrode of the sixteenth PMOS tube is connected with the first end of the second current mirror,

the source electrode of the seventeenth PMOS tube is connected with a high-level power supply, the drain electrode of the seventeenth PMOS tube is connected with the third end of the second current mirror circuit to output a high-voltage pulse signal,

the grid electrode of the tenth NMOS tube is connected with the input end of the first phase inverter, is connected with the output end of the combined control module and receives a control signal for controlling the opening or closing of the first PMOS tube, the source electrode of the tenth NMOS tube is connected with the source electrode of the eleventh NMOS tube,

the grid electrode of the eleventh NMOS tube is connected with the output end of the first reverser,

the first end of the first current source is connected with the ground wire, the second end of the first current source is respectively connected with the source electrode of the tenth NMOS tube and the source electrode of the eleventh NMOS tube,

the second end and the fourth end of the second current mirror module receive the floating ground voltage output by the floating power supply module.

5. The circuit of claim 1, wherein the second level shifting module comprises: a second current source, a third current source, an eighteenth PMOS tube, a second inverter and a third current mirror module, wherein,

the first end of the second current source is connected with a high-level power supply, the second end of the second current source is connected with the source electrode of the eighteenth PMOS tube,

the grid electrode of the eighteenth PMOS tube receives the high-voltage grid pulse signal of the first PMOS tube, the drain electrode of the eighteenth PMOS tube is connected with the first end of the third current mirror circuit,

the second end and the fourth end of the third current mirror module are connected with the ground wire, the third end is connected with the input end of the second reverser,

the input end of the second inverter is connected with the low-level power supply through a third current source, and the output end of the second inverter outputs the control signal for controlling the first NMOS to be turned on or turned off.

6. The circuit of claim 1, wherein the combination control module comprises: a third inverter, a fourth inverter and a first OR gate,

the input end of the third inverter receives a control signal for turning on or off the first NMOS, the output end of the third inverter is connected with the input end of the fourth inverter,

and a first input end of the first or gate is connected with an output end of the fourth inverter, a second input end of the first or gate receives a low-voltage input signal, and an output end of the first or gate outputs an input control signal for controlling the first level conversion module.

7. The circuit of claim 1, wherein the first gate drive module comprises a first drive buffer and a second drive buffer, wherein,

a first terminal of the first driving buffer is connected with a high-level power supply, a second terminal receives the high-voltage pulse signal, a third terminal receives the floating ground voltage, a fourth terminal is connected with a second terminal of the second driving buffer,

and the first end of the second driving buffer is connected with a high-level power supply, the third end of the second driving buffer receives the floating ground voltage, and the fourth end of the second driving buffer outputs the high-voltage grid pulse signal.

8. The circuit of claim 1, wherein the second gate driving module comprises:

a fifth inverter, a first AND gate, a third driving buffer, and a fourth driving buffer, wherein,

the first end of the first AND gate receives the low-voltage pulse signal through a fifth inverter, the second end of the first AND gate receives a low-voltage input signal, the output end of the first AND gate is connected with the second end of the third driving buffer,

the first end of the third driving buffer is connected with the low-level power supply, the third end is connected with the ground wire, the fourth end is connected with the second end of the fourth driving buffer,

and the first end of the fourth driving buffer is connected with the low-level power supply, the third end of the fourth driving buffer is connected with the ground wire, and the fourth end of the fourth driving buffer outputs the control signal for controlling the first NMOS to be turned on or turned off.

9. The circuit of claim 3, wherein the triode module comprises N triodes,

the base electrode of the nth triode is connected with the self collector electrode, the emitter electrode is connected with the collector electrode of the (N + 1) th triode, wherein N is more than or equal to 2 and less than or equal to N-1,

and the collector electrode of the 1 st triode is connected with the drain electrode of the twelfth PMOS tube, and the emitter electrode of the Nth triode is connected with the drain electrode of the ninth NMOS tube.

10. The circuit of claim 7, wherein the first drive buffer comprises: an eighteenth PMOS tube and a twelfth NMOS tube,

and the grid electrode of the eighteenth PMOS tube is connected with the grid electrode of the twelfth NMOS tube and receives the high-voltage pulse signal, the source electrode of the eighteenth PMOS tube is connected with the high-level power supply, and the drain electrode of the eighteenth PMOS tube is connected with the drain electrode of the twelfth NMOS tube and is connected with the second end of the second driving buffer.

Images