CN216310637U

CN216310637U - Clamp for verifying performance of LDO (low dropout regulator) chip

Info

Publication number: CN216310637U
Application number: CN202122600836.3U
Authority: CN
Inventors: 陈晨
Original assignee: Taicang T&W Electronics Co Ltd
Current assignee: Taicang T&W Electronics Co Ltd
Priority date: 2021-10-27
Filing date: 2021-10-27
Publication date: 2022-04-15
Anticipated expiration: 2031-10-27

Abstract

The utility model discloses a clamp for verifying the performance of an LDO (low dropout regulator) chip, which comprises a PCB (printed circuit board), wherein the PCB is provided with an LDO chip pin base, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2 and a triode Q1, the LDO chip pin base is provided with three pins, the pin 1 is connected with a resistor R1 and a resistor R2 in parallel, the other end of the resistor R2 is grounded, the other end of the resistor R1 is connected with the pin 2, the pin 2 is connected with one end of the resistor R3, the other end of the resistor R3 is connected with a collector of a triode Q1, one end of the capacitor C2 is grounded, the other end of the capacitor C is connected with a collector of the triode Q1, an emitter of the triode Q1 is connected with an external electronic load, a base of the triode Q1 is connected with an external circuit, the pin 3 is connected with a voltage input source, one end of the capacitor C1 is grounded, and the other end of the pin is connected with the pin 3. The realization is easy, and the working capacity under the full-load state can be verified. Low cost and high cost performance.

Description

Clamp for verifying performance of LDO (low dropout regulator) chip

Technical Field

The utility model relates to a clamp for verifying the performance of an LDO (low dropout regulator) chip, which is used for verifying the loading capacity of the LDO chip when the LDO chip is fully loaded. The method is mainly used for verifying the capability of the LDO chip whether to work normally in the research and development stage.

Background

In order to ensure that the LDO chip can normally work, the working capacity under the full-load state needs to be verified, and the common LDO is used in an actual prototype, the actual prototype has limited capacity for the LDO load current, the capacity under the full-load state of the LDO cannot be verified, and the loading capacity of the LDO chip can be verified by using the clamp when the LDO chip is fully loaded.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a clamp for verifying the performance of an LDO chip aiming at the defects of the prior art, the load carrying capacity of the LDO chip is observed when the LDO chip is fully loaded, the cost is low, and the operation is convenient.

In order to solve the problems, the technical scheme adopted by the utility model is as follows:

the utility model provides a verify anchor clamps of LDO chip performance, including the PCB board, be equipped with LDO chip pin holder, resistance R1, resistance R2, resistance R3, electric capacity C1, electric capacity C2 and triode Q1 on the PCB board, LDO chip pin holder has three pin, 1 foot parallel connection resistance R1 and resistance R2, resistance R2's other end ground connection, 2 feet are connected to resistance R1's the other end, 2 feet connecting resistance R3's one end, triode Q1's collecting electrode is connected to resistance R3's the other end, electric capacity C2's one end ground connection, another termination triode Q1's collecting electrode, external electronic load is connected to triode Q1's projecting pole, triode Q1's base connects external circuit, 3 feet connect voltage input source VIN, electric capacity C1's one end ground connection, the other end links to each other end with 3 feet.

A further technical solution is that the voltage of the voltage input source VIN is 12V, the resistance of the resistor R1 is 120 ohms, the resistance of the resistor R2 is 200 ohms, the resistance of the resistor R3 is 0 ohms, the capacitance of the capacitor C1 is 0.1uf, and the capacitance of the capacitor C2 is 0.1 uf.

Adopt the produced beneficial effect of above-mentioned technical scheme to lie in: the realization is easy, and the working capacity under the full-load state can be verified. Low cost and high cost performance.

Drawings

FIG. 1 is a schematic of the present invention.

Detailed Description

The embodiments of the present invention will be described in further detail with reference to the drawings and examples. The following examples are intended to illustrate the utility model but are not intended to limit the scope of the utility model.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

As shown in fig. 1, a fixture for verifying the performance of an LDO chip is disclosed, which is used for verifying the load carrying capability of the LDO chip when the LDO chip is fully loaded, and includes a PCB board, where the PCB board is provided with a pin holder of the LDO chip, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, and a transistor Q1, the pin holder of the LDO chip has three pins, a pin 1 is connected in parallel with the resistor R1 and the resistor R2, the other end of the resistor R2 is grounded, the other end of the resistor R1 is connected with the pin 2, the pin 2 is connected with one end of the resistor R3, the other end of the resistor R3 is connected with the collector of a transistor Q1, one end of the capacitor C2 is grounded, the other end is connected with the collector of a transistor Q1, the emitter of the transistor Q1 is connected with an external electronic load, the base of the transistor Q1 is connected with an external circuit, the pin 3 is connected with a voltage input source, one end of the capacitor C1 is grounded, and the other end is connected with the pin 3.

The voltage of the voltage input source VIN is 12V, the resistance of the resistor R1 is 120 ohms, the resistance of the resistor R2 is 200 ohms, the resistance of the resistor R3 is 0 ohms, the capacitance of the capacitor C1 is 0.1uf, and the capacitance of the capacitor C2 is 0.1 uf.

The working principle is as follows: 1. and the voltage input source VIN is used for supplying power to a pin end of the pin base of the LDO chip, and the power supply voltage is 12V. 2. The pin socket of the LDO chip has 3 pins and is used for welding the LDO chip to be tested on, currently, the ZTP1117 chip of ZILLTEK company is used for verification, and the pins correspond to the following: pin 1 is the LDO chip ADJ pin, for adjustable pin, there are two uses, firstly as the reference voltage point, provide 1.25V's reference voltage, secondly as current adjustment, can provide 35 uA's current output, resistance R1 and resistance R2 are divider resistance, resistance R1 is 120 ohms, resistance R2 is 200 ohms, 2 pins are LDO chip output pin, provide output voltage and current, resistance R3 is 0 ohms resistance, be used for the test use here, it connects in series to take off 0 ohms resistance into the wire when needing to carry out the current test promptly, electric capacity C2 is output voltage filter capacitor, the appearance value is 0.1uf, 3 pins are LDO chip power input pin, connect in series to ground through electric capacity C1, electric capacity C1 is 0.1uf, as power input filter capacitor. 3. The emitter of the triode Q1 is connected to an external electronic load through a lead, the collector is connected with the resistor R3, the base level is controlled to be at a high level or a low level by an external circuit, the triode Q1 is used as a switch, when the high level is input externally, the triode is switched on, the electronic load can pump current at the moment, when the low level is input externally, the triode is switched off, and the LDO output and the electronic load are switched off at the moment.

When the clamp is used for verification, firstly, a LDO chip to be tested is welded on a pin base of the LDO chip, currently, a ZTP1117 chip of ZILLTEK company is used for verification, 12V voltage is firstly input to VIN, at the moment, the triode Q1 is in an off state, the LDO chip is in an idle state and can normally output 3.3V voltage, at the moment, the electronic load is adjusted to be 1A, the triode Q1 is opened and is in an on state, at the moment, the electronic load can pump 1A current, at the moment, the output voltage of the LDO chip is tested to be 3.3V by a universal meter, the operation is normal, the electronic load is adjusted to be 1.1A again, the triode Q1 is opened and is in an on state, at the moment, the electronic load can pump 1.1A current, at the moment, the output voltage of the LDO chip is tested to be 3.3V by the universal meter, the operation is normal, finally, the electronic load is adjusted to be 1.2A, the triode Q1 is opened and is in the on state, at the moment, the electronic load can carry 1.2A current, so that the output voltage of the LDO chip is tested to be 0V by using a universal meter, the operation is abnormal, the current value at the moment is recorded, and the full load carrying capacity is 1.1A. The scheme is simple to realize, the cost is saved, the cost of the clamp is only dozens of money, and the operation is convenient.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. The utility model provides a verify anchor clamps of LDO chip performance which characterized in that: the low dropout regulator comprises a PCB (printed circuit board), wherein an LDO (low dropout regulator) chip pin base, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2 and a triode Q1 are arranged on the PCB, the LDO chip pin base is provided with three pins, a 1-pin parallel connection resistor R1 and a resistor R2, the other end of the resistor R2 is grounded, the other end of the resistor R1 is connected with the 2 pin, the 2 pin is connected with one end of a resistor R3, the other end of the resistor R3 is connected with a collector of a triode Q1, one end of the capacitor C2 is grounded, the other end of the capacitor C1 is connected with the collector of the triode Q1, an emitter of the triode Q1 is connected with an external electronic load, a base of the triode Q1 is connected with an external circuit, the 3 pin is connected with a voltage input source VIN, one end of the capacitor C1 is grounded, and the other end of the capacitor C3 pin is connected with the external electronic load.

2. The fixture of claim 1, wherein the fixture for verifying the performance of the LDO chip comprises: the voltage of the voltage input source VIN is 12V, the resistance value of the resistor R1 is 120 ohms, the resistance value of the resistor R2 is 200 ohms, the resistance value of the resistor R3 is 0 ohms, the capacitance value of the capacitor C1 is 0.1uf, and the capacitance value of the capacitor C2 is 0.1 uf.