CN215641648U

CN215641648U - Circuit board clamp for verifying loop response of DCDC power supply chip

Info

Publication number: CN215641648U
Application number: CN202121084175.7U
Authority: CN
Inventors: 陈晨
Original assignee: Taicang T&W Electronics Co Ltd
Current assignee: Taicang T&W Electronics Co Ltd
Priority date: 2021-05-20
Filing date: 2021-05-20
Publication date: 2022-01-25
Anticipated expiration: 2031-05-20

Abstract

The utility model discloses a circuit board clamp for verifying loop response of a DCDC power supply chip, which comprises a PCB, wherein the PCB is provided with a voltage input end Vin, a voltage output end Vout, a DCDC chip holder, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, an inductor L1, a first loop response test end PA and a second loop response test end PB. The power loop response of the DCDC chip can be verified, and corresponding parameters can be obtained. The realization is easy, the scheme has low cost and high cost performance.

Description

Circuit board clamp for verifying loop response of DCDC power supply chip

Technical Field

The utility model relates to a circuit board clamp for verifying loop response of a DCDC power supply chip, which is used for verifying whether the loop response of the DCDC power supply chip meets requirements under different load states and whether a circuit can normally work. The method is mainly used for verifying the condition of the DCDC chip under different load states in the research and development stage.

Background

In order to ensure that the DCDC chip can normally work, verification under different load conditions is required, namely the electronic load is used for verifying the drawing current, the cost of the existing verification mode is high, and the loop response of the DCDC chip under different load conditions can be verified by using the clamp plate, so that corresponding parameters are obtained, and whether the circuit is stable or not is judged.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a circuit board clamp for verifying loop response of a DCDC power supply chip, aiming at the defects of the prior art.

In order to solve the problems, the technical scheme adopted by the utility model is as follows:

a circuit board clamp for verifying loop response of a DCDC power supply chip comprises a PCB, wherein a voltage input end Vin, a voltage output end Vout, a DCDC chip seat, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, an inductor L1, a first loop response test end PA and a second loop response test end PB are arranged on the PCB, the DCDC chip seat is provided with six pins, the voltage input end Vin is connected with a pin 1 of the DCDC chip seat, the voltage output end Vout is connected with a pin 5 of the DCDC chip seat, the resistor R1 and the capacitor C1 are connected in series and then connected in parallel with the capacitor C2 and the capacitor C3, one end of the parallel connection is connected with a pin 1 of the DCDC chip seat, the other end of the parallel connection is connected with a pin 3 of the DCDC chip seat, the pin 3 of the DCDC chip seat is grounded, a pin 2 of the DCDC seat is connected between the capacitor C3985 and the capacitor C3985, the capacitor C4 is connected in series between a pin 5 and a pin 6 of the DCDC chip holder, the inductor L1 is connected in series between the pin 5 of the DCDC chip holder and a voltage output end Vout, after the resistor R2, the resistor R3 and the resistor R4 are connected in series, one end of the inductor L1 is connected between the voltage output end Vout, the other end of the inductor L1 is connected with a pin 3 of the DCDC chip holder, a pin 4 of the DCDC chip holder is connected between a resistor R3 and a resistor R4, the capacitor C5 is connected in parallel with a resistor R3, one end of the capacitor C6 is connected with the voltage output end Vout, the other end of the capacitor C6 is connected with the pin 3 of the DCDC chip holder, the first loop response test end PA is connected with one end of the resistor R2, and the second loop response test end PB is connected with the other end of the resistor R2.

Further, the voltage input by the voltage input terminal Vin is 12V.

The further technical scheme is that the capacitor C1 is a capacitor C1 of 10uf, the capacitor C2 of 0.1uf, the capacitor C3 of 0.1uf, the capacitor C4 of 0.1uf, the capacitor C5 of 0.1uf, and the capacitor C6 of 0.1 uf.

The further technical scheme is that the resistor R1 is 100K omega, the resistor R2 is 10 omega, the resistor R3 is 20K omega, and the resistor R4 is 29.4K omega.

The further technical scheme is that the inductance L1 is 2.2 uH.

Adopt the produced beneficial effect of above-mentioned technical scheme to lie in: the method is easy to implement, and can verify the power loop response of the DCDC chip and obtain corresponding parameters. The scheme has low cost and high cost performance.

Drawings

Fig. 1 is a schematic structural view of the present invention.

Detailed Description

The embodiments of the present invention will be described in further detail with reference to the drawings and examples. The following examples are intended to illustrate the utility model but are not intended to limit the scope of the utility model.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

As shown in fig. 1, a circuit board fixture for verifying the loop response of a DCDC power supply chip is disclosed, which is used for verifying whether the loop response of the DCDC power supply chip meets the requirements under different load conditions and whether the circuit can work normally. The circuit board is provided with a voltage input end Vin, a voltage output end Vout, a DCDC chip seat, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, an inductor L1, a first loop response test end PA and a second loop response test end PB, the DCDC chip seat is provided with six pins, the voltage input end Vin is connected with a pin 1 of the DCDC chip seat, the voltage output end Vout is connected with a pin 5 of the DCDC chip seat, the resistor R1 and the capacitor C3 are connected in series and then connected in parallel with the capacitor C1 and the capacitor C2, one end of the DCDC chip seat after parallel connection is connected with the pin 1 of the DCDC chip seat, the other end of the DCDC chip seat after parallel connection is connected with a pin 3 of the DCDC chip seat, the pin 3 of the DCDC chip seat is grounded, a pin 2 of the DCDC chip seat is connected between the resistor R1 and the capacitor C4 9, and the capacitor C5966 are connected in series between the DCDC chip seat, the inductor L1 is connected in series between a pin 5 of the DCDC chip base and a voltage output end Vout, after the resistor R2, the resistor R3 and the resistor R4 are connected in series, one end of the resistor R2 is connected between the inductor L1 and the voltage output end Vout, the other end of the resistor R4 is connected with a pin 3 of the DCDC chip base, a pin 4 of the DCDC chip base is connected between the resistor R3 and the resistor R4, the capacitor C5 is connected with the resistor R3 in parallel, one end of the capacitor C6 is connected with the voltage output end Vout, the other end of the capacitor C6 is connected with the pin 3 of the DCDC chip base, the first loop response test end PA is connected with one end of the resistor R2, and the second loop response test end PB is connected with the other end of the resistor R2.

The voltage input by the voltage input end Vin is 12V. The capacitor C1 of the capacitor C1 is 10uf, the capacitor C2 is 0.1uf, the capacitor C3 is 0.1uf, the capacitor C4 is 0.1uf, the capacitor C5 is 0.1uf, and the capacitor C6 is 0.1 uf. The resistor R1 is 100K omega, the resistor R2 is 10 omega, the resistor R3 is 20K omega, and the resistor R4 is 29.4K omega. Inductance L1 was 2.2 uH.

The working principle is as follows: 1. the voltage input end Vin serves as a voltage input source and is used for supplying power to the DCDC chip, and the power supply voltage is 12V. 2. The DCDC chip holder has 6 pins for soldering the DCDC chip to be tested thereon, and currently uses ZTP7193KT as a verification chip. Pin 1 is Vin voltage input, pin 2 is an EN enable pin, pin 3 is a ground pin, pin 4 is an output FB feedback loop pin, pin 5 is an SW output pin, and pin 6 is a BOOT pin. The other components have the following functions: the capacitor C1 and the capacitor C2 are input bypass capacitors, the capacitor C1 is 10uf, and the capacitor C2 is 0.1uf, and are used for filtering input voltage; the resistor R1 and the capacitor C3 form an RC delay circuit, the resistor R1 is 100K omega, and the capacitor C3 is 0.1uf, so that the EN pin is enabled to delay; the capacitor C4 is a bootstrap capacitor, and the capacitor C4 is 0.1 uf; the inductor L1 is an energy storage inductor and is 2.2 uH; the resistor R2 is a test power supply loop response resistor with the resistance value of 10 ohms and is used for injecting small signals to two ends of the resistor; r3 and R4 are output voltage dividing resistors, R3 is 20K omega, and R4 is 29.4K omega; the capacitor C5 is a feedforward capacitor and can be used for adjusting loop response parameters, such as a zero-order point in a Burdet diagram; the capacitor C6 is an output filter capacitor with a capacitance value of 0.1 uf. 3. The voltage output end Vout is output voltage and is used for connecting an external electronic load, and the output voltage of the circuit is 3.3V and is used for drawing current and simulating the service condition of the load. The first loop response test end PA and the second loop response test end PB are two SMA seats, are connected to an external loop response tester, and are used for injecting small signals to two ends of the resistor R2 to perform loop response test analysis.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A circuit board clamp for verifying loop response of a DCDC power supply chip comprises a PCB and is characterized in that a voltage input end Vin, a voltage output end Vout, a DCDC chip holder, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, an inductor L1, a first loop response test end PA and a second loop response test end PB are arranged on the PCB, the DCDC chip holder is provided with six pins, the voltage input end Vin is connected with a pin 1 of the DCDC chip holder, the voltage output end Vout is connected with a pin 5 of the DCDC chip holder, the resistor R1 and the capacitor C1 are connected in series and then connected with the capacitor C2 and the capacitor C3 in parallel, one end of the DCDC chip holder after parallel connection is connected with a pin 1 of the DCDC chip holder, the other end of the DCDC chip holder after parallel connection is connected with a pin 3 of the DCDC chip holder, the DCDC chip holder is grounded, a pin 3 of the DCDC chip holder is connected between the capacitor C1 and the capacitor C1, the capacitor C4 is connected in series between a pin 5 and a pin 6 of the DCDC chip holder, the inductor L1 is connected in series between the pin 5 of the DCDC chip holder and a voltage output end Vout, after the resistor R2, the resistor R3 and the resistor R4 are connected in series, one end of the inductor L1 is connected between the voltage output end Vout, the other end of the inductor L1 is connected with a pin 3 of the DCDC chip holder, a pin 4 of the DCDC chip holder is connected between a resistor R3 and a resistor R4, the capacitor C5 is connected in parallel with a resistor R3, one end of the capacitor C6 is connected with the voltage output end Vout, the other end of the capacitor C6 is connected with the pin 3 of the DCDC chip holder, the first loop response test end PA is connected with one end of the resistor R2, and the second loop response test end PB is connected with the other end of the resistor R2.

2. The circuit board clamp for verifying loop response of the DCDC power supply chip as recited in claim 1, wherein: the voltage input by the voltage input end Vin is 12V.

3. The circuit board clamp for verifying loop response of the DCDC power supply chip as recited in claim 1, wherein: the capacitor C1 of the capacitor C1 is 10uf, the capacitor C2 is 0.1uf, the capacitor C3 is 0.1uf, the capacitor C4 is 0.1uf, the capacitor C5 is 0.1uf, and the capacitor C6 is 0.1 uf.

4. The circuit board clamp for verifying loop response of the DCDC power supply chip as recited in claim 1, wherein: the resistor R1 is 100K omega, the resistor R2 is 10 omega, the resistor R3 is 20K omega, and the resistor R4 is 29.4K omega.

5. The circuit board clamp for verifying loop response of the DCDC power supply chip as recited in claim 1, wherein: inductance L1 was 2.2 uH.