CN216213473U - Semiconductor device with a plurality of transistors - Google Patents
Semiconductor device with a plurality of transistors Download PDFInfo
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- CN216213473U CN216213473U CN202121812563.2U CN202121812563U CN216213473U CN 216213473 U CN216213473 U CN 216213473U CN 202121812563 U CN202121812563 U CN 202121812563U CN 216213473 U CN216213473 U CN 216213473U
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Abstract
The application provides a semiconductor device, which comprises a substrate and a grid structure positioned above the substrate, wherein the grid structure comprises a first insulating layer, a semiconductor layer, a barrier layer and a metal layer which are sequentially arranged above the substrate in a laminated manner; wherein the size of the lower surface of the semiconductor layer is larger than the size of the upper surface of the semiconductor layer, and the metal layer completely covers the semiconductor layer. Cover (shelter from) the uncontrolled semiconductor layer of slope angle through the metal level at least in this application for the marginal dimension of gate structure mainly is easily controlled and the great metal level of sculpture slope angle decides by the slope angle, even the slope angle of semiconductor layer is uncontrolled, can not influence follow-up appearance and the position in the doping area that both sides formed yet, the uncontrolled short circuit problem that leads to in appearance and the position of doping area that has significantly reduced.
Description
Technical Field
The application relates to the technical field of semiconductor devices, in particular to a semiconductor device.
Background
Due to their small size, versatility and/or low manufacturing cost, semiconductor devices can be used in various ways in the electronics industry. The semiconductor device may be classified into a semiconductor memory device for storing logic data, a semiconductor logic device for processing logic data, and a hybrid semiconductor device having a function of the semiconductor memory device and a function of the semiconductor logic device. The electronics industry is increasingly demanding semiconductor devices with high reliability, high speed and/or versatility. Therefore, the structure of the semiconductor device becomes more and more complicated, and the semiconductor device has become highly integrated. The semiconductor memory device comprises an active area and a peripheral area, wherein the active area comprises a recessed gate structure, the peripheral area comprises a planar gate structure, and the structural design of the planar gate structure generally influences the appearance and the position of doped areas on two sides of the planar gate structure, so that the appearance and the position of the doped areas on two sides are not controlled, and finally the electrical performance of the semiconductor device is influenced, and a short circuit is caused.
SUMMERY OF THE UTILITY MODEL
In view of the above problems, the present application provides a semiconductor device, which solves the technical problem that the structural design of a planar gate structure in the prior art easily affects the appearance and position of doped regions on both sides.
The present application provides a semiconductor device including: the gate structure comprises a substrate and a gate structure positioned above the substrate;
the grid structure comprises a first insulating layer, a semiconductor layer, a barrier layer and a metal layer which are sequentially arranged above the substrate in a laminated manner;
wherein the size of the lower surface of the semiconductor layer is larger than the size of the upper surface of the semiconductor layer, and the metal layer completely covers the semiconductor layer.
According to an embodiment of the present application, optionally, the semiconductor device further includes: the second insulating layer wraps the side face of the grid structure;
the second insulating layer includes:
the first part wraps the side face of the semiconductor layer;
the second part wraps the side surface of the barrier layer and the side surface of the metal layer;
wherein a maximum lateral distance between an outer edge of the first portion and a bottom edge of the semiconductor layer is not less than a maximum lateral distance between an outer edge of the second portion and the bottom edge of the semiconductor layer.
According to an embodiment of the application, optionally, in the semiconductor device, a thickness of the first portion is greater than a thickness of the second portion.
According to an embodiment of the application, optionally, in the semiconductor device, a maximum lateral distance between an outer edge of the first portion and a bottom edge of the semiconductor layer is not less than a maximum lateral distance between an outer edge of the first insulating layer and the bottom edge of the semiconductor layer.
According to an embodiment of the application, optionally, in the semiconductor device, a size of an upper surface of the first insulating layer is not smaller than a size of a lower surface of the semiconductor layer, and the upper surface of the first insulating layer completely covers the lower surface of the semiconductor layer.
According to an embodiment of the present application, optionally, in the semiconductor device, a size of a lower surface of the barrier layer is not smaller than a size of an upper surface of the semiconductor layer, and the lower surface of the barrier layer completely covers the upper surface of the semiconductor layer.
According to an embodiment of the present application, optionally, in the semiconductor device, a size of an upper surface of the barrier layer is larger than a size of a lower surface of the barrier layer.
According to an embodiment of the present application, optionally, in the semiconductor device, a size of an upper surface of the barrier layer is not smaller than a size of a lower surface of the semiconductor layer.
According to an embodiment of the present application, optionally, in the semiconductor device, a size of the lower surface of the metal layer is not greater than a size of the upper surface of the barrier layer, and the upper surface of the barrier layer completely covers the lower surface of the metal layer.
According to an embodiment of the present application, optionally, in the semiconductor device, a size of an upper surface of the metal layer is not larger than a size of a lower surface of the metal layer.
According to an embodiment of the present application, optionally, the semiconductor device further includes:
the first doping area and the second doping area are arranged in the upper surface of the substrate and are respectively positioned on two sides of the first insulating layer;
wherein neither the first insulating layer nor the second insulating layer covers the first doped region nor the second doped region.
According to an embodiment of the present application, optionally, in the semiconductor device, the gate structure further includes:
a third insulating layer over the metal layer.
According to an embodiment of the present application, optionally, in the semiconductor device, a size of a lower surface of the third insulating layer is not greater than a size of an upper surface of the metal layer, and the upper surface of the metal layer completely covers the lower surface of the third insulating layer.
According to an embodiment of the present application, optionally, in the semiconductor device, a size of an upper surface of the third insulating layer is not larger than a size of a lower surface of the third insulating layer.
Compared with the prior art, one or more embodiments in the above scheme can have the following advantages or beneficial effects:
the application provides a semiconductor device, which comprises a substrate and a grid structure positioned above the substrate, wherein the grid structure comprises a first insulating layer, a semiconductor layer, a barrier layer and a metal layer which are sequentially arranged above the substrate in a laminated manner; wherein the size of the lower surface of the semiconductor layer is larger than the size of the upper surface of the semiconductor layer, and the metal layer completely covers the semiconductor layer. Cover (shelter from) the uncontrolled semiconductor layer of slope angle through the metal level at least in this application for the marginal dimension of gate structure mainly is easily controlled and the great metal level of sculpture slope angle decides by the slope angle, even the slope angle of semiconductor layer is uncontrolled, can not influence follow-up appearance and the position in the doping area that both sides formed yet, the uncontrolled short circuit problem that leads to in appearance and the position of doping area that has significantly reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application and not to limit the application. In the drawings:
FIG. 1 is a schematic cross-sectional view of a semiconductor device;
fig. 2 is a schematic cross-sectional structure diagram of a semiconductor device according to an exemplary embodiment of the present application;
fig. 3 is a schematic cross-sectional structure diagram of another semiconductor device shown in an exemplary embodiment of the present application;
fig. 4 is a schematic cross-sectional structure diagram of another semiconductor device shown in an exemplary embodiment of the present application;
fig. 5 is a schematic cross-sectional structure diagram of another semiconductor device shown in an exemplary embodiment of the present application;
fig. 6 is a schematic cross-sectional structure diagram of another semiconductor device shown in an exemplary embodiment of the present application;
fig. 7 is a schematic cross-sectional structure diagram of another semiconductor device shown in an exemplary embodiment of the present application;
FIG. 8 is a schematic flow chart diagram illustrating a method of fabricating a semiconductor device in accordance with an exemplary embodiment of the present application;
in the drawings, wherein like parts are designated with like reference numerals, the drawings are not necessarily to scale;
the reference signs are:
101-a substrate; 102-a first insulating layer; 103-a semiconductor layer; 104-a barrier layer; 105-a metal layer; 106-a second insulating layer; 107-first doped region; 108-a second doped region;
201-a substrate; 202-a first insulating layer; 203-a semiconductor layer; 204-a barrier layer; 205-a metal layer; 206-a second insulating layer; 2061-first portion; 2062-second part; 2063-third fraction; 207-a first doped region; 208-a second doped region; 209-third insulating layer; d1 — maximum lateral distance of the outside edge of the first portion from the bottom edge of the semiconductor layer; d2-maximum lateral distance of the outside edge of the second portion from the bottom edge of the semiconductor layer.
Detailed Description
The following detailed description will be provided with reference to the accompanying drawings and embodiments, so that how to apply the technical means to solve the technical problems and achieve the corresponding technical effects can be fully understood and implemented. The embodiments and various features in the embodiments of the present application can be combined with each other without conflict, and the formed technical solutions are all within the scope of protection of the present application. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
It will be understood that spatial relationship terms, such as "above", "below", "beneath", and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" other elements would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the present application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
In order to provide a thorough understanding of the present application, detailed structures and steps will be provided in the following description in order to explain the technical solutions proposed in the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions.
A semiconductor device having the structure shown in fig. 1, comprising: a substrate 101, a gate structure (not labeled), a second insulating layer 106, a first doped region 107, and a second doped region 108. The gate structure includes: a first insulating layer 102, a semiconductor layer 103, a barrier layer 104, and a metal layer 105. In the semiconductor device, the barrier layer 104 and the metal layer 105 do not completely cover the semiconductor layer 103, so the film thickness of the second insulating layer 106 deposited thereon is relatively uniform, the slope angle of the semiconductor layer 103 is small and uncontrolled, and in the formation process of the first doped region 107 and the second doped region 108, the gate structure is used as a part of a mask, the size of the gate structure is directly related to the slope angle of the semiconductor layer 103, so the slope angle of the semiconductor layer 103 directly affects the appearance and the position of the first doped region 107 and the second doped region 108 on both sides, so that the appearance and the position of the doped regions on both sides are not controlled, and finally the electrical performance of the semiconductor device is affected to cause short circuit.
Example one
As shown in fig. 2, an embodiment of the present application provides a semiconductor device including: a substrate 201, a gate structure (not labeled), a second insulating layer 206, a first doped region 207, and a second doped region 208.
The gate structure is located above the substrate 201, and includes a first insulating layer 202, a semiconductor layer 203, a barrier layer 204 and a metal layer 205, which are sequentially stacked and disposed above the substrate 201.
The size of the lower surface of the semiconductor layer 203 is larger than the size of the upper surface of the semiconductor layer 203, that is, the slope angle (the included angle between the side surface and the lower surface) of the semiconductor layer 203 is smaller than 90 degrees.
Of the barrier layer 204 and the metal layer 205, at least the metal layer 205 completely covers the semiconductor layer 203, that is, an orthographic projection of the metal layer 205 on the substrate 201 at least covers an orthographic projection of the semiconductor layer 203 on the substrate 201.
The barrier layer 204 may also completely cover the semiconductor layer 203, i.e. an orthographic projection of the barrier layer 204 on the substrate 201 at least covers an orthographic projection of the semiconductor layer 203 on the substrate 201.
That is to say, in this embodiment, the semiconductor layer 203 with an uncontrolled slope angle is covered (shielded) by at least the metal layer 205, so that the edge size of the gate structure is mainly determined by the metal layer 205 with an easily controlled slope angle and a large etching slope angle, and even if the slope angle of the semiconductor layer 203 is uncontrolled, the shape and position of the doped region formed at both sides subsequently cannot be affected, and the short circuit problem caused by the uncontrolled shape and position of the doped region is greatly reduced.
The size of the upper surface of the first insulating layer 202 is not smaller than the size of the lower surface of the semiconductor layer 203, and the upper surface of the first insulating layer 202 completely covers the lower surface of the semiconductor layer 203.
The first insulating layer 202 may be aligned with the semiconductor layer 203 or may extend beyond the semiconductor layer 203, as shown in fig. 3.
The size of the lower surface of the barrier layer 204 is not smaller than the size of the upper surface of the semiconductor layer 203, and the lower surface of the barrier layer 204 completely covers the upper surface of the semiconductor layer 203, and in some cases, the lower surface of the barrier layer 204 may extend outside the upper surface of the semiconductor layer 203, as shown in fig. 4.
The upper surface of the barrier layer 204 has a larger dimension than the lower surface of the barrier layer 204. That is, the slope angle of barrier layer 204 is greater than 90 degrees.
A concave structure is formed at the interface of the barrier layer 204 and the semiconductor layer 203, which is more beneficial to shielding the semiconductor layer 203 from the barrier layer 204.
The size of the upper surface of the barrier layer 204 may also be not smaller than the size of the lower surface of the semiconductor layer 203, so that the barrier layer 204 can block the semiconductor layer 203, i.e., the orthographic projection of the barrier layer 204 on the substrate 201 can completely cover the orthographic projection of the semiconductor layer 203 on the substrate 201.
The size of the lower surface of the metal layer 205 is not larger than the size of the upper surface of the barrier layer 204, and the upper surface of the barrier layer 204 completely covers the lower surface of the metal layer 205, that is, the lower surface of the metal layer 205 may cover part of or the entire upper surface of the barrier layer 204.
The size of the upper surface of the metal layer 205 is not greater than the size of the lower surface of the metal layer 205. That is, the slope angle of the metal layer 205 is 90 degrees or less.
The size of the lower surface of the metal layer 205 is not smaller than the size of the lower surface of the semiconductor layer 203, so that the metal layer 205 can block the semiconductor layer 203, that is, the orthographic projection of the metal layer 205 on the substrate 201 can completely cover the orthographic projection of the semiconductor layer 203 on the substrate 201.
The second insulating layer 206 covers the sides and top surface of the gate structure.
The second insulating layer 206 includes: a first portion 2061 and a second portion 2062.
The first portion 2061 wraps around the side surface of the semiconductor layer 203.
The second portion 2062 wraps around the side of the barrier layer 204 and the side of the metal layer 205.
The maximum lateral distance D1 between the outer edge of the first portion 2061 and the bottom edge of the semiconductor layer 203 is not less than the maximum lateral distance D2 between the outer edge of the second portion 2062 and the bottom edge of the semiconductor layer 203, i.e., D1 is not less than D2.
The thickness of the first portion 2061 is greater than the thickness of the second portion 2062.
The second insulating layer 206 may further include a third portion 2063 that wraps around the top surface of the metal layer 205 (i.e., the top surface of the gate structure).
The maximum lateral distance between the outer edge of the first portion 2061 and the bottom edge of the semiconductor layer 203 is not less than the maximum lateral distance between the outer edge of the first insulating layer 202 and the bottom edge of the semiconductor layer 203. That is, when the first insulating layer 202 is aligned with the semiconductor layer 203, the first portion 2061 of the second insulating layer 206 covers the side surface of the first insulating layer 202, and when the first insulating layer 202 extends out of the semiconductor layer 203, the first portion 2061 of the second insulating layer 206 covers at least the upper surface of the outer portion of the first insulating layer 202 extending out of the semiconductor layer 203, and may even cover the upper surface and the side surface of the outer portion of the first insulating layer 202 extending out of the semiconductor layer 203.
The first doped region 207 and the second doped region 208 are disposed in the upper surface of the substrate 201 and located on two sides of the first insulating layer 202, respectively, wherein the first insulating layer 202 and the second insulating layer 206 do not cover the first doped region 207 and the second doped region 208.
Although the ion implantation mask in the process of forming the first doped region 207 and the second doped region 208 is the second insulating layer 206, the shape and size of the second insulating layer 206 depend on the shape and size of the gate structure, so that in this embodiment, at least the metal layer 205 covers (shields) the semiconductor layer 203 with an uncontrolled slope angle, so that the edge size of the gate structure is mainly determined by the metal layer 205 with an easily controlled slope angle and a large etching slope angle, and even if the slope angle of the semiconductor layer 203 is not controlled, the shape and position of the doped regions formed at two sides subsequently cannot be affected, thereby greatly reducing the short circuit problem caused by the uncontrolled shape and position of the doped regions.
In this embodiment, the semiconductor device may be a transistor.
The embodiment of the application provides a semiconductor device, which comprises a substrate 201 and a gate structure positioned above the substrate 201, wherein the gate structure comprises a first insulating layer 202, a semiconductor layer 203, a barrier layer 204 and a metal layer 205 which are sequentially stacked and arranged above the substrate 201; the size of the lower surface of the semiconductor layer 203 is larger than the size of the upper surface of the semiconductor layer 203, and the metal layer 205 completely covers the semiconductor layer 203. In this application at least cover (shelter from) the uncontrolled semiconductor layer of slope angle 203 through metal level 205 for the marginal dimension of gate structure mainly is easily controlled by the slope angle and the great metal level 205 of etching slope angle decides, even the slope angle of semiconductor layer 203 is uncontrolled, can not influence follow-up appearance and the position in the doping region that both sides formed yet, the appearance that has significantly reduced the doping region and the short circuit problem that the position is uncontrolled leads to.
Example two
As shown in fig. 5, an embodiment of the present application provides a semiconductor device including: a substrate 201, a gate structure, a second insulating layer 206, a first doped region 207 and a second doped region 208.
The gate structure is located above the substrate 201, and includes a first insulating layer 202, a semiconductor layer 203, a barrier layer 204, a metal layer 205, and a third insulating layer 209, which are sequentially stacked over the substrate 201.
The size of the lower surface of the semiconductor layer 203 is larger than the size of the upper surface of the semiconductor layer 203, that is, the slope angle of the semiconductor layer 203 is smaller than 90 degrees.
Of the barrier layer 204 and the metal layer 205, at least the metal layer 205 completely covers the semiconductor layer 203, that is, an orthographic projection of the metal layer 205 on the substrate 201 at least completely covers an orthographic projection of the semiconductor layer 203 on the substrate 201.
The barrier layer 204 may also completely cover the semiconductor layer 203, i.e. an orthographic projection of the barrier layer 204 on the substrate 201 at least completely covers an orthographic projection of the semiconductor layer 203 on the substrate 201.
That is to say, in this embodiment, the semiconductor layer 203 with an uncontrolled slope angle is covered (shielded) by at least the metal layer 205, so that the edge size of the gate structure is mainly determined by the metal layer 205 with an easily controlled slope angle and a large etching slope angle, and even if the slope angle of the semiconductor layer 203 is uncontrolled, the shape and position of the doped region formed at both sides subsequently cannot be affected, and the short circuit problem caused by the uncontrolled shape and position of the doped region is greatly reduced.
The size of the upper surface of the first insulating layer 202 is not smaller than the size of the lower surface of the semiconductor layer 203, and the upper surface of the first insulating layer 202 completely covers the lower surface of the semiconductor layer 203.
The first insulating layer 202 may be aligned with the semiconductor layer 203 or may extend beyond the semiconductor layer 203, as shown in fig. 6.
The size of the lower surface of the barrier layer 204 is not smaller than the size of the upper surface of the semiconductor layer 203, and the lower surface of the barrier layer 204 completely covers the upper surface of the semiconductor layer 203. In some cases, the lower surface of barrier layer 204 may extend outside the upper surface of semiconductor layer 203, as shown in fig. 7.
The upper surface of the barrier layer 204 has a larger dimension than the lower surface of the barrier layer 204. That is, the slope angle of barrier layer 204 is greater than 90 degrees.
A concave structure is formed at the interface of the barrier layer 204 and the semiconductor layer 203, which is more beneficial to shielding the semiconductor layer 203 from the barrier layer 204.
The size of the upper surface of the barrier layer 204 may also be not smaller than the size of the lower surface of the semiconductor layer 203, so that the barrier layer 204 can block the semiconductor layer 203, i.e., the orthographic projection of the barrier layer 204 on the substrate 201 can completely cover the orthographic projection of the semiconductor layer 203 on the substrate 201.
The size of the lower surface of the metal layer 205 is not larger than the size of the upper surface of the barrier layer 204, and the upper surface of the barrier layer 204 completely covers the lower surface of the metal layer 205, that is, the lower surface of the metal layer 205 may cover part of or the entire upper surface of the barrier layer 204.
The size of the upper surface of the metal layer 205 is not greater than the size of the lower surface of the metal layer 205. That is, the slope angle of the metal layer 205 is 90 degrees or less.
The size of the lower surface of the metal layer 205 is not smaller than the size of the lower surface of the semiconductor layer 203, so that the metal layer 205 can block the semiconductor layer 203, that is, the orthographic projection of the metal layer 205 on the substrate 201 can completely cover the orthographic projection of the semiconductor layer 203 on the substrate 201.
A third insulating layer 209 is located over the metal layer 205.
The size of the lower surface of the third insulating layer 209 is not greater than the size of the upper surface of the metal layer 205, and the upper surface of the metal layer 205 completely covers the lower surface of the third insulating layer 209.
The size of the upper surface of the third insulating layer 209 is not greater than the size of the lower surface of the third insulating layer 209. That is, the slope angle of the metal layer 205 is 90 degrees or less.
The third insulating layer 209 may further achieve protection of the metal layer 205.
The second insulating layer 206 covers the sides and top surface of the gate structure.
The second insulating layer 206 includes: a first portion 2061 and a second portion 2062.
The first portion 2061 wraps around the side of the semiconductor layer 203.
The second portion 2062 wraps around the side of the barrier layer 204 and the side of the metal layer 205.
The maximum lateral distance D1 between the outer edge of the first portion 2061 and the bottom edge of the semiconductor layer 203 is not less than the maximum lateral distance D2 between the outer edge of the second portion 2062 and the bottom edge of the semiconductor layer 203, i.e., D1 is not less than D2.
The thickness of the first portion 2061 is greater than the thickness of the second portion 2062.
The second insulating layer 206 may also include a third portion 2063 coating the sides and top of the third insulating layer 209.
The maximum lateral distance between the outer edge of the first portion 2061 and the bottom edge of the semiconductor layer 203 is not less than the maximum lateral distance between the outer edge of the first insulating layer 202 and the bottom edge of the semiconductor layer 203. That is, when the first insulating layer 202 is aligned with the semiconductor layer 203, the first portion 2061 of the second insulating layer 206 covers the side surface of the first insulating layer 202, and when the first insulating layer 202 extends out of the semiconductor layer 203, the first portion 2061 of the second insulating layer 206 covers at least the upper surface of the outer portion of the first insulating layer 202 extending out of the semiconductor layer 203, and may even cover the upper surface and the side surface of the outer portion of the first insulating layer 202 extending out of the semiconductor layer 203.
The first doped region 207 and the second doped region 208 are disposed in the upper surface of the substrate 201 and located on two sides of the first insulating layer 202, respectively, wherein the first insulating layer 202 and the second insulating layer 206 do not cover the first doped region 207 and the second doped region 208.
Although the ion implantation mask in the process of forming the first doped region 207 and the second doped region 208 is the second insulating layer 206, the shape and size of the second insulating layer 206 depend on the shape and size of the gate structure, so that in this embodiment, at least the metal layer 205 covers (shields) the semiconductor layer 203 with an uncontrolled slope angle, so that the edge size of the gate structure is mainly determined by the metal layer 205 with an easily controlled slope angle and a large etching slope angle, and even if the slope angle of the semiconductor layer 203 is not controlled, the shape and position of the doped regions formed at two sides subsequently cannot be affected, thereby greatly reducing the short circuit problem caused by the uncontrolled shape and position of the doped regions.
In this embodiment, the semiconductor device may be a transistor.
The embodiment of the application provides a semiconductor device, which comprises a substrate 201 and a gate structure positioned above the substrate 201, wherein the gate structure comprises a first insulating layer 202, a semiconductor layer 203, a barrier layer 204, a metal layer 205 and a third insulating layer 209 which are sequentially stacked and arranged above the substrate 201; the size of the lower surface of the semiconductor layer 203 is larger than the size of the upper surface of the semiconductor layer 203, and the metal layer 205 completely covers the semiconductor layer 203. In this application at least cover (shelter from) the uncontrolled semiconductor layer of slope angle 203 through metal level 205 for the marginal dimension of gate structure mainly is easily controlled by the slope angle and the great metal level 205 of etching slope angle decides, even the slope angle of semiconductor layer 203 is uncontrolled, can not influence follow-up appearance and the position in the doping region that both sides formed yet, the appearance that has significantly reduced the doping region and the short circuit problem that the position is uncontrolled leads to.
EXAMPLE III
On the basis of the first embodiment or the second embodiment, as shown in fig. 8, an embodiment of the present application provides a method for manufacturing a semiconductor device, including:
step S110: a substrate 201 is provided.
Step S120: forming a gate structure above a substrate 201, wherein the gate structure comprises a first insulating layer 202, a semiconductor layer 203, a barrier layer 204 and a metal layer 205 which are sequentially stacked and arranged above the substrate 201; wherein the size of the lower surface of the semiconductor layer 203 is larger than the size of the upper surface of the semiconductor layer 203, and the metal layer 205 completely covers the semiconductor layer 203.
The size of the lower surface of the semiconductor layer 203 is larger than the size of the upper surface of the semiconductor layer 203, that is, the slope angle of the semiconductor layer 203 is smaller than 90 degrees.
Of the barrier layer 204 and the metal layer 205, at least the metal layer 205 completely covers the semiconductor layer 203, that is, an orthographic projection of the metal layer 205 on the substrate 201 at least completely covers an orthographic projection of the semiconductor layer 203 on the substrate 201.
The barrier layer 204 may also completely cover the semiconductor layer 203, i.e. an orthographic projection of the barrier layer 204 on the substrate 201 at least completely covers an orthographic projection of the semiconductor layer 203 on the substrate 201.
That is to say, in this embodiment, the semiconductor layer 203 with an uncontrolled slope angle is covered (shielded) by at least the metal layer 205, so that the edge size of the gate structure is mainly determined by the metal layer 205 with an easily controlled slope angle and a large etching slope angle, and even if the slope angle of the semiconductor layer 203 is uncontrolled, the shape and position of the doped region formed at both sides subsequently cannot be affected, and the short circuit problem caused by the uncontrolled shape and position of the doped region is greatly reduced.
The size of the upper surface of the first insulating layer 202 is not smaller than the size of the lower surface of the semiconductor layer 203, and the upper surface of the first insulating layer 202 completely covers the lower surface of the semiconductor layer 203.
The first insulating layer 202 may be aligned with the semiconductor layer 203, or may extend outside the semiconductor layer 203.
The size of the lower surface of the barrier layer 204 is not smaller than the size of the upper surface of the semiconductor layer 203, and the lower surface of the barrier layer 204 completely covers the upper surface of the semiconductor layer 203, and in some cases, the lower surface of the barrier layer 204 may extend outside the upper surface of the semiconductor layer 203.
The upper surface of the barrier layer 204 has a larger dimension than the lower surface of the barrier layer 204. That is, the slope angle of barrier layer 204 is greater than 90 degrees.
A concave structure is formed at the interface of the barrier layer 204 and the semiconductor layer 203, which is more beneficial to shielding the semiconductor layer 203 from the barrier layer 204.
The size of the upper surface of the barrier layer 204 may also be not smaller than the size of the lower surface of the semiconductor layer 203, so that the barrier layer 204 can block the semiconductor layer 203, that is, the orthographic projection of the barrier layer 204 on the substrate 201 can cover the orthographic projection of the semiconductor layer 203 on the substrate 201.
The size of the lower surface of the metal layer 205 is not larger than the size of the upper surface of the barrier layer 204, and the upper surface of the barrier layer 204 covers the lower surface of the metal layer 205, that is, the lower surface of the metal layer 205 may cover a part of or the whole upper surface of the barrier layer 204.
The size of the upper surface of the metal layer 205 is not greater than the size of the lower surface of the metal layer 205. That is, the slope angle of the metal layer 205 is 90 degrees or less.
The size of the lower surface of the metal layer 205 is not smaller than the size of the lower surface of the semiconductor layer 203, so that the metal layer 205 can shield the semiconductor layer 203, that is, the orthographic projection of the metal layer 205 on the substrate 201 can cover the orthographic projection of the semiconductor layer 203 on the substrate 201.
Step S130: a second insulating layer 206 is formed to wrap the sides of the gate structure.
Wherein the second insulating layer 206 includes:
a first portion 2061 wrapping the side surface of the semiconductor layer 203;
a second portion 2062, coating the side of the barrier layer 204 and the side of the metal layer 205.
The maximum lateral distance between the outer edge of the first portion 2061 and the bottom edge of the semiconductor layer 203 is not less than the maximum lateral distance between the outer edge of the second portion 2062 and the bottom edge of the semiconductor layer 203.
The second insulating layer 206 covers the sides and top surface of the gate structure.
The second insulating layer 206 includes: a first portion 2061 and a second portion 2062.
The first portion 2061 wraps around the side of the semiconductor layer 203.
The second portion 2062 wraps around the side of the barrier layer 204 and the side of the metal layer 205.
The maximum lateral distance D1 between the outer edge of the first portion 2061 and the bottom edge of the semiconductor layer 203 is not less than the maximum lateral distance D2 between the outer edge of the second portion 2062 and the bottom edge of the semiconductor layer 203, i.e., D1 is not less than D2.
The thickness of the first portion 2061 is greater than the thickness of the second portion 2062.
The second insulating layer 206 may also include a third portion 2063 that wraps around the top surface of the gate structure.
The maximum lateral distance between the outer edge of the first portion 2061 and the bottom edge of the semiconductor layer 203 is not less than the maximum lateral distance between the outer edge of the first insulating layer 202 and the bottom edge of the semiconductor layer 203. That is, when the first insulating layer 202 is aligned with the semiconductor layer 203, the first portion 2061 of the second insulating layer 206 covers the side surface of the first insulating layer 202, and when the first insulating layer 202 extends out of the semiconductor layer 203, the first portion 2061 of the second insulating layer 206 covers at least the upper surface of the outer portion of the first insulating layer 202 extending out of the semiconductor layer 203, and may even cover the upper surface and the side surface of the outer portion of the first insulating layer 202 extending out of the semiconductor layer 203.
Step S140: forming a first doped region 207 and a second doped region 208 respectively positioned at two sides of the first insulating layer 202 in the upper surface of the substrate 201; wherein, neither the first insulating layer 202 nor the second insulating layer 206 covers the first doped region 207 nor the second doped region 208.
The first doped region 207 and the second doped region 208 are disposed in the upper surface of the substrate 201 and located on two sides of the first insulating layer 202, respectively, wherein the first insulating layer 202 and the second insulating layer 206 do not cover the first doped region 207 and the second doped region 208.
Although the ion implantation mask in the process of forming the first doped region 207 and the second doped region 208 is the second insulating layer 206, the shape and size of the second insulating layer 206 depend on the shape and size of the gate structure, so that in this embodiment, at least the metal layer 205 covers (shields) the semiconductor layer 203 with an uncontrolled slope angle, so that the edge size of the gate structure is mainly determined by the metal layer 205 with an easily controlled slope angle and a large etching slope angle, and even if the slope angle of the semiconductor layer 203 is not controlled, the shape and position of the doped regions formed at two sides subsequently cannot be affected, thereby greatly reducing the short circuit problem caused by the uncontrolled shape and position of the doped regions.
In this embodiment, the semiconductor device may be a transistor.
In some cases, the gate structure further comprises: a third insulating layer 209 over the metal layer 205.
The size of the lower surface of the third insulating layer 209 is not greater than the size of the upper surface of the metal layer 205, and the upper surface of the metal layer 205 covers the lower surface of the third insulating layer 209.
The size of the upper surface of the third insulating layer 209 is not greater than the size of the lower surface of the third insulating layer 209. That is, the slope angle of the metal layer 205 is 90 degrees or less.
The third insulating layer 209 may further achieve protection of the metal layer 205.
The embodiment of the application provides a method for manufacturing a semiconductor device, which comprises the steps of providing a substrate 201; forming a gate structure over a substrate 201; wherein, forming a gate structure over the substrate 201 comprises the following steps: a first insulating layer 202, a semiconductor layer 203, a barrier layer 204 and a metal layer 205 which are stacked are sequentially formed above a substrate 201; wherein the size of the lower surface of the semiconductor layer 203 is larger than the size of the upper surface of the semiconductor layer 203, and the metal layer 205 covers the semiconductor layer 203. In this application at least cover (shelter from) the uncontrolled semiconductor layer of slope angle 203 through metal level 205 for the marginal dimension of gate structure mainly is easily controlled by the slope angle and the great metal level 205 of etching slope angle decides, even the slope angle of semiconductor layer 203 is uncontrolled, can not influence follow-up appearance and the position in the doping region that both sides formed yet, the appearance that has significantly reduced the doping region and the short circuit problem that the position is uncontrolled leads to.
Although the embodiments disclosed in the present application are described above, the embodiments are merely used for the understanding of the present application, and are not intended to limit the present application. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims.
Claims (14)
1. A semiconductor device, comprising: the gate structure comprises a substrate and a gate structure positioned above the substrate;
the grid structure comprises a first insulating layer, a semiconductor layer, a barrier layer and a metal layer which are sequentially arranged above the substrate in a laminated manner;
wherein the size of the lower surface of the semiconductor layer is larger than the size of the upper surface of the semiconductor layer, and the metal layer completely covers the semiconductor layer.
2. The semiconductor device according to claim 1, further comprising: the second insulating layer wraps the side face of the grid structure;
the second insulating layer includes:
the first part wraps the side face of the semiconductor layer;
the second part wraps the side surface of the barrier layer and the side surface of the metal layer;
wherein a maximum lateral distance between an outer edge of the first portion and a bottom edge of the semiconductor layer is not less than a maximum lateral distance between an outer edge of the second portion and the bottom edge of the semiconductor layer.
3. The semiconductor device according to claim 2, wherein a thickness of the first portion is larger than a thickness of the second portion.
4. The semiconductor device according to claim 2, wherein a maximum lateral distance between an outer edge of the first portion and a bottom edge of the semiconductor layer is not less than a maximum lateral distance between an outer edge of the first insulating layer and the bottom edge of the semiconductor layer.
5. The semiconductor device according to claim 1, wherein a size of an upper surface of the first insulating layer is not smaller than a size of a lower surface of the semiconductor layer, and wherein the upper surface of the first insulating layer completely covers the lower surface of the semiconductor layer.
6. The semiconductor device according to claim 1, wherein a size of a lower surface of the barrier layer is not smaller than a size of an upper surface of the semiconductor layer, and the lower surface of the barrier layer completely covers the upper surface of the semiconductor layer.
7. The semiconductor device of claim 6, wherein a size of an upper surface of the barrier layer is larger than a size of a lower surface of the barrier layer.
8. The semiconductor device according to claim 7, wherein a size of an upper surface of the barrier layer is not smaller than a size of a lower surface of the semiconductor layer.
9. The semiconductor device of claim 1, wherein a size of a lower surface of the metal layer is not greater than a size of an upper surface of the barrier layer, and the upper surface of the barrier layer completely covers the lower surface of the metal layer.
10. The semiconductor device according to claim 9, wherein a size of an upper surface of the metal layer is not larger than a size of a lower surface of the metal layer.
11. The semiconductor device according to claim 2, further comprising:
the first doping area and the second doping area are arranged in the upper surface of the substrate and are respectively positioned on two sides of the first insulating layer;
wherein neither the first insulating layer nor the second insulating layer covers the first doped region nor the second doped region.
12. The semiconductor device of claim 1, wherein the gate structure further comprises:
a third insulating layer over the metal layer.
13. The semiconductor device according to claim 12, wherein a size of a lower surface of the third insulating layer is not larger than a size of an upper surface of the metal layer, and the upper surface of the metal layer completely covers the lower surface of the third insulating layer.
14. The semiconductor device according to claim 13, wherein a size of an upper surface of the third insulating layer is not larger than a size of a lower surface of the third insulating layer.
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| CN202121812563.2U CN216213473U (en) | 2021-08-04 | 2021-08-04 | Semiconductor device with a plurality of transistors |
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| CN202121812563.2U CN216213473U (en) | 2021-08-04 | 2021-08-04 | Semiconductor device with a plurality of transistors |
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