CN113629079A - Display substrate, manufacturing method thereof and display device - Google Patents
Display substrate, manufacturing method thereof and display device Download PDFInfo
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- CN113629079A CN113629079A CN202111002703.4A CN202111002703A CN113629079A CN 113629079 A CN113629079 A CN 113629079A CN 202111002703 A CN202111002703 A CN 202111002703A CN 113629079 A CN113629079 A CN 113629079A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 229
- 239000002184 metal Substances 0.000 claims abstract description 229
- 238000000034 method Methods 0.000 claims description 27
- 230000002093 peripheral effect Effects 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 23
- 238000000059 patterning Methods 0.000 claims description 23
- 238000004806 packaging method and process Methods 0.000 claims description 10
- 239000007788 liquid Substances 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 7
- 239000010936 titanium Substances 0.000 description 23
- 229910052719 titanium Inorganic materials 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 10
- 229910052782 aluminium Inorganic materials 0.000 description 9
- 230000000903 blocking effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000013461 design Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
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- 230000002411 adverse Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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Abstract
The display substrate comprises a substrate, a source drain metal layer, a flat layer and an electrode layer, wherein the source drain metal layer, the flat layer and the electrode layer are sequentially arranged from one side close to the substrate to the side far away from the substrate; the shielding pattern directly covers at least part of the second source drain metal pattern and is arranged along the pattern edge of the second source drain metal pattern. The display substrate, the manufacturing method thereof and the display device can solve the technical problem that the source and drain metal patterns are poor due to side defects when the electrode layer is etched.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display substrate, a manufacturing method of the display substrate and a display device.
Background
In the related art, an array substrate of a display panel includes a substrate, and a source-drain metal layer and an electrode layer located on the substrate, where the source-drain metal layer includes a source, a drain, a data line, and various source-drain metal patterns (e.g., terminals and traces of a binding line, and a package base pattern) located in a binding region, and the electrode layer is located on one side of the source-drain metal layer away from the substrate.
When the array substrate is manufactured, firstly, a source drain metal layer is formed on a substrate, the source drain metal layer is made of a metal layer through patterning, and the metal layer generally adopts a titanium (Ti) -aluminum (Al) -titanium laminated structure; then, covering an insulating layer behind the source drain metal layer, wherein the insulating layer is covered on the source drain metal layer only in the display area after being subjected to patterning treatment, and the source drain metal pattern in the binding area is not covered with the insulating layer; then, an electrode layer is manufactured, an insulating layer exists between a source drain metal layer and the electrode layer of the display area, for the binding area, the electrode layer directly covers the source drain metal pattern, and due to the fact that the patterning process of the electrode layer comprises an exposure etching process, the etching rate of aluminum metal is higher than that of titanium metal, the problem that lateral etching of the patterned source drain metal pattern is serious easily occurs, and therefore bright spots are bad is caused.
Disclosure of Invention
The embodiment of the disclosure provides a display substrate, a manufacturing method thereof and a display device, which can solve the technical problem that side defects occur in source and drain metal patterns during electrode layer etching to cause defects.
The technical scheme provided by the embodiment of the disclosure is as follows:
the embodiment of the disclosure provides a display substrate, which comprises a substrate, a source drain metal layer, a flat layer and an electrode layer, wherein the source drain metal layer, the flat layer and the electrode layer are sequentially arranged on one side close to the substrate and far away from the substrate, the source drain metal layer at least comprises a first source drain metal pattern covered by the flat layer and a second source drain metal pattern not covered by the flat layer, the electrode layer comprises an electrode pattern and a shielding pattern, and the electrode pattern is positioned on the flat layer; the shielding pattern directly covers at least part of the second source drain metal pattern and is arranged along the pattern edge of the second source drain metal pattern.
Illustratively, the second source-drain metal pattern comprises a first metal layer, a second metal layer and a third metal layer which are sequentially arranged from one side close to the substrate to one side far away from the substrate, the etching rate of the second metal layer in etching under a preset etching liquid is greater than that of the third metal layer, the second metal layer comprises a side surface which is not covered by the third metal layer, and the shielding pattern at least covers the side surface of the second metal layer.
Illustratively, the blocking pattern covers the second source-drain metal pattern in a conformal manner, and the blocking pattern includes:
the first shielding area covers the surface of one side, far away from the substrate base plate, of the third metal layer;
a second shielding region covering a side surface of the second metal layer;
and the third shielding area covers the side face of the first metal layer, and is formed by extending one side of the side face shielding area, which is far away from the first shielding area, along the direction parallel to the substrate base plate.
For example, an orthographic projection of the first shielding region on the substrate base plate completely covers a side surface, far away from the substrate base plate, of the third metal layer.
Illustratively, the first shielding region is provided with a hollow pattern so as to expose at least a partial region of the surface of one side of the third metal layer, which is far away from the substrate base plate, and the pattern shape of the hollow pattern is along the pattern edge shape of the second source drain metal pattern.
Illustratively, the display substrate includes a display region and a peripheral region located at the periphery of the display region, and the second source-drain metal pattern is located at the peripheral region.
Illustratively, the peripheral region includes a bonding region and a package substrate region, and the second source-drain metal pattern includes:
the binding circuit is positioned in the binding area and comprises a terminal and a binding wire;
and/or a package substrate pattern located in the package substrate region.
The embodiment of the disclosure also provides a display device, which comprises the display substrate provided by the embodiment of the disclosure.
The embodiment of the present disclosure further provides a method for manufacturing a display substrate, for manufacturing the display substrate of the embodiment of the present disclosure, the method includes:
providing a substrate base plate;
sequentially forming a source drain metal layer, a flat layer and an electrode layer on the substrate, wherein the source drain metal layer at least comprises a first source drain metal pattern covered by the flat layer and a second source drain metal pattern not covered by the flat layer, the electrode layer comprises an electrode pattern and a shielding pattern, and the electrode pattern is positioned on the flat layer; the shielding pattern directly covers at least part of the second source drain metal pattern and is arranged along the pattern edge of the second source drain metal pattern.
In an exemplary embodiment, the method sequentially forms a source drain metal layer, a planarization layer, and an electrode layer on the substrate, and specifically includes:
forming a source drain metal layer on the substrate, and patterning the source drain metal layer to form a first source drain metal pattern and a second source drain metal pattern;
forming a flat layer on the source drain metal layer, wherein the flat layer is positioned on the first source drain metal pattern and does not cover the second source drain metal pattern;
and forming an electrode layer on the flat layer, and performing patterning treatment on the electrode layer to form the electrode pattern and the shielding pattern.
The beneficial effects brought by the embodiment of the disclosure are as follows:
in the display substrate, the manufacturing method thereof and the display device provided by the embodiment of the disclosure, the shielding pattern formed by the electrode layer is arranged on the part, which is not covered by the flat layer, of the source-drain metal layer, namely, on the second source-drain metal pattern, and the shielding pattern is arranged along the edge of the second source-drain metal pattern, so that in the patterning process of the electrode layer, after the whole electrode layer is formed, when the electrode layer is subjected to etching process patterning treatment, the photoresist above the electrode layer is subjected to patterning design, so that the electrode layer above the edge of the second source-drain metal pattern is covered and protected by the photoresist, the edge of the second source-drain metal pattern is protected from being etched, namely, the side surface of the second source-drain metal pattern is not etched, and the problem that the side surface of the source-drain metal pattern is sunken to cause badness in the related technology is solved.
Drawings
Fig. 1 is a schematic structural diagram of an optical glue above a second source-drain metal pattern when a patterning process is performed on an electrode layer of a display substrate provided in some embodiments of the present disclosure;
fig. 2 is a schematic structural view of a shielding pattern over a second source-drain pattern of a display substrate provided in some embodiments of the present disclosure;
fig. 3 is a schematic structural diagram of an optical glue above a second source-drain metal pattern when a patterning process is performed on an electrode layer on a display substrate provided in other embodiments of the present disclosure;
fig. 4 is a schematic structural diagram illustrating a shielding pattern above a second source/drain pattern of a display substrate according to another embodiment of the present disclosure;
FIG. 5 is a schematic diagram illustrating the size and structure of two adjacent terminals of a bonding area of a display substrate according to the related art;
FIG. 6 is a schematic diagram illustrating the size and structure of two adjacent terminals in the bonding region of the display substrate in the embodiment shown in FIG. 2;
FIG. 7 is a schematic diagram illustrating the size and structure of two adjacent terminals in the bonding region of the display substrate in the embodiment shown in FIG. 4;
FIG. 8 is a schematic diagram illustrating a local wiring structure of a bonding region and a package base region of a display substrate according to an embodiment of the disclosure;
fig. 9 illustrates a schematic partial cross-sectional structure of a display substrate at a terminal of a bonding region in an embodiment of the present disclosure;
fig. 10 is a schematic partial cross-sectional view of a display substrate in an area of a package substrate according to an embodiment of the disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
Before the detailed description of the display substrate, the method for manufacturing the same, and the display device provided in the embodiments of the present disclosure, it is necessary to describe the following related art:
in the related art, the display substrate includes a source-drain metal layer, a planarization layer, and an electrode layer sequentially arranged from bottom to top, where the pattern of the source-drain metal layer mainly includes a first source-drain metal pattern located in the display region, such as signal lines like a source and a drain of a thin film transistor, and a data line, and a second source-drain metal pattern is further provided in the peripheral region, such as: terminals and bonding wires of the bonding wires, the package substrate pattern, and peripheral signal wires, such as peripheral VSS wires.
The disclosure of the present invention finds, through research, that the planarization layer mainly plays a role of insulating between the source and drain metal layers and the electrode layer and providing a planarization surface for the electrode layer, and the electrode layer is generally only disposed in the display region, so the planarization layer is generally patterned to cover the display region, so the source and drain metal layers in the display region are covered by the planarization layer, and a portion of the source and drain metal pattern in the peripheral region is not covered by the planarization layer, for the source and drain metal pattern not covered by the planarization layer, before the electrode layer is unpatterned in the electrode layer process, the electrode layer is directly covered on the source and drain metal pattern, when the electrode layer is exposed and etched, since the source and drain metal pattern generally includes a stack of titanium and aluminum, the etching rates of titanium and aluminum are different, so that a recess may occur on the side surface of the source and drain metal pattern, for example, when the source and drain metal layer adopts a stack structure of titanium (Ti) -aluminum (Al) -titanium (Ti), defects such as various grooves are easily generated on the side surface of the aluminum layer in the source-drain metal pattern, so that the titanium layer positioned above the aluminum layer is protruded and may fall to the display area to cause a bad phenomenon.
In order to solve the above problems, if a planarization layer is also disposed on the second source-drain metal pattern in the peripheral region, the planarization layer has a large thickness and is not suitable for the requirement of the peripheral region such as the bonding region on the thickness, and if the planarization layer wants to reduce the thickness in the peripheral region, the patterning process of the planarization layer is complicated, and the planarization layer is close to the edge and can cause moisture.
Based on the above problems, the embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device, which can solve the technical problem that a source-drain metal pattern has a side defect during electrode layer etching, which results in a defect.
Fig. 2, fig. 4, fig. 9 and fig. 10 are schematic partial structural views of a display substrate according to an embodiment of the disclosure.
As shown in fig. 2, 4, 9, and 10, an embodiment of the present disclosure provides a display substrate including: the semiconductor device comprises a substrate 100, a source drain metal layer, a flat layer and an electrode layer, wherein the source drain metal layer, the flat layer and the electrode layer are sequentially arranged from one side close to the substrate 100 to the side far away from the substrate 100, and the source drain metal layer at least comprises a first source drain metal pattern (not shown in the figure) covered by the flat layer and a second source drain metal pattern 400 not covered by the flat layer; wherein the electrode layer comprises an electrode pattern (not shown) and a shielding pattern 300, the electrode pattern is located on the planarization layer; the shielding pattern 300 directly covers at least a portion of the second source-drain metal pattern 400, and is disposed along a pattern edge of the second source-drain metal pattern 400. In the above-mentioned solution, the shielding pattern 300 formed by the electrode layer is disposed on the portion of the source-drain metal layer not covered by the planarization layer, that is, on the second source-drain metal pattern 400, and the shielding pattern 300 is disposed along the edge of the second source-drain metal pattern 400, so that, in the patterning process of the electrode layer, after the entire electrode layer is formed, when the electrode layer is subjected to the etching process patterning treatment, the electrode layer above the edge of the second source-drain metal pattern 400 is retained to form the shielding pattern 300, specifically, the photoresist 600 above the electrode layer is subjected to the patterning design, so that the electrode layer photoresist 600 above the edge of the second source-drain metal pattern 400 is covered and protected to retain the electrode layer to form the shielding pattern 300, thereby shielding the edge of the second source-drain metal pattern 400 from being etched, so that the side surface of the second source-drain metal pattern 400 is not etched, therefore, the problem that the side surface of the source-drain metal pattern is sunken to cause defects in the related art is solved.
It should be noted here that the shielding pattern 300 is disposed along the pattern edge of the second source-drain metal pattern 400, which means that the shielding pattern 300 covers at least the side surface of the second source-drain metal pattern 400, and the shape of the shielding pattern 300 is matched with the shape of the second source-drain metal pattern 400, which does not adversely affect the function of the second source-drain metal pattern 400, for example, when the second source-drain metal pattern 400 includes a terminal in a binding region, a shielding pattern covered above the second source-drain metal pattern 400 is disposed along the shape of the edge of the terminal, so that finally, the pattern of the terminal is still maintained in the pattern of the stacked structure formed by the second source-drain metal pattern 400 and the shielding pattern 300.
The technical solutions provided by the embodiments of the present disclosure are explained in more detail below.
In the display substrate provided by the present disclosure, the second source-drain metal pattern 400 includes a first metal layer 410, a second metal layer 420, and a third metal layer 430, which are sequentially disposed from a side close to the substrate 100 to a side far from the substrate 100, an etching rate of the second metal layer 420 when etching is performed under a preset etching liquid is greater than an etching rate of the third metal layer 430, the second metal layer 420 includes a side not covered by the third metal layer 430, and the shielding pattern 300 covers at least the side of the second metal layer 420.
With the above scheme, the second source-drain metal pattern 400 may be a three-layer metal stacked structure, where an etching rate of the second metal layer 420 located in the middle layer is greater than an etching rate of the third metal layer 430 located above the second metal layer during etching of the electrode layer, and in some embodiments, the stacked structure of the second source-drain metal pattern 400 may be a titanium (Ti) -aluminum (Al) -titanium (Ti) stacked structure, that is, the first metal layer 410 is a titanium (Ti) layer, the second metal layer 420 is an aluminum (Al) layer, and the third metal layer 430 is a titanium (Ti) layer. It should be noted that, the above is only an example of the stacked structure of the second source/drain metal pattern 400, and in practical applications, the stacked structure of the second source/drain metal pattern 400 is not limited thereto.
In some exemplary embodiments of the present disclosure, the blocking pattern 300 covers the second source drain metal pattern 400 in a conformal manner, and the blocking pattern 300 includes: a first shielding region 310 covering a surface of the third metal layer 430 on a side away from the substrate base plate 100; a second blocking region 320 covering a side of the second metal layer 420; and a third shielding region 330 covering a side surface of the first metal layer 410, wherein the third shielding region 330 is formed by extending a side surface of the side shielding region far from the first shielding region 310 along a direction parallel to the substrate 100.
In the above solution, the blocking pattern 300 is covered on the second source/drain metal pattern 400 in a conformal manner, and at least a portion of the blocking pattern is covered on the upper surface of the third metal layer 430 (i.e. the surface of the third metal layer 430 on the side away from the substrate 100), that is, the first blocking region 310; at least one part covers the side of the second metal layer 420, that is, the second shielding region 320; at least a portion of the third metal layer 430 covers the lateral surface and extends outward for a distance, i.e., the third shielding region 330.
Fig. 3 and 4 and 7 are schematic views of an occlusion pattern 300 in some embodiments of the present disclosure. As shown in fig. 3, 4 and 7, in some embodiments, an orthographic projection of the first shielding region 310 on the substrate base plate 100 completely covers a side surface of the third metal layer 430 far from the substrate base plate 100.
In this embodiment, in the electrode layer patterning process, the photoresist 600 includes a reserved region and a removed region, and by designing the reserved region and the removed region pattern of the photoresist 600, taking the photoresist 600 as a positive photoresist as an example, an orthographic projection of the reserved region of the photoresist 600 on the substrate base plate 100 completely covers an orthographic projection of the second source-drain metal pattern 400 on the substrate base plate 100, so that the electrode layer finally forms the shielding pattern 300.
Fig. 1, 2 and 6 are schematic views illustrating a shielding pattern 300 according to other embodiments of the present disclosure. As shown in fig. 1, fig. 2 and fig. 6, in other embodiments, the first blocking region 310 has a hollow pattern 311 thereon to expose at least a partial region of a side surface of the third metal layer 430 far from the substrate 100, and a pattern shape of the hollow pattern 311 is along a pattern edge shape of the second source-drain metal pattern 400.
In the above scheme, the first shielding region 310 has the hollow pattern 311, and the pattern shape of the hollow pattern 311 is along the pattern edge shape of the second source-drain metal pattern 400, that is, the first shielding region 310 divides the shielding pattern 300, and only the edge of the second source-drain metal pattern 400 is shielded.
In addition, in some embodiments, the display substrate includes a display area AA and a peripheral area located at the periphery of the display area AA, the first source-drain metal pattern is located in the display area AA (not shown in the figure), and the second source-drain metal pattern 400 is located in the peripheral area.
For the display substrate, as shown in fig. 8, the peripheral area mainly includes a bonding area C and a package base area b (frit sub) located between the bonding area C and a display area AA (not shown in the figure), a bonding line is arranged in the bonding area C, the bonding line includes a terminal 1 and a bonding trace 4, and the peripheral area may further include some peripheral traces 2, for example, Vss, Vdd traces, and the like.
As shown in fig. 8, the bonding lines include a plurality of terminals 1 and bonding traces 4 connected to the terminals, the terminals 1 may be sequentially arranged in at least one row, at least one terminal 1 is connected to at least one bonding trace 4, and a Vss trace or a Vdd trace is disposed at an end of a bonding region, where the Vss trace may be disposed around a display region.
The packaging substrate region B is used for setting a packaging substrate pattern, the packaging substrate pattern 3 may include a substrate portion 31 and a plurality of openings 32 on the substrate portion 31, the packaging substrate pattern is used for providing a substrate for packaging when the display substrate is packaged, and the openings on the packaging substrate pattern facilitate the integration of the packaging material on the upper layer of the packaging substrate pattern and the material on the lower layer of the packaging substrate pattern, thereby improving the packaging effect.
In some embodiments, the Vss traces may be routed from one end of the bonding area, and extend around the periphery of the display area AA to connect to the other end of the bonding area.
In some embodiments, the peripheral signal traces such as Vss and Vdd may be made of the same material as the layer of the package substrate pattern 3 and integrally connected to the same layer, for example, both are made of a source and drain metal layer material, that is, the package substrate pattern may also be reused as peripheral signal traces such as Vss and Vdd.
In the display substrate provided by the embodiment of the present disclosure, the second source-drain metal pattern 400 may include the above-mentioned bonding lines, such as the terminal 1 and the bonding trace 4, and may further include the peripheral trace 2 and the package substrate pattern 3.
It should be understood that, for the display substrate, the peripheral signal traces or other source and drain patterns formed by patterning the source and drain metal layer, which are disposed in the peripheral region of the display substrate, are all the second source and drain metal patterns 400, that is, the peripheral signal traces or other source and drain patterns formed by patterning the source and drain metal layer, which are disposed in the peripheral region of the display substrate, may have a shielding pattern formed by forming an electrode layer above them.
In addition, the display substrate further includes a gate layer 500, and the pattern of the gate layer 500 includes a gate, a gate line, and other patterns. An orthographic projection of the bonding wire on the substrate base plate 100 can at least partially coincide with an orthographic projection of the gate layer on the substrate base plate 100; an orthogonal projection of the package base pattern on the substrate base plate 100 may at least partially coincide with an orthogonal projection of the gate layer on the substrate base plate 100, and at least partially do not coincide with the orthogonal projection.
Taking the second source-drain metal pattern 400 including the terminal in the bonding line of the display substrate as an example, fig. 9 is a schematic cross-sectional structure diagram of a connection portion where the terminal and the gate pass through the via hole, and fig. 2, 4, and 6 to 7 are schematic cross-sectional structure diagrams of a connection portion where the terminal and the gate do not pass through the via hole.
As shown in fig. 9, the binding region C of the substrate 100 includes a gate layer 500, a gate insulating layer 700, a source-drain metal layer and an electrode layer, which are sequentially disposed from bottom to top, wherein a pattern of the source-drain metal layer is a second source-drain metal pattern 400, the gate layer 500 is overlapped through a via hole, and a shielding pattern 300 is covered on an edge of the second source-drain metal pattern 400.
As shown in fig. 10, the package substrate region B of the substrate 100 includes a gate insulating layer 700, a source-drain metal layer, and an electrode layer, which are sequentially disposed from bottom to top, where a pattern of the source-drain metal layer is a second source-drain metal pattern 400, and a shielding pattern 300 covers an edge of the second source-drain metal pattern 400.
The second source-drain metal pattern 400 covers the shielding pattern 300, the original function of the second source-drain metal pattern is not affected, and the following description is made on the size of the second source-drain metal pattern 400 after the shielding pattern 300 is arranged, in consideration of the line width and other factors of the terminal, the wiring and the like:
taking the terminal 1 in the second source-drain metal pattern in the related art as an example, as shown in fig. 5, the length of the terminal 1 of the bonding line in the related art is f1Width of c1At an interval of e1 E.g. length f 1600 μm, width c112 μm at e1＝10μm。
In the embodiment shown in fig. 6, the gap e between the shielding patterns on two adjacent terminals2＝e1The distance d ═ c between the edges of the opposite sides of the shielding pattern 300 on the same terminal1In the shielding pattern 300 of the same terminal, the first shielding region is divided into two sub-regions by the hollow pattern, the widths of the two sub-regions are the same and are both b, the sum of the widths of the two sub-regions and the hollow pattern is c, the width of the third sub-region is a, d is 2a + c, and the length f of the shielding pattern 300 is f1By a length f 1600 μm, width c112 μm at e1For example, when d is 12 μm, c is 9 μm, a is 1.5 μm, b is 1.5 μm, and f is 600 μm. The values of a, b, c and d can be adjusted according to the performance accuracy of different exposure machines, but are not limited thereto.
In the embodiment shown in FIG. 7, the gap e between the shielding patterns on two adjacent terminals3＝e1The distance d' c between the edges of the shielding pattern 300 on the same terminal is larger than the distance d ═ c between the edges of the shielding pattern 300 on the opposite sides1If the width of the first light-shielding region in the shielding pattern 300 of the same terminal is c ', the width of the third sub-region is a ', and d ' is 2a ' + c ', the length f of the shielding pattern 300 is f2＝f1By a length f 1600 μm, width c112 μm at e1For example, when d ' is 12 μm, c ' is 9 μm, and a ' is 1.5 μm. The values of a ', b', c 'and d' can be adjusted according to the performance accuracy of different exposure machines, but are not limited thereto。
It should be noted that, for the second source-drain metal pattern 400 in the peripheral region of the display substrate, for example, signal traces such as terminals, bonding traces, VDD traces, VSS traces, and the like, the signal traces also have a signal transmission function. The shielding pattern 300 is disposed above the second source-drain metal pattern 400 in the display substrate provided in the embodiment of the present disclosure, and compared with a scheme in which only the second source-drain metal pattern is adopted and only the source-drain metal layer is adopted in the related art, since the pattern size finally formed by the second source-drain metal pattern and the shielding pattern above the second source-drain metal pattern corresponds to (is substantially the same as) the original pattern size obtained by only adopting the source-drain metal layer, the change of a signal is not very little affected, and normal signal transmission is not affected.
It should be noted that, the above description is only given by taking the terminal pattern in the second source-drain pattern as an example, for the trace, the package substrate pattern, and the like, the final sizes of the shielding pattern 300 and the second source-drain metal pattern 400 should be reasonably designed according to the performance precision of the exposure machine, the wiring requirement, and the like.
In addition, the embodiment of the disclosure also provides a display device which comprises the display substrate provided by the embodiment of the disclosure. The display device may include various display devices such as a mobile phone, a tablet computer, a display, and the like.
In addition, the embodiment of the present disclosure also provides a method for manufacturing a display substrate, for manufacturing the display substrate of the embodiment of the present disclosure, the method includes:
step S01, providing a base substrate 100;
step S02, sequentially forming a source-drain metal layer, a planarization layer, and an electrode layer on the substrate 100, where the source-drain metal layer at least includes a first source-drain metal pattern covered by the planarization layer and a second source-drain metal pattern 400 not covered by the planarization layer, where the electrode layer includes an electrode pattern and a shielding pattern 300, and the electrode pattern is located on the planarization layer; the shielding pattern 300 directly covers at least a portion of the second source-drain metal pattern 400, and is disposed along a pattern edge of the second source-drain metal pattern 400.
Illustratively, in the method, step S02 specifically includes:
step S021, forming a source drain metal layer on the substrate 100, and performing patterning processing on the source drain metal layer to form the first source drain metal pattern and the second source drain metal pattern 400;
the source-drain metal layer may include a laminated structure of a first metal layer 410, a second metal layer 420, and a third metal layer 430, which are sequentially arranged from bottom to top, for example, a laminated structure of titanium (Ti) -aluminum (Al) -titanium (Ti), and after depositing each layer in sequence, performing processes such as exposure, development, etching, and the like to perform a patterning process on the source-drain metal layer, so as to form a first source-drain metal pattern and a second source-drain metal pattern 400;
step S022, forming a planarization layer on the source-drain metal layer, wherein the planarization layer is located on the first source-drain metal pattern and does not cover the second source-drain metal pattern 400;
the flat layer can play the roles of insulation and flatness, and can be an inorganic insulating layer or an organic insulating layer;
step S023, as shown in fig. 1 and 3, forming an electrode layer on the planarization layer, and performing a patterning process on the electrode layer to form the electrode pattern and the shielding pattern 300;
the electrode layer may be an anode layer, for example, an ITO layer (indium tin oxide layer) or a metal layer, and the electrode layer is deposited and covered on the substrate 100, and then an electrode layer patterning process is performed by using, for example, exposure, development, and etching, where the photoresist 600 includes a reserved region and a removed region during exposure and development, and taking the photoresist 600 as a positive photoresist as an example, the pattern of the reserved region at least covers the edge alignment position of the second source/drain metal pattern 400, so as to reserve the electrode layer above the second source/drain metal pattern 400, and form the shielding pattern 300, so as to protect the side surface of the second source/drain metal pattern 400 from being etched.
In addition, it should be noted that the display substrate provided in the embodiment of the present disclosure may further include a step of fabricating films such as a gate electrode, a gate insulating layer, and an active layer, which is not described in detail herein.
The following points need to be explained:
(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.
(2) For purposes of clarity, the thickness of layers or regions in the figures used to describe embodiments of the present disclosure are exaggerated or reduced, i.e., the figures are not drawn on a true scale. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.
(3) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.
The above is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be determined by the scope of the claims.
Claims (10)
1. A display substrate is characterized by comprising a substrate base plate, a source drain metal layer, a flat layer and an electrode layer, wherein the source drain metal layer, the flat layer and the electrode layer are sequentially arranged from one side close to the substrate base plate to the side far away from the substrate base plate; the shielding pattern directly covers at least part of the second source drain metal pattern and is arranged along the pattern edge of the second source drain metal pattern.
2. The display substrate of claim 1,
the second source-drain metal pattern comprises a first metal layer, a second metal layer and a third metal layer which are sequentially arranged from one side close to the substrate to one side far away from the substrate, the etching rate of the second metal layer in etching under a preset etching liquid is greater than that of the third metal layer, the second metal layer comprises a side face which is not covered by the third metal layer, and the shielding pattern at least covers the side face of the second metal layer.
3. The display substrate of claim 2,
the shielding pattern covers the second source drain metal pattern along with the shape, and the shielding pattern comprises:
the first shielding area covers the surface of one side, far away from the substrate base plate, of the third metal layer;
a second shielding region covering a side surface of the second metal layer;
and the third shielding area covers the side face of the first metal layer, and is formed by extending one side of the side face shielding area, which is far away from the first shielding area, along the direction parallel to the substrate base plate.
4. The display substrate of claim 3,
the orthographic projection of the first shielding area on the substrate base plate completely covers one side surface, far away from the substrate base plate, of the third metal layer.
5. The display substrate of claim 3,
the first shielding area is provided with a hollow pattern so as to expose at least part of the surface of one side of the third metal layer far away from the substrate base plate, and the pattern shape of the hollow pattern is along the pattern edge shape of the second source drain metal pattern.
6. The display substrate of claim 1,
the display substrate comprises a display area and a peripheral area located at the periphery of the display area, and the second source drain metal pattern is located in the peripheral area.
7. The display substrate of claim 6,
the peripheral region includes a binding region and a packaging substrate region, and the second source-drain metal pattern includes:
the binding circuit is positioned in the binding area and comprises a terminal and a binding wire;
and/or a package substrate pattern located in the package substrate region.
8. A display device comprising the display substrate according to any one of claims 1 to 7.
9. A method for manufacturing a display substrate, for manufacturing the display substrate according to any one of claims 1 to 7, the method comprising:
providing a substrate base plate;
sequentially forming a source drain metal layer, a flat layer and an electrode layer on the substrate, wherein the source drain metal layer at least comprises a first source drain metal pattern covered by the flat layer and a second source drain metal pattern not covered by the flat layer, the electrode layer comprises an electrode pattern and a shielding pattern, and the electrode pattern is positioned on the flat layer; the shielding pattern directly covers at least part of the second source drain metal pattern and is arranged along the pattern edge of the second source drain metal pattern.
10. The method of claim 9,
in the method, a source drain metal layer, a flat layer and an electrode layer are sequentially formed on the substrate, and the method specifically comprises the following steps:
forming a source drain metal layer on the substrate, and patterning the source drain metal layer to form a first source drain metal pattern and a second source drain metal pattern;
forming a flat layer on the source drain metal layer, wherein the flat layer is positioned on the first source drain metal pattern and does not cover the second source drain metal pattern;
and forming an electrode layer on the flat layer, and performing patterning treatment on the electrode layer to form the electrode pattern and the shielding pattern.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023159405A1 (en) * | 2022-02-24 | 2023-08-31 | 京东方科技集团股份有限公司 | Circuit board and manufacturing method therefor, functional backplane, backlight module, and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023159405A1 (en) * | 2022-02-24 | 2023-08-31 | 京东方科技集团股份有限公司 | Circuit board and manufacturing method therefor, functional backplane, backlight module, and display device |
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