CN217444401U - Trench gate field effect transistor - Google Patents

Abstract

The utility model provides a trench gate field effect transistor. The first work function layer and the second work function layer with different work functions are respectively arranged on the inner surfaces of the positions with different heights of the grid groove, the second work function layer with low work function is formed in the area overlapped with the source drain area, the problem of leakage current of a transistor device is solved, and the first work function layer and the second work function layer can be respectively prepared, so that the work functions of different film layers can be adjusted.

Description

Trench gate field effect transistor

Technical Field

The utility model relates to the field of semiconductor technology, in particular to trench gate field effect transistor.

Background

As the feature size of the field effect transistor is reduced, the feature size of the field effect transistor is also reduced rapidly, and as the feature size of the field effect transistor is reduced, the gate-induced drain leakage (GIDL) generated by the transistor in the off state or the standby state is also increased, which may have a large influence on the reliability of the transistor, cause instability of the transistor and increase the static power consumption of the transistor.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a trench gate field effect transistor improves field effect transistor's the induced drain leakage current phenomenon of grid.

The utility model provides a pair of trench gate field effect transistor, include: a gate trench formed in a substrate; a work function adjusting layer covering an inner surface of the gate trench, the work function adjusting layer including a first work function layer and a second work function layer connected to each other, the first work function layer covering the inner surface of the gate trench lower than a first height, the second work function layer covering the inner surface of the gate trench not lower than the first height, and a work function of the second work function layer being lower than a work function of the first work function layer; and a gate electrode formed in the gate trench and on the work function adjusting layer.

Optionally, the thickness of the second work function layer is greater than the thickness of the first work function layer.

Optionally, the gate electrode includes a first gate electrode and a second gate electrode connected up and down, and a top surface of the first gate electrode is higher than a top surface of the first work function layer.

Optionally, a top surface of the second gate electrode is lower than a top surface of the second work function layer.

Optionally, the top surface of the gate electrode is lower than the top position of the gate trench, and an insulating capping layer is further filled in the gate trench to cover the gate electrode.

Optionally, the trench gate field effect transistor further includes: and the source drain region is formed on the side edge of the grid groove, and the top of the first work function layer is lower than the bottom of the source drain region.

Optionally, the materials of the first work function layer and the second work function layer both include metal nitrides, and the nitrogen content in the second work function layer is higher than the nitrogen content in the first work function layer.

In the trench gate field effect transistor provided by the present invention, a first work function layer and a second work function layer having different work functions are formed on the inner surfaces of the gate trenches at different height positions, respectively, wherein the first work function layer having a high work function is formed at the lower portion of the gate trench to ensure the turn-on performance of the transistor device; and the second work function layer with low work function is formed in the region overlapped with the source drain region, so that the problem of leakage current of the transistor device is effectively solved. In addition, the first work function layer and the second work function layer can be prepared respectively, and the work functions of different film layers can be adjusted conveniently.

Drawings

Fig. 1 is a schematic flow chart of a manufacturing method of a trench gate field effect transistor according to an embodiment of the present invention.

Fig. 2-7 are schematic structural diagrams of a trench gate field effect transistor in an embodiment of the present invention during a manufacturing process thereof.

Fig. 8 is another schematic structural diagram of a trench gate field effect transistor according to an embodiment of the present invention.

Wherein the reference numbers are as follows:

100-a substrate;

200-a gate dielectric layer;

310 — first work function layer;

320-a second work function layer;

410-a first gate electrode;

420-a second gate electrode;

500-insulating capping layer;

610-a first source drain region;

620-second source drain region.

Detailed Description

The core concept of the present invention is to provide a trench gate field effect transistor, which can improve a gate induced drain leakage current (GIDL) of a transistor device on the basis of ensuring a turn-on performance of the transistor device.

The trench gate field effect transistor provided by the present invention is further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention. It will be understood that relative terms, such as "above," "below," "top," "bottom," "above," and "below," may be used in relation to various elements shown in the figures. These relative terms are intended to encompass different orientations of the elements in addition to the orientation depicted in the figures. For example, if the device were inverted relative to the view in the drawings, an element described as "above" another element, for example, would now be below that element.

The following description preferentially describes a method for manufacturing a trench gate field effect transistor, and specifically refers to fig. 1 and fig. 2 to fig. 7, where fig. 1 is a schematic flow diagram of a method for manufacturing a trench gate field effect transistor in an embodiment of the present invention, and fig. 2 to fig. 7 are schematic structural diagrams of a trench gate field effect transistor in an embodiment of the present invention during a manufacturing process thereof.

First, step S100 is performed, and referring to fig. 2 in particular, a substrate 100 is provided, and a gate trench is formed in the substrate 100, where the gate trench is used for accommodating a subsequently formed gate electrode.

Next, step S200 is performed, and referring to fig. 3 with emphasis on forming a first work function layer 310 and a first gate electrode 410 in the gate trench, where the first work function layer 310 covers an inner surface of the gate trench lower than a first height, and the first gate electrode 410 is formed on the first work function layer 310.

In this embodiment, before forming the first work function layer 310 and the first gate electrode 410, the method further includes: a gate dielectric layer 200 is formed on the inner surface of the gate trench, and the gate dielectric layer 200 may be formed, for example, by an oxidation process. And the first work function layer 310 is formed on the gate dielectric layer 200.

In a specific embodiment, the material of the first work function layer 310 may include a metal nitride, the metal nitride is specifically titanium nitride, and the work function of the first work function layer 310 is higher than 4.6eV, for example. And, the first gate electrode 410 may be a metal gate electrode, and a material of the metal gate electrode includes, for example, tungsten (W), titanium (Ti), tantalum (Ta), or the like.

The method for preparing the first work function layer 310 and the first gate electrode 410 may include the following steps.

A first step, specifically referring to fig. 2, of depositing a first work function material layer 310a on the inner surface of the gate trench; and filling the first electrode material layer 410a in the gate trench.

In a second step, referring to fig. 3 specifically, a first etching process is performed to reduce the height of the top of the first electrode material layer 410a, so that the height of the top of the first electrode material layer 410a is lower than the height of the top of the gate trench. Specifically, the first etching process may remove a portion of the first electrode material layer 410a outside the gate trench, and further etch the first electrode material layer 410a in the gate trench to reduce the height of the top of the first electrode material layer 410a, where the first electrode material layer with the reduced height constitutes the first gate electrode 410.

After the first etching process is performed to form the first gate electrode 410, a portion of the first work function material layer 310a higher than the first gate electrode 410 is exposed.

A third step, continuing to refer to fig. 3, of performing a second etching process to remove the exposed portion of the first work function material layer 310 a.

In the example shown in fig. 3, the height of the top of the first gate electrode 410 corresponds to a first height, and a portion of the first work function material layer 310a higher than the first height is removed by a second etching process, so that the top of the first work function layer 310 is flush with the top of the first gate electrode 410. However, in other embodiments, the top of the first gate electrode may be lowered to be higher than the first height by a first etching process, and the exposed portion of the first work function material layer 310a may be removed by a second etching process, and the top of the first work function material layer 310a may be further lowered to be higher than the first gate electrode 410.

Next, step S300 is performed, and referring to fig. 4-6 in particular, a second work function layer 320 and a second gate electrode 420 are formed in the gate trench.

The second work function layer 320 covers the inner surface of the gate trench not lower than the first height and is connected to the first work function layer 310, and the work function of the second work function layer 320 is lower than that of the first work function layer 310. Specifically, the second work function layer 320 and the first work function layer 310 may be formed of the same material, for example, a metal nitride including the same metal, and the nitrogen content in the second work function layer 320 may be higher than that in the first work function layer 310, so that the work function of the second work function layer 320 is lower than that of the first work function layer 310. Alternatively, the second work function layer 320 and the first work function layer 310 may be formed by using different materials, for example, the second work function layer 320 and the first work function layer 310 may be formed by using metal nitrides of different metals, respectively (that is, the material of the first work function layer 310 includes a metal nitride of a first metal, and the material of the second work function layer 320 includes a metal nitride of a second metal), as long as the work function of the second work function layer 320 is lower than that of the first work function layer 310. Wherein the work function of the first work function layer 310 may be higher than 4.6eV, and the work function of the second work function layer 320 may be lower than 4.6 eV.

In a specific example, the method for preparing the second work function layer 320 may include: referring first to fig. 4, depositing a second work function material layer 320a, the second work function material layer 320a covering a top surface of the first gate electrode 410 and an inner surface of the gate trench above a first height; next, referring to fig. 5, the portion of the second work function material layer covering the top surface of the first gate electrode 410 is removed to form the second work function layer 320, thereby exposing the top surface of the first gate electrode 410. Further, a portion of the second work function material layer 320a above a second height, which is higher than the first height and lower than the top height of the gate trench, may be removed, that is, the top of the second work function material layer is lowered to the second height. In this embodiment, the second work function layer 320 may be formed by a two-pass etching process, that is, a first etching process is used to remove a portion of the second work function material layer 320a covering the top surface of the first gate electrode, and a second etching process is used to remove a portion of the second work function material layer 320a higher than the second height.

Next, referring to fig. 6, a second gate electrode 420 is formed on the second work function layer 320, and the second gate electrode 420 is located above the first gate electrode 410 and connected to the first gate electrode 410. The method for forming the second gate electrode 420 specifically includes: filling a second electrode material layer in the gate trench; and finally, etching the second electrode material layer to reduce the top of the second electrode material layer to be not higher than the second height. That is, the top of the second gate electrode 420 is not higher than the top of the second work function layer 320.

Wherein, in the example shown in fig. 6, the top surface of the second gate electrode 420 and the top surface of the second work function layer 320 are flush. However, in other embodiments, the top surface of the second gate electrode 420 may be further lower than the top surface of the second work function layer 320.

It should be noted that in this embodiment, the second gate electrode 420 is prepared after the top height of the second work function layer 320 in the gate trench is reduced. However, in other embodiments, the height of the second work function layer 320 in the gate trench may be reduced after the second gate electrode 420 is prepared. Specifically, after removing the part of the second work function material layer covering the top surface of the first gate electrode, filling a second electrode material layer in the gate trench; then, a third etching process is performed to reduce the height of the top of the second electrode material layer to form the second gate electrode 420; then, a fourth etching process is performed to remove the second work function material layer higher than the second height, thereby forming the second work function layer 320.

In this embodiment, specifically referring to fig. 7, after forming the second gate electrode 420, the method further includes: an insulating cap layer 500 is filled in the region of the gate trench higher than the second gate electrode 420. That is, the gate electrode in the gate trench is covered with the insulating cap layer 500.

In a further aspect, the method for forming the trench gate field effect transistor further includes: source and drain regions are formed on the side of the gate trench, for example, as shown in fig. 7, a first source and drain region 610 and a second source and drain region 620 are formed on two sides of the gate trench, respectively. And the top of the first work function layer 410 is lower than the bottom of the source drain region.

Specifically, the bottom positions of the first source drain region 610 and the second source drain region 620 are lower than the top position of the second gate electrode 420, so that the second gate electrode 420 and the first source drain region 610/the second source drain region 620 have an overlapping region. At this time, the portion overlapping the first source drain region 610/the second source drain region 620 corresponds to the second work function layer 320, and the second work function layer 320 has a lower work function, which effectively improves the gate induced drain leakage current (GIDL) of the transistor device.

Based on the above-described manufacturing method, the manufactured trench gate field effect transistor is described below. Specifically, referring to fig. 7, the trench gate field effect transistor includes: a gate trench formed in a substrate 100; a work function adjusting layer covering the inner surface of the gate trench; and a gate electrode formed in the gate trench and on the work function adjusting layer.

The work function adjusting layer includes a first work function layer 310 and a second work function layer 320 that are connected to each other, the first work function layer 310 covers an inner surface of the gate trench that is lower than the first height, and the second work function layer 320 covers an inner surface of the gate trench that is not lower than the first height. The first work function layer 310 is connected to the second work function layer 320, and the work function of the second work function layer 320 is lower than that of the first work function layer 310. In this embodiment, the materials of the first work function layer 310 and the second work function layer 320 may both include metal nitride, and the nitrogen content in the second work function layer 320 is higher than that in the first work function layer 310, so that the work function of the second work function layer 320 is lower than that of the first work function layer 310. In addition, the thickness of the second work function layer 320 may be further greater than the thickness of the first work function layer 310.

With continued reference to fig. 7, the gate electrode is formed on the work function adjusting layer, which specifically includes: the first gate electrode 410 and the second gate electrode 420 are stacked from bottom to top. Wherein a sidewall of the first gate electrode 410 contacts the first work function layer 310, and a top of the first gate electrode 410 is not higher than a top of the first work function layer 310. And, the sidewall of the second gate electrode 420 contacts the second work function layer 320, and the top of the second gate electrode 420 is not higher than the top of the second work function layer 320. In this embodiment, the first gate electrode 410 and the second gate electrode 420 may be formed of the same material (for example, the materials of the first gate electrode 410 and the second gate electrode 420 both include tungsten), or may be formed of different materials.

Further, in the example shown in fig. 7, the first gate electrode 410 is flush with the top surface of the first work function layer 310, and the second gate electrode 420 is flush with the top surface of the second work function layer 320. However, in the example shown in fig. 8, the top of the first gate electrode 410 is higher than the top of the first work function layer 310, and the top of the second gate electrode 420 is lower than the top of the second work function layer 320.

Further, the trench gate field effect transistor further includes: and forming source and drain regions on the side edges of the gate trench. As shown in fig. 7, a first source drain region 610 and a second source drain region 620 are formed on two sides of the gate trench, respectively. And the bottom positions of the first source-drain region 610 and the second source-drain region 620 are lower than the top position of the second gate electrode 420, so that the second gate electrode 420 and the first source-drain region 610/the second source-drain region 620 have an overlapping region, and at this time, the portion overlapping the first source-drain region 610/the second source-drain region 620 corresponds to the second work function layer 320.

It should be noted that the first work function layer 310 with a high work function is adopted in the lower portion of the gate trench, which is beneficial to improving the turn-on performance of the device. In the region overlapping the source/drain region, the second work function layer 320 with low work function is disposed, so as to effectively improve gate induced drain leakage current (GIDL) of the transistor device.

In a further aspect, the trench gate field effect transistor as described above may also be applied to a memory to improve the performance of the memory. In this case, the memory transistor of the memory can be formed by the trench gate field effect transistor as described above.

Specifically, the memory may include a substrate having a plurality of active regions formed therein. And the memory further includes a plurality of word lines buried in the substrate, the word lines extending in a predetermined direction and intersecting the respective active regions. It can be considered that a portion of the word line intersecting the active region is used to constitute a gate electrode of a memory transistor.

In summary, in the trench gate field effect transistor provided in this embodiment, the first work function layer and the second work function layer with different work functions are respectively prepared, and the first work function layer with a high work function is formed at the lower portion of the gate trench, so as to ensure the turn-on performance of the transistor device; and forming a second work function layer with low work function in the overlapped area with the source drain area, thereby effectively improving the leakage current problem of the transistor device.

It should be noted that although the present invention has been described with reference to the preferred embodiments, the above embodiments are not intended to limit the present invention. To anyone skilled in the art, without departing from the scope of the present invention, the technical solution disclosed above can be used to make many possible variations and modifications to the technical solution of the present invention, or to modify equivalent embodiments with equivalent variations. Therefore, any simple modification, equivalent change and modification made to the above embodiments by the technical entity of the present invention all still belong to the protection scope of the technical solution of the present invention, where the technical entity does not depart from the content of the technical solution of the present invention.

It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated. It should also be understood that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims (7)

1. A trench-gate field effect transistor, comprising:

a gate trench formed in a substrate;

a work function adjusting layer covering an inner surface of the gate trench, the work function adjusting layer including a first work function layer and a second work function layer connected to each other, the first work function layer covering the inner surface of the gate trench lower than a first height, the second work function layer covering the inner surface of the gate trench not lower than the first height, and a work function of the second work function layer being lower than a work function of the first work function layer; and the number of the first and second groups,

and the gate electrode is formed in the gate groove and is positioned on the work function adjusting layer.

2. The trench-gate field effect transistor of claim 1, wherein a thickness of the second work function layer is greater than a thickness of the first work function layer.

3. The trench-gate field effect transistor according to claim 1, wherein the gate electrode includes a first gate electrode and a second gate electrode connected up and down, and a top surface of the first gate electrode is higher than a top surface of the first work function layer.

4. The trench-gate field effect transistor of claim 3, wherein a top surface of the second gate electrode is lower than a top surface of the second work function layer.

5. The trench-gate field effect transistor of claim 1 wherein a top surface of the gate electrode is below a top position of the gate trench and an insulating cap layer is further filled in the gate trench to cover the gate electrode.

6. The trench-gate field effect transistor of claim 1 further comprising: and the source drain region is formed on the side edge of the grid groove, and the top of the first work function layer is lower than the bottom of the source drain region.

7. The trench-gate field effect transistor of claim 1, wherein the material of the first work function layer and the second work function layer each comprises a metal nitride, and wherein the nitrogen content in the second work function layer is higher than the nitrogen content in the first work function layer.

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