CN111640745A - Memory and forming method thereof - Google Patents
Memory and forming method thereof Download PDFInfo
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- CN111640745A CN111640745A CN201910833563.1A CN201910833563A CN111640745A CN 111640745 A CN111640745 A CN 111640745A CN 201910833563 A CN201910833563 A CN 201910833563A CN 111640745 A CN111640745 A CN 111640745A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
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Abstract
The invention provides a memory and a forming method thereof. In the memory provided by the invention, the dielectric material layer formed in the word line groove has an upper layer part and a lower layer part, and the thickness of the upper layer part of the dielectric material layer is larger than that of the lower layer part in the groove isolation structure and the active region. Thus, the leakage current phenomenon between the word line and the active region can be improved, including: the leakage current between the word line and the active region in the trench isolation structure is reduced, and the gate induced leakage current (GIDL) phenomenon can be improved on the basis of maintaining the performance of the memory transistor.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a memory and a forming method thereof.
Background
As the size of semiconductor devices continues to shrink, the feature sizes of individual components in the semiconductor devices also shrink rapidly, and the spacing between adjacent individual components also gets closer and closer. Thus, the leakage current between adjacent devices is very easily caused.
Particularly for a Memory (e.g., a Dynamic Random Access Memory), with the continuous reduction of the Memory size, a leakage current phenomenon easily occurs between a word line buried in a substrate and an adjacent active region.
Disclosure of Invention
The invention aims to provide a memory to improve the leakage current phenomenon of the memory.
To solve the above technical problem, the present invention provides a memory, including:
a substrate having a plurality of active regions and trench isolation structures formed therein, the trench isolation structures separating adjacent active regions, and a word line trench also formed therein, the word line trench extending in a predetermined direction to pass through the respective active regions and trench isolation structures;
the dielectric material layer covers the inner wall of the word line groove, is provided with an upper layer part and a lower layer part which are connected up and down, and both continuously extends along the preset direction, so that the inner wall of the groove in the word line groove, which is positioned in the active area, and the inner wall of the groove in the groove isolation structure are both covered with the upper layer part and the lower layer part, and the thickness value of the upper layer part is larger than that of the lower layer part; and the number of the first and second groups,
at least one word line formed on the dielectric material layer and filling the word line trench, and extending from the lower layer portion to the upper layer portion.
Based on the transistor, the invention also provides a forming method of the memory, which comprises the following steps:
the semiconductor device comprises a substrate, a plurality of first transistors and a plurality of second transistors, wherein a trench isolation structure is formed in the substrate, and a plurality of active regions are defined by the trench isolation structure;
forming a word line trench in the substrate, the word line trench extending along a predetermined direction to pass through the respective active regions and trench isolation structures;
forming a dielectric material layer on the inner wall of the word line trench, wherein the dielectric material layer is provided with an upper layer part and a lower layer part which are connected up and down, the upper layer part and the lower layer part both extend continuously along the preset direction, so that the inner wall of the trench in the word line trench in the active area and the inner wall of the trench in the trench isolation structure are both covered with the upper layer part and the lower layer part, and the thickness value of the upper layer part is larger than that of the lower layer part; and the number of the first and second groups,
forming at least one word line in the word line trench, the word line being formed on the dielectric material layer and extending from the lower layer portion to the upper layer portion.
In the memory provided by the invention, the dielectric material layer formed in the word line trench has an upper layer part and a lower layer part which are different in thickness, and the upper layer part and the lower layer part in the dielectric material layer both extend continuously along the extending direction of the word line, so that the inner wall of the trench in the word line trench, which is positioned in the active area, and the inner wall of the trench in the trench isolation structure are both covered with the upper layer part and the lower layer part, and the thickness value of the upper layer part is greater than the thickness of the lower layer part. In this way, the thicker upper layer portion can be used to improve the leakage current between the word line and the active region, and particularly, the leakage current between the word line and the active region in the trench isolation structure can be effectively improved.
Drawings
FIG. 1 is a top view of a memory according to a first embodiment of the invention;
FIG. 2a is a schematic cross-sectional view of a memory in an aa' direction according to a first embodiment of the present invention;
FIG. 2b is a schematic cross-sectional view of a memory in a first embodiment of the invention in the bb' direction;
FIGS. 3a to 3f are schematic structural diagrams illustrating a method for forming a memory device according to a first embodiment of the invention during a manufacturing process thereof;
FIG. 4a is a schematic structural diagram of a memory in the direction aa' according to a second embodiment of the present invention;
FIG. 4b is a schematic structural diagram of a memory in the bb' direction according to the second embodiment of the present invention;
fig. 5a to 5e are schematic structural diagrams illustrating a method for forming a memory according to a second embodiment of the invention in a manufacturing process thereof.
Wherein the reference numbers are as follows:
100-a substrate;
110 a-upper trench;
200-an insulating dielectric layer;
300-a sacrificial layer;
WL-word line;
a DL/DL' -dielectric material layer;
DL1/DL 1' -first dielectric layer;
DL2/DL 2' -second dielectric layer;
AA-active region;
STI-trench isolation structure;
S/D1-first source/drain regions;
S/D2-second source/drain regions;
tr1 — first groove;
tr2 — second groove;
D1/D2-opening size;
h1 — first height position;
h2 — second elevation position;
h3 — third height position;
Detailed Description
The memory and the forming method thereof according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
Fig. 1 is a top view of a memory according to a first embodiment of the invention, fig. 2a is a schematic cross-sectional view of the memory according to the first embodiment of the invention in a direction aa ', and fig. 2b is a schematic cross-sectional view of the memory according to the first embodiment of the invention in a direction bb'. As shown in fig. 1 and 2a to 2b, the memory includes: a substrate 100 and word lines WL formed on the substrate 100.
A plurality of active areas AA and trench isolation structures STI are formed in the substrate 100, and the trench isolation structures STI separate adjacent active areas AA. The active areas AA are arranged in an array mode, and the active areas AA are mutually independent through the groove isolation structure STI, so that mutual interference among the active areas AA is avoided.
Further, a word line trench is formed in the substrate 100, and the word line trench is used for accommodating the word line WL. Specifically, the word line trench extends in a predetermined direction (X direction) to pass through the respective active area AA and the trench isolation structure STI, and a portion of the word line trench located in the active area AA constitutes a first groove Tr1 and a portion of the word line trench located in the trench isolation structure STI constitutes a second groove Tr 2.
In this embodiment, the opening size D2 of the second groove Tr2 is greater than the opening size D1 of the first groove Tr 1. Further, the bottom position of the second groove Tr2 is also lower than the bottom position of the first groove Tr 1. With particular reference to fig. 2a and 2b, the bottom position of the first groove Tr1 is located at the second height position H2, the bottom position of the second groove Tr2 is located at the first height position H1, and the first height position H1 is lower than the second height position H2.
With continued reference to fig. 1 and fig. 2a to 2b, the memory further includes a dielectric material layer DL covering the inner wall of the word line trench. The dielectric material layer DL has an upper layer and a lower layer which are connected up and down, the upper layer and the lower layer both extend continuously along the predetermined direction, so that the inner walls of the trench in the word line trench in the active area AA and the inner walls of the trench in the trench isolation structure STI are covered with the upper layer and the lower layer, and the thickness value of the upper layer is greater than that of the lower layer. That is, in the dielectric material layer DL, a portion located in the active area AA and a portion located in the trench isolation structure STI are both thick at the top and thin at the bottom.
The upper portion of the dielectric material layer DL covers, for example, the inner wall of the word line trench at a position higher than the predetermined height (i.e., the third height position H3), and the lower portion of the dielectric material layer DL covers, for example, the inner wall of the word line trench at a position lower than the predetermined height.
As described above, in the present embodiment, the bottom position of the second groove Tr2 is lower than the bottom position of the first groove Tr1, and based on this, the bottom position of the dielectric material layer DL corresponding to the trench isolation structure STI is also lower than the bottom position of the dielectric material layer DL corresponding to the active area AA.
In addition, in this embodiment, the height positions of the upper layer portion in the trench isolation structure STI and the upper layer portion in the active area AA are the same. It should be appreciated, however, that in other embodiments, the bottom of the upper layer portion in the trench isolation structure STI may also be located lower than the bottom of the upper layer portion in the active area AA, i.e., the upper layer portion in the trench isolation structure STI is made more sunken than the upper layer portion in the active area AA.
With continued reference to fig. 1 and fig. 2a to 2b, the word lines WL are formed on the dielectric material layer DL and fill the word line trenches, and the word lines WL extend from the lower layer portion to the upper layer portion. That is, the top position of the word line WL is higher than the predetermined height position (i.e., the third height position H3).
As described above, the word line trench passes through the corresponding active area AA and the trench isolation structure STI, and thus the word line WL also passes through the active area AA and the trench isolation structure STI accordingly. In this embodiment, the bottom position of the word line WL in the trench isolation structure STI is lower than the bottom position of the word line WL in the active area AA, and the top position of the word line WL is located at the same height position.
The active area AA is used to form a memory transistor, for example, and the intersecting portion of the word line WL with the active area AA can be used to form a gate conductive layer of the memory transistor.
Further, a source drain region may be further formed in the active region AA, where the source drain region includes a first source/drain region S/D1 and a second source/drain region S/D2, and the first source/drain region S/D1 and the second source/drain region S/D2 are respectively located at two sides of the word line WL to jointly form the memory transistor.
And the bottom boundary of the source drain region is lower than the top position of the word line WL and higher than the bottom boundary of the upper layer part. That is, the word line WL and the source drain region have an overlapping region opposite to each other, and in the overlapping region, the word line WL and the source drain region are spaced by an upper layer portion having a relatively thick thickness.
It should be noted that, since the word line WL extends from the lower portion to the upper portion, there are a lower portion between the bottom of the word line WL and the substrate 100 and a thicker upper portion between the top of the word line WL and the substrate 100. Particularly, an overlapping area exists between the top of the word line WL and the source drain area, so that the isolation performance between the word line WL and the source drain area can be improved, and the leakage current phenomenon between the word line WL and the source drain area is improved.
Specifically, the side edges of the source and drain regions extend to the side walls of the trench isolation structure STI, and at this time, the top of the part of the word line WL in the trench isolation structure STI corresponds to the lower layer part with thicker thickness, so that the leakage current phenomenon between the word line WL in the trench isolation structure STI and the source and drain regions can be effectively improved. In particular, in the present embodiment, the opening size of the second groove Tr2 formed in the trench isolation structure STI is relatively large, and the dimension of the space between the word line WL and the source/drain region in the trench isolation structure STI is correspondingly reduced, so that the leakage current phenomenon can be effectively alleviated by increasing the thickness of the dielectric material layer DL between the word line WL and the source/drain region.
And, in a specific memory transistor, a lower portion of the dielectric material layer DL having a relatively small thickness corresponds to a space between the gate conductive layer (i.e., the word line WL) and the substrate for forming the conductive channel, wherein the lower portion can be adjusted according to actual requirements to ensure the turn-on performance of the memory transistor and maintain the saturation current of the memory transistor. In addition, as described above, the upper layer portion of the dielectric material layer DL at least corresponds to a portion between the gate conductive layer and the source/drain region, and the thickness of the upper layer portion is relatively thick, so that gate induced leakage current (GIDL) can be effectively alleviated, a leakage current phenomenon of the memory transistor can be alleviated, and overall performance of the memory transistor can be further improved. That is, the memory transistor in this embodiment can reduce gate induced leakage current (GIDL) of the memory transistor on the basis of ensuring the on-state performance and saturation current of the memory transistor, thereby facilitating improvement of the overall performance of the memory.
It can be seen that, in the memory provided in this embodiment, the upper layer portion and the lower layer portion in the dielectric material layer DL extend continuously along the extending direction of the word line, so that the trench isolation structure STI and the active area AA both have the dielectric material layer DL with a thick top and a thin bottom, and thus, the leakage current phenomenon of the word line WL in the trench isolation structure STI and the active area AA can be improved at the same time, and the performance of the memory is greatly improved.
Further, a portion of the lower layer of the dielectric material layer DL located in the active region constitutes a first lower layer portion, a portion of the lower layer of the dielectric material layer DL located in the trench isolation structure constitutes a second lower layer portion, and a thickness dimension of the first lower layer portion is different from a thickness dimension of the second lower layer portion. Furthermore, the thickness of the first lower portion is larger than that of the second lower portion, that is, the dielectric material layer corresponding to the conductive channel region of the memory transistor is ensured to have a sufficient thickness, thereby ensuring the performance of the memory transistor.
With continuing reference to fig. 2a and 2b, the dielectric material layer DL may be a stacked structure, so as to realize the thickness adjustment of the dielectric material layer DL through each film layer in the stacked structure.
Specifically, the dielectric material layer DL comprises a first dielectric layer DL1 and a second dielectric layer DL2 which sequentially cover the inner wall of the trench. The first dielectric layer DL1 covers the inner wall of the word line trench higher than the predetermined height position (i.e., the third height position H3), the second dielectric layer DL2 covers the first dielectric layer DL1 and the inner wall of the word line trench lower than the predetermined height position, so that the lower layer part is formed by the part lower than the predetermined height position in the second dielectric layer DL2, and the upper layer part is formed by the part higher than the predetermined height position in the second dielectric layer DL2 and the first dielectric layer DL 1. That is, the upper portion in the present embodiment protrudes toward the inner wall of the trench with respect to the lower portion.
It can be understood that in this embodiment, the lower layer portion of the dielectric material layer DL is formed by using the second dielectric layer DL2, and the upper layer portion of the dielectric material layer DL is formed by overlapping the first dielectric DL1 on the basis of the second dielectric layer DL2, so as to increase the thickness of the upper layer portion. Namely, the thickness of the upper layer part comprises the sum of the thicknesses of the first dielectric layer DL1 and the second dielectric layer DL2, and the thickness of the lower layer part comprises the thickness of the second dielectric layer DL 2.
It should be appreciated that the thickness of the first dielectric layer DL1 can be adjusted according to practical requirements without affecting the thickness of the second dielectric layer DL2, for example, the thickness dimension of the first dielectric layer DL1 in the direction perpendicular to the trench sidewalls can be greater than or equal to the thickness dimension of the second dielectric layer DL2 in the direction perpendicular to the trench sidewalls. Thus, the thickness of the upper layer can be flexibly adjusted.
In addition, the first dielectric layer DL1 and the second dielectric layer DL2 may be formed by a deposition process and a thermal oxidation process, and based on this, the thickness dimension of the first dielectric layer DL1 and the second dielectric layer DL2 in the active area AA and the thickness dimension in the trench isolation structure STI may be different from each other. For example, in this embodiment, the thickness of the portion of the second dielectric layer DL2 located in the active area AA and the thickness of the portion of the second dielectric layer DL2 located in the trench isolation structure STI may be different from each other, which is equivalent to making the thickness of the first lower portion of the lower portion located in the active area AA different from the thickness of the second lower portion located in the trench isolation structure STI. And further, the thickness dimension of the second dielectric layer DL2 in the active area AA can be larger than the thickness dimension of the second dielectric layer DL2 in the trench isolation structure STI.
The first dielectric layer DL1 and the second dielectric layer DL2 may be formed of the same material, and each may include silicon oxide, for example. Of course, different materials may be used. Specifically, the material for the second dielectric layer DL2 constituting the upper and lower layer portions may include silicon oxide. And, the material for the first dielectric layer DL1 constituting the upper layer portion may also include silicon oxide. Alternatively, the first dielectric layer DL1 may be formed by using a material with better blocking performance (for example, the material of the first dielectric layer DL1 includes silicon nitride, etc.), so that the leakage current phenomenon may be further improved on the basis of increasing the thickness of the upper layer portion.
With continued reference to fig. 2a and 2b, in the present embodiment, a portion of the word line trench above the predetermined height position (i.e., the third height position H3) constitutes an upper trench, and a portion of the word line trench below the predetermined height position constitutes a lower trench. At this time, the first dielectric layer DL1 covers the trench sidewall of the upper trench, and the second dielectric layer DL2 covers the outer sidewall of the first dielectric layer DL1 and the trench inner wall of the lower trench.
Further, in the word line trench, the opening size of the upper trench is larger than that of the lower trench, and the inner walls of the interconnected trenches in the upper trench and the lower trench form a step-like structure. It can be understood that, in this embodiment, the sidewall of the upper trench is recessed toward the sidewall direction relative to the sidewall of the lower trench, so that the upper trench and the lower trench form a step-like structure at the junction.
Wherein the first dielectric layer DL1 is formed on the step of the step-like structure. Further, the outer side wall of the first dielectric layer DL1 is smoothly connected with the trench side wall of the lower trench, and the second dielectric layer DL2 conforms to the outer side wall of the first dielectric layer DL1 and the trench inner wall of the lower trench, and conformally covers the first dielectric layer DL1 and the inner wall of the lower trench. And the side wall boundary of the word line WL filled in the word line groove correspondingly conforms to the outer side wall of the second dielectric layer DL2 and presents a smooth side wall.
With continued reference to fig. 2a and 2b, the top position of the word line WL is lower than the top position of the word line trench, and the space of the word line trench higher than the word line WL is further filled with an insulating medium layer 200 to cover the word line WL.
Based on the memory described above, a method of forming the memory in the present embodiment will be described in detail below. Specifically, in the method for forming the memory in this embodiment, the word line trench is formed in the process of preparing the dielectric material layer. Fig. 3a to fig. 3f are schematic structural diagrams of a method for forming a memory according to a first embodiment of the invention during a manufacturing process thereof.
Referring first to fig. 3a, a substrate 100 is provided, the substrate 100 is formed with a trench isolation structure STI, and a plurality of active regions AA are defined by the trench isolation structure SIT.
Next, referring to fig. 3b, an upper trench 110a is formed in the substrate 100, and a bottom position of the upper trench 110a is located at a predetermined height position (i.e., a third height position H3).
Wherein the upper trenches 110a further form word line trenches in a subsequent step, so that the upper trenches 110a respectively extend along a predetermined direction and pass through the respective active areas AA and the trench isolation structures STI. Further, the opening dimension D1 of the upper trench 110a in the active area AA is smaller than the opening dimension D2 of the upper trench 110a in the trench isolation structure STI.
Referring next to fig. 3c, a first dielectric layer DL1 is formed on the sidewalls of the upper trench 110 a. At this time, the first medium layer DL1 is correspondingly higher than the predetermined height. The first dielectric Layer DL1 may be formed by a Deposition process, specifically by an Atomic Layer Deposition (ALD) process.
Referring to fig. 3d, the bottom of the upper trench 110a is etched by using the first dielectric layer DL1 as a mask to form a lower trench, and the lower trench is in upper and lower communication with the upper trench 110 a. That is, the lower trench extends further downward from the predetermined height position (third height position H3), and the trench sidewall of the lower trench and the outer sidewall of the first dielectric layer DL1 are smoothly connected, thereby causing the lower trench and the upper trench 110a to assume a step-like structure at the connection, and causing the opening size of the lower trench to be smaller than the opening size of the upper trench 110 a.
Further, the bottom of the lower trench in the trench isolation structure STI extends downward to the first height position H1, the bottom of the lower trench in the active area AA extends downward to the second height position H2, and the first height position H1 is lower than the second height position H2.
In this embodiment, the word line trench is formed by the lower trench and the upper trench 110a, and a portion of the word line trench located in the active region AA forms a first groove Tr1, a portion of the word line trench located in the trench isolation structure STI forms a second groove Tr2, and a bottom position of the second groove Tr2 is lower than a bottom position of the first groove Tr 1.
It should be noted that although the mask layer on the top surface of the substrate is not shown in the drawings of the present embodiment, it should be appreciated that during the etching of the substrate 100 to form the upper trench and the lower trench, the mask layer is usually formed on the top surface of the substrate 100 to avoid etching the regions of the substrate that are not corresponding to the trenches.
Next, referring to fig. 3e, a second dielectric layer DL2 is formed in the word line trench, the second dielectric layer DL2 covers the inner wall of the lower trench and the outer sidewall of the first dielectric layer DL 1. The dielectric material layer DL can be formed by the second dielectric layer DL2 and the first dielectric layer DL 1.
The part of the second dielectric layer DL2 covering the first dielectric layer DL1 and the first dielectric layer DL1 form the upper layer part, and the part of the second dielectric layer DL2 covering the inner wall of the lower groove forms the lower layer part.
In this embodiment, the forming method of the second dielectric layer DL2 includes a deposition process and a thermal oxidation process. Specifically, the forming method of the second dielectric layer DL2 may include: first, a deposition process (e.g., an atomic layer deposition process, etc.) is performed to deposit a dielectric material in the first and second grooves Tr1 and Tr 2; next, a thermal oxidation process (e.g., an in-situ steam oxidation method ISSG, etc.) is performed, thus improving the densification of the dielectric material.
It should be noted that, by performing a thermal oxidation process (for example, ISSG), in the trench isolation structure STI, not only the compactness of the deposited dielectric material can be improved, but also the compactness of the insulating material of the trench isolation structure STI itself can be further improved, and the internal stress of the trench isolation structure STI can be relieved, so that the isolation performance of the trench isolation structure STI can be improved, and the leakage current phenomenon can be further improved. In the active area AA, through the thermal oxidation process, on one hand, the compactness of the dielectric material in the active area AA can be improved, and the dielectric constant of the dielectric material is improved; on the other hand, in the thermal oxidation process, the oxygen radicals further oxidize the substrate on the inner wall of the word line trench, so that the thickness dimension of the second dielectric layer DL2 in the active region AA is increased, and the device performance of the formed memory transistor is favorably guaranteed.
Referring next to fig. 3f, a word line WL is formed in the word line trench. Specifically, the top position of the word line WL is higher than the predetermined height position (third height position H3), so that the sidewall boundary of the word line WL conforms to the sidewall of the second dielectric layer DL2 and extends from the lower layer portion to the upper layer portion. The material of the word line WL includes, for example, polysilicon or tungsten.
In this embodiment, the top position of the word line WL is also lower than the top surface of the substrate 100, i.e., the word line WL does not fill the word line trench. Specifically, the height of the word line WL in the word line trench may be reduced, for example, by an etch-back process, so that the top surface of the word line WL is lower than the top surface of the substrate 100.
In a further aspect, with continued reference to fig. 3f, the method of forming a memory further includes: and filling an insulating medium layer 200 in the space of the word line groove higher than the word line WL to cover the word line WL. The material of the insulating dielectric layer 200 includes, for example, silicon nitride.
With continued reference to fig. 3f, the method of forming the memory further comprises: forming a source drain region in the substrate 100, wherein a side edge boundary of the source drain region extends to a side wall of the word line trench close to the top opening, and a bottom boundary of the source drain region is lower than a top position of the word line WL and higher than the predetermined height position (a third height position H3), so that the source drain region and the word line WL have mutually opposite overlapping regions, and in the overlapping regions, the word line WL and the source drain region are separated from each other by an upper layer part in the dielectric material layer DL.
Specifically, the source and drain regions include a first source/drain region S/D1 and a second source/drain region S/D2, and the first source/drain region S/D1 and the second source/drain region S/D2 are respectively located at two sides of the word line WL. In this embodiment, the side edge boundary of the first source/drain region S/D1 also extends to the sidewall of the trench isolation structure STI.
It should be noted that, in this embodiment, after the word line trench is formed and the word line WL is formed, the source and drain regions are prepared. However, in other embodiments, the source and drain regions may be formed first, and then the word line trench and the word line WL are sequentially formed, which is not limited herein.
Example two
The difference from the first embodiment is that the dielectric material layer in the present embodiment has an upper portion protruding in a direction away from the inner wall of the trench relative to a lower portion. The memory in this embodiment is described in detail below with reference to fig. 4a and 4 b. Fig. 4a is a schematic structural diagram of a memory in a second embodiment of the present invention in an aa 'direction, and fig. 4b is a schematic structural diagram of a memory in a second embodiment of the present invention in a bb' direction.
In the embodiment, as shown in fig. 4a and 4b, the dielectric material layer DL ' includes a first dielectric layer DL1 ' and a second dielectric layer DL2 '. The first dielectric layer DL1 ' covers the inner wall of the word line trench, and the part of the first dielectric layer DL1 ' lower than the predetermined height position (i.e., the third height position H3) constitutes the lower part of the dielectric material layer DL '; and the second dielectric layer DL2 ' covers the part of the first dielectric layer DL1 ' higher than the predetermined height position, and the part of the first dielectric layer DL1 ' higher than the predetermined height position and the second dielectric layer DL2 ' form the upper layer part of the dielectric material layer DL '.
It can be understood that, in the present embodiment, the lower layer portion of the dielectric material layer DL ' is formed by using the first dielectric layer DL1 ', and the upper layer portion of the dielectric material layer DL ' is formed by overlapping the second dielectric layer DL2 ' on the basis of the first dielectric layer DL1 ', so as to increase the thickness of the upper layer portion. It should be appreciated that the thickness of the second dielectric layer DL2 'can be adjusted according to practical requirements without affecting the thickness of the first dielectric layer DL 1', for example, the thickness dimension of the second dielectric layer DL2 'in the direction perpendicular to the trench sidewalls can be greater than or equal to the thickness dimension of the first dielectric layer DL 1' in the direction perpendicular to the trench sidewalls.
As described above, the materials of the first dielectric layer DL1 'and the second dielectric layer DL 2' may be the same or different. In this embodiment, the material of the first dielectric layer DL 1' constituting the upper and lower portions includes, for example, silicon oxide (SiO). And the material for forming the second dielectric layer DL 2' of the upper layer portion can be adjusted according to actual requirements. Specifically, the second dielectric layer DL2 'may be made of the same material as the first dielectric layer DL 1', which is equivalent to increasing the thickness of the upper layer; alternatively, the second dielectric layer DL2 '(e.g., the second dielectric layer DL 2' is made of silicon nitride) may be made of a material having a better blocking property, so that the leakage current phenomenon may be further improved on the basis of increasing the thickness of the upper portion 200 b.
In addition, in this embodiment, the first dielectric layer DL1 ' and the second dielectric layer DL2 ' may be formed by a deposition process and a thermal oxidation process, and based on this, the thickness of the first dielectric layer DL ' and the second dielectric layer DL2 ' in the active area AA may be different from the thickness of the second dielectric layer DL2 ' in the trench isolation structure STI. Specifically, in this embodiment, the thickness of the portion of the first dielectric layer DL1 'located in the active area AA and the thickness of the portion of the first dielectric layer DL 1' located in the trench isolation structure STI may be different from each other, which is equivalent to making the thickness of the first lower portion of the lower portion located in the active area AA different from the thickness of the second lower portion located in the trench isolation structure STI. And further, the thickness dimension of the first dielectric layer DL1 'in the active area AA can be larger than the thickness dimension of the first dielectric layer DL 1' in the trench isolation structure STI.
As can be seen from the first and second embodiments, when selecting the materials of the first dielectric layer and the second dielectric layer, for the dielectric layer simultaneously used for forming the upper layer portion and the lower layer portion, for example, silicon oxide may be used for forming the dielectric layer, and for the dielectric layer simultaneously used for forming the upper layer portion and the lower layer portion, the dielectric layer may have different thicknesses in the active region and the trench isolation structure (for example, the thickness dimension of the dielectric layer in the active region is larger than that in the trench isolation structure). And, the dielectric layer for constituting only the upper layer portion may be adjusted according to actual requirements (for example, including silicon nitride and/or silicon oxide, etc.), and of course, the dielectric layer for constituting only the upper layer portion may also have different thickness dimensions in the active region and the trench isolation structure.
Furthermore, the side wall of the word line trench is a smooth side wall, the first dielectric layer DL1 ' conforms to the inner wall of the word line trench and conformally covers the inner wall of the word line trench, and the second dielectric layer DL2 ' covers the outer side wall of the first dielectric layer DL1 ', so that the formed upper layer part protrudes relative to the lower layer part in a direction away from the inner wall of the trench.
Based on this, the top dimension of the word line WL filled in the word line trench can be reduced. Specifically, the word line WL has a first sidewall attached to the first dielectric layer DL1 'and a second sidewall attached to the second dielectric layer DL 2', and the first sidewall and the second sidewall form a step-like structure at the junction.
With continuing reference to fig. 4a and 4b, similar to the embodiment, the top position of the word line WL is lower than the top position of the word line trench, and the space of the word line trench above the gate conductive layer 100 is further filled with an insulating dielectric layer 200 to cover the word line WL.
The method of forming the memory in this embodiment will be described in detail below. Specifically, in the method for forming the memory in this embodiment, the dielectric material layer is prepared after the gate trench is formed. Fig. 5a to 5e are combined to describe in detail, wherein fig. 5a to 5e are schematic structural diagrams of a memory forming method in a second embodiment of the invention in a manufacturing process thereof.
Referring first to fig. 5a, a substrate 100 is provided, the substrate 100 having a word line trench formed therein. The word line trenches extend along a predetermined direction (i.e., an extending direction of the word line) to pass through the respective active areas AA and the trench isolation structures STI.
As described above, the bottom position of the second groove Tr1 in the word line trench is more depressed with respect to the bottom position of the first groove Tr1 in the word line trench.
Referring next to fig. 5b, a first dielectric layer DL 1' is formed on the inner wall of the word line trench. The material of the first dielectric layer DL 1' includes, for example, silicon oxide.
Further, the first dielectric layer DL1 'may be formed by, for example, a deposition process and a thermal oxidation process, and further, the thermal oxidation process may include, for example, an in-situ steam oxidation (ISSG) process, so as to increase the dielectric constant of the first dielectric layer DL 1'.
In this embodiment, when the first dielectric layer DL1 ' is formed by a deposition process and a thermal oxidation process, the thickness of the portion of the formed first dielectric layer DL1 ' located in the active area AA and the thickness of the portion of the formed first dielectric layer DL1 ' located in the trench isolation structure STI may be different from each other. Specifically, when the thermal oxidation process is performed, the compactness of the formed first dielectric layer DL1 ' may be improved, the compactness of the insulating material in the trench isolation structure STI may also be improved, and the substrate on the inner wall of the word line trench in the active area AA may also be oxidized, so that the thickness dimension of the first dielectric layer DL1 ' in the active area AA may be greater than the thickness dimension of the first dielectric layer DL1 ' in the trench isolation structure.
In this embodiment, the first dielectric layer DL 1' may be formed on the top surface of the substrate 10 at the same time as the inner wall of the word line trench.
Note that, a portion of the first dielectric layer DL1 'lower than the predetermined height position is used to form a lower portion of the dielectric material layer DL'. In the active region AA, the lower portion constitutes a gate dielectric layer between the gate conductive layer and the conductive channel of the memory transistor, and therefore, the thickness of the first dielectric layer DL 1' can be adjusted according to the specific memory transistor to meet the device performance of the memory transistor.
Referring next to fig. 5c, a sacrificial layer 300 is filled in the word line trench, the sacrificial layer 300 being filled up to a predetermined height position (third height position H3) from the bottom of the word line trench. That is, the sacrificial layer 300 covers a portion of the first dielectric layer DL1 'lower than the predetermined height position and exposes the outer sidewall of the first dielectric layer DL 1' higher than the sacrificial layer.
The material of the sacrificial layer 300 includes, for example, an organic material. And, the specific forming method of the sacrificial layer 300 includes, for example: firstly, filling organic materials into the word line groove by adopting a spin coating process; next, an etch-back process is performed to reduce the height of the organic material in the word line trench to a predetermined height position, so as to form the sacrificial layer 300.
With continued reference to fig. 5c, a second dielectric layer DL2 'is formed on the exposed outer sidewall of the first dielectric layer DL 1', i.e., the second dielectric layer DL2 'is correspondingly formed on the outer sidewall of the first dielectric layer DL 1' at a position higher than the predetermined height.
The first dielectric layer DL1 'and the second dielectric layer DL 2' constitute a dielectric material layer DL ', a portion of the first dielectric layer DL 1' lower than a predetermined height position constitutes the lower layer portion, and a portion of the first dielectric layer DL1 'higher than the predetermined height position and the second dielectric layer DL 2' constitute the upper layer portion.
Further, the material of the second dielectric layer DL2 'may be the same as that of the first dielectric layer DL 1', for example, both include silicon oxide. And the second dielectric layer DL 2' can be formed by a chemical vapor deposition process or an atomic layer deposition process.
Referring next to fig. 5d, the sacrificial layer 300 is removed, so that a portion of the first dielectric layer DL 1' below a predetermined height position may be exposed.
That is, in the dielectric material layer DL 'of the present embodiment, the lower layer portion is formed by the first dielectric layer DL 1', and the upper layer portion is formed by the first dielectric layer DL1 'and the second dielectric layer DL 2', so that the upper layer portion protrudes away from the inner wall of the trench relative to the lower layer portion.
Referring next to fig. 5e, a word line WL is formed in the word line trench. Similar to the embodiment, the top position of the word line WL is lower than the top position of the word line trench, and based on this, after the word line WL is formed, the method further includes filling an insulating dielectric layer 200 in the space above the word line in the word line trench.
In summary, in the memory described in the above embodiment, the dielectric material layer has a thicker upper layer portion and a thinner lower layer portion, so that the word line and the source drain region are separated from each other by the thicker upper layer portion in the overlapped region where the word line and the source drain region overlap each other, thereby facilitating to improve the leakage current phenomenon of the memory.
Specifically, for the isolation region (corresponding to the region of the trench isolation structure), the edge boundary of the source/drain region in the active region extends to the trench isolation structure, and the word line and the source/drain region in the trench isolation structure have a thicker upper layer portion in the overlapping region of the front surfaces of each other, so that the leakage current phenomenon between the word line and the source/drain region in the isolation region can be effectively improved.
And, for the active region as well, it is possible to make the word line and the source-drain region have a thicker upper layer portion in an overlapping region of the front surfaces of each other, and a thinner lower layer portion between the word line and the substrate for constituting the conductive channel. Therefore, on one hand, because a medium material layer with a relatively thin thickness is still adopted between the word line and the substrate for forming the conductive channel, the performance of the storage transistor is ensured; on the other hand, thicker dielectric material layers are adopted between the word line and the source drain region to be mutually spaced, so that the phenomenon of gate induced leakage current (GIDL) can be effectively improved.
In addition, in the memory as described above, the dielectric material layers are stacked, so that the thickness of the upper layer portion can be increased without changing the thickness of the lower layer portion, which not only can improve the gate induced leakage current (GIDL) phenomenon while maintaining the performance of the memory transistor, but also is beneficial to flexibly adjusting the parameters of the upper layer portion, for example, the thickness, material, and the like of the upper layer portion.
It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.
It should be noted that, although the present invention has been described with reference to the preferred embodiments, the above embodiments are not intended to limit the present invention. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.
Claims (19)
1. A memory, comprising:
a substrate having a plurality of active regions and trench isolation structures formed therein, the trench isolation structures separating adjacent active regions, and a word line trench also formed therein, the word line trench extending in a predetermined direction to pass through the respective active regions and trench isolation structures;
the dielectric material layer covers the inner wall of the word line groove, is provided with an upper layer part and a lower layer part which are connected up and down, and both continuously extends along the preset direction, so that the inner wall of the groove in the word line groove, which is positioned in the active area, and the inner wall of the groove in the groove isolation structure are both covered with the upper layer part and the lower layer part, and the thickness value of the upper layer part is larger than that of the lower layer part; and the number of the first and second groups,
at least one word line formed on the dielectric material layer and filling the word line trench, and extending from the lower layer portion to the upper layer portion.
2. The memory of claim 1, wherein a portion of the word line trench located in the active region constitutes a first recess, and a portion of the word line trench located in the trench isolation structure constitutes a second recess, an opening size of the second recess being larger than an opening size of the first recess.
3. The memory according to claim 1, wherein a portion of the word line trench located in the active region constitutes a first recess, and a portion of the word line trench located in the trench isolation structure constitutes a second recess, and a bottom position of the second recess is lower than a bottom position of the first recess.
4. The memory of claim 1, wherein a portion of the lower layer of the dielectric material layer that is located in the active region constitutes a first lower layer portion, a portion of the lower layer of the dielectric material layer that is located in the trench isolation structure constitutes a second lower layer portion, and a thickness dimension of the first lower layer portion and a thickness dimension of the second lower layer portion are different from each other.
5. The memory of claim 4, wherein a thickness dimension of the first lower portion is greater than a thickness dimension of the second lower portion.
6. The memory of claim 1, wherein the layer of dielectric material comprises a first dielectric layer and a second dielectric layer;
the first dielectric layer covers the inner wall of the word line groove higher than the preset height position, the second dielectric layer covers the first dielectric layer and the inner wall of the word line groove lower than the preset height position, so that the part of the second dielectric layer lower than the preset height position forms the lower layer part, and the part of the second dielectric layer higher than the preset height position and the first dielectric layer form the upper layer part.
7. The memory of claim 6, wherein a thickness dimension of the first dielectric layer in a direction perpendicular to a trench sidewall is greater than a thickness dimension of the second dielectric layer in a direction perpendicular to a trench sidewall.
8. The memory of claim 6, wherein a thickness dimension of a portion of the second dielectric layer located in the active region and a thickness dimension of a portion of the second dielectric layer located in the trench isolation structure are different from each other.
9. The memory of claim 6, wherein a portion of the word line trench above a predetermined height position constitutes an upper trench, a portion of the word line trench below the predetermined height position constitutes a lower trench, an opening size of the upper trench is larger than an opening size of the lower trench, and the upper trench and the lower trench form a step-like structure at a junction.
10. The memory of claim 1, wherein the layer of dielectric material comprises a first dielectric layer and a second dielectric layer;
the first dielectric layer covers the inner wall of the word line groove, the part of the first dielectric layer, which is lower than the preset height position, forms the lower layer part, the second dielectric layer covers the part of the first dielectric layer, which is higher than the preset height position, and the second dielectric layer and the part of the first dielectric layer, which is higher than the preset height position, form the upper layer part.
11. The memory of claim 10, wherein a thickness dimension of the second dielectric layer in a direction perpendicular to a trench sidewall is greater than a thickness dimension of the first dielectric layer in a direction perpendicular to a trench sidewall.
12. The memory of claim 10, wherein a thickness dimension of a portion of the first dielectric layer located in the active region and a portion of the first dielectric layer located in the trench isolation structure are different from each other.
13. The memory of claim 10, wherein the word line has a first sidewall conforming to the first dielectric layer and a second sidewall conforming to the second dielectric layer, the first sidewall and the second sidewall forming a step-like structure at a junction.
14. The memory of claim 1, wherein the memory further comprises:
and the source and drain regions are formed in the active region, and the bottom boundaries of the source and drain regions are lower than the top position of the word line and higher than the bottom boundary of the upper layer part.
15. A method for forming a memory, comprising:
the semiconductor device comprises a substrate, a plurality of first transistors and a plurality of second transistors, wherein a trench isolation structure is formed in the substrate, and a plurality of active regions are defined by the trench isolation structure;
forming a word line trench in the substrate, the word line trench extending along a predetermined direction to pass through the respective active regions and trench isolation structures;
forming a dielectric material layer on the inner wall of the word line trench, wherein the dielectric material layer is provided with an upper layer part and a lower layer part which are connected up and down, the upper layer part and the lower layer part both extend continuously along the preset direction, so that the inner wall of the trench in the word line trench in the active area and the inner wall of the trench in the trench isolation structure are both covered with the upper layer part and the lower layer part, and the thickness value of the upper layer part is larger than that of the lower layer part; and the number of the first and second groups,
forming a word line in the word line trench, the word line being formed on the dielectric material layer and extending from the lower layer portion to the upper layer portion.
16. The method of claim 15, wherein the dielectric material layer is formed by a deposition process and a thermal oxidation process, and a thickness of a first lower portion of the lower layer in the active region is different from a thickness of a second lower portion of the lower layer in the trench isolation structure.
17. The method of forming a memory of claim 15, wherein the dielectric material layer is formed after forming the word line trench, wherein the method of forming the dielectric material layer comprises:
forming a first dielectric layer on the inner wall of the word line groove;
filling a sacrificial layer in the word line groove, wherein the sacrificial layer is filled from the bottom of the word line groove to a preset height position upwards, and the outer side wall, higher than the sacrificial layer, of the first dielectric layer is exposed;
forming a second dielectric layer on the exposed outer side wall of the first dielectric layer, wherein the first dielectric layer and the second dielectric layer form the dielectric material layer; and the number of the first and second groups,
and removing the sacrificial layer.
18. The method of forming a memory of claim 15, wherein the word line trench is formed while the dielectric material layer is being prepared, wherein the method of forming the word line trench and the dielectric material layer comprises:
forming an upper groove in the substrate, wherein the bottom position of the upper groove is located at a preset height position;
forming a first dielectric layer on the side wall of the upper groove;
etching the bottom of the upper groove by taking the first dielectric layer as a mask to form a lower groove, wherein the lower groove is communicated with the upper groove up and down to form the word line groove;
and forming a second dielectric layer in the word line groove, wherein the second dielectric layer covers the inner wall of the lower groove and the outer side wall of the first dielectric layer, and the second dielectric layer and the first dielectric layer form the dielectric material layer.
19. The method of forming a memory of claim 15, further comprising, after forming the layer of dielectric material:
and forming a source drain region in the active region, wherein the bottom boundary of the source drain region is lower than the top position of the word line and higher than the bottom boundary of the upper layer part.
Priority Applications (3)
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| CN201910833563.1A CN111640745A (en) | 2019-09-04 | 2019-09-04 | Memory and forming method thereof |
| PCT/CN2020/079583 WO2021022812A1 (en) | 2019-08-16 | 2020-03-17 | Transistor, memory and method of forming same |
| US17/298,315 US20220028867A1 (en) | 2019-08-16 | 2020-03-17 | Transistor, memory and method of forming same |
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| CN201910833563.1A CN111640745A (en) | 2019-09-04 | 2019-09-04 | Memory and forming method thereof |
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| CN113471200A (en) * | 2020-03-31 | 2021-10-01 | 长鑫存储技术有限公司 | Memory and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113471200A (en) * | 2020-03-31 | 2021-10-01 | 长鑫存储技术有限公司 | Memory and forming method thereof |
| WO2021197039A1 (en) * | 2020-03-31 | 2021-10-07 | 长鑫存储技术有限公司 | Memory and forming method therefor |
| CN113471200B (en) * | 2020-03-31 | 2023-12-12 | 长鑫存储技术有限公司 | Memory and forming method thereof |
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