CN111640746A - Semiconductor device, forming method thereof and memory - Google Patents

Semiconductor device, forming method thereof and memory Download PDF

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Publication number
CN111640746A
CN111640746A CN201910877052.XA CN201910877052A CN111640746A CN 111640746 A CN111640746 A CN 111640746A CN 201910877052 A CN201910877052 A CN 201910877052A CN 111640746 A CN111640746 A CN 111640746A
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China
Prior art keywords
bit line
contact plug
line contact
conductive layer
layer
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Pending
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CN201910877052.XA
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Chinese (zh)
Inventor
何世伟
黄德浩
朱贤士
周运帆
黄丰铭
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Fujian Jinhua Integrated Circuit Co Ltd
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Fujian Jinhua Integrated Circuit Co Ltd
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Application filed by Fujian Jinhua Integrated Circuit Co Ltd filed Critical Fujian Jinhua Integrated Circuit Co Ltd
Priority to CN201910877052.XA priority Critical patent/CN111640746A/en
Priority to PCT/CN2019/124589 priority patent/WO2020211406A1/en
Priority to US16/635,465 priority patent/US11164877B2/en
Publication of CN111640746A publication Critical patent/CN111640746A/en
Priority to US17/482,456 priority patent/US11678479B2/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/312—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with a bit line higher than the capacitor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a semiconductor device, a forming method thereof and a memory. In the semiconductor device provided by the invention, the bit line contact plug is formed on the active region and is also partially formed on the insulating material layer in the gate trench, so that the bit line contact plug can be fully contacted with the active region, and even if a gap is formed in the bit line contact plug, the electrical transmission performance between the bit line contact plug and the active region can be still ensured. At this time, for the bit line contact plug allowing the void, the manufacturing difficulty is lower, the manufacturing process is faster, and accordingly, the productivity of the memory can be effectively improved.

Description

Semiconductor device, forming method thereof and memory
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device, a method of forming the same, and a memory.
Background
With the continuous development of semiconductor technology, the size of semiconductor devices is continuously reduced, so that the preparation difficulty of the semiconductor devices is higher, the production efficiency is low, and the utilization rate of semiconductor processing equipment is lower.
Taking a Memory as an example, further example is a Dynamic Random Access Memory (DRAM), which generally includes Memory transistors and bit lines and word lines, so as to select corresponding Memory transistors by using the word lines and the bit lines and control the conduction of the selected Memory transistors.
In the conventional memory, in order to ensure a good electrical connection between the bit line and the memory transistor when the bit line is fabricated, the requirements for the fabrication process of the bit line (especially the bit line contact plug) are high, for example, the requirements for the deposition process are also strict. In this case, the manufacturing requirement of the bit line is strict, the manufacturing process is slow, the production efficiency of the memory is affected, and the utilization rate of the semiconductor processing equipment is low.
Disclosure of Invention
The invention aims to provide a semiconductor device, which is used for reducing the manufacturing difficulty of the semiconductor device and accelerating the preparation process of the semiconductor device so as to be beneficial to improving the productivity.
To solve the above technical problem, the present invention provides a semiconductor device, comprising:
the semiconductor device comprises a substrate, a plurality of active regions and at least one grid groove, wherein the grid groove is at least partially positioned in the active regions;
the buried gate electrode and the insulating material layer are sequentially filled in the gate trench; and the number of the first and second groups,
a bit line contact plug formed locally on the insulating material layer and coupled to the active region, and a void provided in the bit line contact plug.
In addition, the present invention also provides a memory comprising:
a substrate having a plurality of active regions formed therein;
the bit line comprises a first conductive layer and a second conductive layer which are stacked from bottom to top, the first conductive layer is coupled to the active region and used for forming a bit line contact plug, the maximum width dimension of the bit line contact plug is larger than that of the second conductive layer, and at least one gap is formed in the bit line contact plug.
And, based on the semiconductor device as described above, the present invention also provides a method of forming a semiconductor device, comprising:
providing a substrate, wherein a plurality of active regions are defined in the substrate;
forming at least one gate trench in the substrate, the gate trench being at least partially located in the active region;
sequentially filling a buried gate electrode and an insulating material layer in the gate trench; and the number of the first and second groups,
forming a bit line contact plug on the substrate, the bit line contact plug also being formed partially on the insulating material layer and coupled to the active region, and a void being formed in the bit line contact plug.
The present invention provides a semiconductor device wherein a bit line contact plug is formed locally on the layer of insulating material and coupled to said active region, i.e. equivalently, said bit line contact plug is formed on the active region and further extends laterally to above the buried gate electrode. Therefore, the bit line contact plug can have a larger width dimension, so that the contact area between the bit line contact plug and the active region is as large as possible, thereby being beneficial to reducing the contact resistance between the bit line contact plug and the active region. It can be seen that even though the void is formed in the bit line contact plug, since the bit line contact plug formed with the void can be sufficiently contacted with the active region, signal transmission performance between the bit line contact plug and the active region can be still secured. In addition, for the bit line contact plug with the allowed gap, in the preparation process of the bit line contact plug, the bit line contact plug can be prepared faster by adopting a rapid deposition mode, so that the preparation process of the bit line contact plug can be accelerated, the preparation efficiency of a semiconductor device is correspondingly improved, the productivity is effectively improved, and the utilization rate of semiconductor processing equipment is improved.
Drawings
Fig. 1 is a top view of a semiconductor device in accordance with a first embodiment of the present invention;
fig. 2a is a schematic cross-sectional view along aa' direction of a semiconductor device according to a first embodiment of the present invention;
fig. 2b is a schematic cross-sectional view of a semiconductor device along the bb' direction in the first embodiment of the invention;
fig. 3 is a schematic flow chart illustrating a method for forming a semiconductor device according to a first embodiment of the present invention;
fig. 4a to fig. 4e are schematic structural diagrams of a method for forming a semiconductor device in a first embodiment of the invention during a manufacturing process thereof;
fig. 5 is a schematic structural diagram of a semiconductor device according to a second embodiment of the present invention.
Wherein the reference numbers are as follows:
100-a substrate;
101-a trench isolation structure;
110 — a first source/drain region;
120-a second source/drain region;
200-word line;
200 a-word line trench;
210-a layer of insulating material;
300-bit line;
310/310' -bit line contact plugs;
310a/310 a' -voids;
310 b-curved sidewalls;
320-a second conductive layer;
330-a third conductive layer;
340-a capping layer;
400-an isolation layer;
510-a first layer of sacrificial material;
520-a second layer of sacrificial material;
600-bit line trenches;
610-a first groove;
620-a second recess;
630-a third groove;
AA-active region.
Detailed Description
The semiconductor device, the forming method thereof and the memory according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
Fig. 1 is a top view of a semiconductor device according to a first embodiment of the present invention, fig. 2a is a schematic cross-sectional view of the semiconductor device along a direction aa ', and fig. 2b is a schematic cross-sectional view of the semiconductor device along a direction bb'.
As shown in fig. 1 and 2a to 2b, the semiconductor device includes a substrate 100, and a buried gate electrode 200 and a bit line 300 formed on the substrate 100.
Further, a plurality of active regions AA are formed in the substrate 100. The semiconductor device is, for example, a memory. In this embodiment, the semiconductor device is taken as an example of a memory, and based on this, a first source/drain region 110 and a second source/drain region 120 may also be formed in the active region AA to form a memory transistor. Adjacent active areas AA may be separated from each other by a trench isolation structure 101, for example.
With continued reference to fig. 1 and fig. 2a to 2b, a gate trench 200a is further formed in the substrate 100, and the gate trench 200a is at least partially located in the active area AA. And a buried gate electrode 200 and an insulating material layer 210 are also filled in the gate trench 200a in this order.
In an embodiment taking the memory as an example, the buried gate electrode 200 is used to form a word line, for example, based on which the buried gate electrode 200 extends along the second direction (X direction) and intersects with the corresponding active area AA, and a portion of the word line intersecting with the active area AA is located between the first source/drain region 110 and the second source/drain region 120 (i.e., the first source/drain region 110 and the second source/drain region 120 are located at both sides of the word line, respectively) to form a gate structure of the memory transistor.
In this embodiment, the top position of the buried gate electrode 200 is lower than the top position of the gate trench 200a, and the insulating material layer 210 is filled in the space where the gate trench 200a is higher than the buried gate electrode 200, so as to cover the buried gate electrode 200 with the insulating material layer 210, thereby preventing the buried gate electrode 200 from being exposed.
Referring to fig. 1 and 2 a-2 b with emphasis, the bit lines 300 are formed on the substrate 100 and extend along a first direction (i.e., Y direction) and spatially intersect the corresponding active areas AA, such that the corresponding active areas AA are electrically connected to the bit lines 300. In this embodiment, the first source/drain region 110 in the active area AA is electrically connected to the bit line 300.
Further, the bit line 300 includes: a bit line contact plug 310 partially formed on the insulating material layer 210 and coupled to the active region AA, and a void 310a is disposed in the bit line contact plug 310. Specifically, the bit line contact plug 310 may be formed using, for example, a first conductive layer, and the material of the first conductive layer includes, for example, polysilicon.
In this embodiment, the bit line contact plug 310 extends from the first source/drain region 110 to the insulating material layer 210, and at this time, the length dimension of the bottom surface of the bit line contact plug 310 in the first direction is greater than or equal to the length dimension of the first source/drain region 110 in the first direction, so that the contact surface of the first source/drain region 110 can be fully utilized to achieve sufficient contact between the bit line contact plug 310 and the first source/drain region 110, and reduce the contact resistance between the bit line contact plug 310 and the first source/drain region 110. Therefore, even if the void 310a is formed in the bit line contact plug 310, the electrical transmission performance of the bit line contact plug 310 can be ensured.
It should be noted that, since the bit line contact plug 310 may allow the void 310a to be formed therein, when the bit line contact plug 310 is prepared, the bit line contact plug 310 may be prepared faster by using a fast deposition method, so as to speed up the preparation process of the semiconductor device, effectively improve the productivity, and improve the utilization rate of the semiconductor processing equipment.
As shown in fig. 2a and 2b, the bit line contact plug 310 may be further embedded in the substrate 100, so as to further increase the contact area between the bit line contact plug 310 and the active area AA. Moreover, the ion concentration of the ion implanted active area AA corresponding to the inside of the substrate is generally higher than the ion concentration corresponding to the surface of the substrate, so that the bit line contact plug 310 is embedded into the substrate 100, which is beneficial to further reducing the contact resistance between the bit line contact plug 310 and the active area AA and improving the connection performance between the bit line contact plug 310 and the high ion concentration area.
As described above, the bit line contact plug 310 is partially formed on the insulating material layer 210 and coupled to the active region AA. Based on this, the bit line contact plug 310 having a portion embedded in the substrate 100 in the present embodiment, that is, it can be considered that the bit line contact plug 310 extends from above the top surface of the insulating material layer 210 to a predetermined depth position of the insulating material layer 210, which is above the top surface of the buried gate electrode 200.
As shown with continued reference to fig. 2a and 2b, the bit line contact plug 310 has two convex sidewalls facing each other. And, the space 310a is formed in a region between two convex type sidewalls where the bit line contact plugs 310 are opposite to each other.
In this embodiment, the bit line contact plug 310 has the arc-shaped sidewall 310b in each of two opposite sidewalls extending in the first direction, and the two arc-shaped sidewalls 310b are oppositely disposed. And, a void 310a in the bit line contact plug 310 may be further formed in a region between two arc-shaped sidewalls 310b facing each other.
As described above, the bit line contact plug 310 is further embedded in the substrate 100, and it can be considered that, in the present embodiment, a portion of the bit line contact plug 310 embedded in the substrate 100 constitutes a third portion, and a portion of the bit line contact plug 310 corresponding to between two arc-shaped sidewalls 310b facing each other constitutes a second portion.
In the present embodiment, the void 310a is formed in the second portion of the bit line contact plug 310, that is, the void 310a is formed in the portion of the bit line contact plug 310 that is higher than the substrate 100. It is understood that, in this embodiment, the sidewall of the second portion is also protruded relative to the sidewall of the third portion, and at this time, the second portion has a larger width dimension based on the second portion although the gap 310a is formed therein, so that the electrical performance of the second portion can still be ensured.
It should be noted that, by disposing the void 310a in the portion of the bit line contact plug 310 higher than the substrate 100, the void 310a in the bit line contact plug 310 can be disposed away from the active area AA, so as to avoid the void 310a from being close to the active area AA, which is beneficial to ensuring the connection performance between the bit line 300 and the active area AA.
Of course, the bottom of the void 310a in the bit line 300 may also be made lower than the top surface of the substrate 100 as long as it is ensured that the void 310a in the bit line 300 does not extend to the doped surface of the active region AA.
With continued reference to fig. 2a and 2b, the bit line contact plug 310 further has a first portion that is located above the second portion, and the maximum width dimension of the first portion is smaller than the maximum width dimension of the second portion. That is, in the present embodiment, the side wall of the second portion is convex with respect to both the first portion and the third portion.
In an alternative scheme, the bit line contact plug 310 may also have a second portion with a height dimension greater than that of the first portion. At this time, a sufficient forming space may be provided for the void 310a, or it may be understood that a volume of a portion of the bit line 300, which can be deposited by using a rapid deposition method, is increased, which is advantageous for further improving the manufacturing efficiency of the bit line 300.
With continued reference to fig. 2a and 2b, the bit line 300 further includes a second conductive layer 320, and the second conductive layer 320 is formed on the bit line contact plug 310 for further electrical transmission. Specifically, the material of the second conductive layer 320 includes, for example, tungsten or the like.
Alternatively, the maximum width dimension of the bit line contact plug 310 is greater than the maximum width dimension of the second conductive layer 320. It should be noted that, since the bit line contact plug 310 has a larger width dimension (i.e., the maximum width dimension of the bit line contact plug 310 is larger than the maximum width dimension of the second conductive layer 320), it is correspondingly beneficial to increase the electrical transmission performance of the bit line contact plug 310, and therefore, even if the void 310a is formed in the bit line contact plug 310, the overall performance of the bit line contact plug 310 can still be ensured. In addition, while the width dimension of the bit line contact plug 310 is increased, it is also advantageous to achieve an increase in the contact area between the bit line contact plug 310 and the active area AA to improve the connection performance between the bit line contact plug 310 and the active area AA. As can be seen, even if the void 310a is formed in the bit line contact plug 310, the performance of the bit line contact plug 310 is not greatly affected.
Further, the bit line contact plug 310 has a portion protruding in a width direction, i.e., a second direction (X direction), with respect to the second conductive layer 320, so that a maximum width dimension of the bit line contact plug 310 is greater than a maximum width dimension of the second conductive layer 320. And, a height position of the void 310a in the bit line contact plug 310 corresponds to a height position of the protruding portion of the bit line contact plug 310. In this embodiment, the protruding portion of the bit line contact plug 310 corresponds to the portion of the arc-shaped sidewall 310 b.
With continued reference to fig. 2a and 2b, the bit line 300 further includes a third conductive layer 330, the third conductive layer 330 being formed between the bit line contact plug 310 and the second conductive layer 320. The material of the third conductive layer 330 includes, for example, titanium nitride and the like.
In this embodiment, the third conductive layer 330 is formed on the first portion of the bit line contact plug 310, and a sidewall of the third conductive layer 330 may be aligned with a sidewall of the first portion.
Further, the bit line 300 further includes a cap layer 340, and the cap layer 340 is formed on the second conductive layer 320 to cover the second conductive layer 320. Wherein, the material of the cap layer 340 includes silicon nitride, for example. In this embodiment, the sidewalls of the cover layer 340, the second conductive layer 320, and the third conductive layer 330 are aligned.
Referring to fig. 2b, an isolation layer 400 is further formed on the top surface of the substrate 100, and the bit line 300 is partially formed on the isolation layer 400. Specifically, a portion of the bit line 300 connected to the active area AA penetrates the isolation layer 400 to extend to the top surface of the substrate 100, and a portion of the bit line 300 not connected to the active area AA is formed on the isolation layer 400 to separate the bit line 300 and the substrate 100 by the isolation layer 400. Wherein, the material of the isolation layer 400 includes, for example, one or a combination of silicon nitride and silicon oxide.
Based on the semiconductor device as described above, a method of forming the semiconductor device is explained below. Fig. 3 is a schematic flow chart of a method for forming a semiconductor device according to an embodiment of the present invention, and as shown in fig. 3, the method for forming a semiconductor device includes:
step S100, providing a substrate, wherein a plurality of active regions are defined in the substrate;
step S200, forming at least one grid groove in the substrate, wherein at least part of the grid groove is positioned in the active region;
step S300, filling a buried gate electrode and an insulating material layer in the gate trench in sequence;
step S400, forming a bit line contact plug on the substrate, wherein the bit line contact plug is also partially formed on the insulating material layer and coupled to the active region, and a void is formed in the bit line contact plug.
Next, a method for forming the semiconductor device in this embodiment will be described in further detail with reference to fig. 4a to 4 e. Fig. 4a to 4e are schematic structural diagrams of a method for forming a semiconductor device in a manufacturing process of the semiconductor device according to an embodiment of the present invention.
In step S100, specifically referring to fig. 4a, a substrate 100 is provided, wherein a plurality of active areas AA are defined in the substrate 100. In this embodiment, the active area AA has a first source/drain area 110 and a second source/drain area 120 formed therein.
Specifically, a trench isolation structure 101 is formed in the substrate 100, so that the active area AA is defined by the trench isolation structure 101.
In step S200, with continued reference to fig. 4a, at least one gate trench 200a is formed in the substrate 100, wherein the gate trench 200a is at least partially located in the active area AA. In this embodiment, the word line trenches 200a extend along the second direction and intersect the corresponding active regions AA. And, the first source/drain region 110 and the second source/drain region 120 in the active area AA are respectively located at both sides of the word line trench 200 a.
In step S300, with continued reference to fig. 4a, a buried gate electrode 200 and a layer of insulating material 210 are sequentially filled in said gate trench 200 a.
In this embodiment, the buried gate electrode 200 is used to constitute a word line of a memory, and the top surface of the buried gate electrode 200 is lower than the top surface of the word line trench 200a, based on which the insulating material layer 210 may be filled in the space where the word line trench 200a is higher than the buried gate electrode 200 to cover the buried gate electrode 200.
In a further aspect, after forming the buried gate electrode 200, the method further includes: an isolation layer 400 is covered on the top surface of the substrate 100, and the isolation layer 400 correspondingly covers the active area AA.
In this embodiment, the isolation layer 400 may be formed while filling the insulating material layer 210. For example, the following are: an insulating material is deposited over the substrate 100, filling the wordline trench 200a and covering the top surface of the substrate 100, and a planarization process is performed to planarize the insulating material, wherein the insulating material remaining in the wordline trench 200a constitutes the insulating material layer 210 and the insulating material covering the top surface of the substrate constitutes the isolation layer 400.
In step S400, referring specifically to fig. 4b to 4d, a bit line contact plug 310 is formed on the substrate 100, the bit line contact plug 310 is also formed locally on the insulating material layer 210 and coupled to the active region AA, and a void 310a is formed in the bit line contact plug 310.
Specifically, the method for forming the bit line contact plug 310 includes the following steps, for example.
Step S410, specifically referring to fig. 4b to 4c, a sacrificial layer is formed on the substrate 100, wherein at least one bit line trench 600 is formed in the sacrificial layer, and the bit line trench 600 extends along a first direction. The bit line trench 600 is utilized to accommodate the first conductive layer in the bit line in a subsequent process.
Referring to fig. 4c, the sacrificial layer includes a first sacrificial material layer 510 and a second sacrificial material layer 520 stacked from top to bottom, and the bit line trench 600 has a first recess 610 and a second recess 620 connected to each other. Specifically, the first recess 610 is formed in the first sacrificial material layer 510, the second recess 620 is formed in the second sacrificial material layer 520, and the first recess 610 is located above the second recess 620.
The method for forming the bit line groove comprises the following steps:
step one, specifically referring to fig. 4b, sequentially forming a second sacrificial material layer 520 and a first sacrificial material layer 510 on the substrate 100;
step two, continuing to refer to fig. 4b, patterning the first sacrificial material layer 510 to form a first groove 610 in the first sacrificial material layer 510, the first groove 610 extending along a first direction;
step three, specifically referring to fig. 4c, etching the second sacrificial material layer 520 through the first groove 610 in the first sacrificial material layer 510 to form a second groove 620 in the second sacrificial material layer 520, and recessing a sidewall of the second groove 620 relative to a sidewall of the first groove 610, so that a maximum opening size of the second groove 620 is larger than a maximum opening size of the first groove 610. Specifically, the side wall of the recess in the second groove 620 is, for example, an arc-shaped side wall.
Specifically, the second sacrificial material layer 520 is etched by using an etching process to form the second recess 620, and in the etching process, the second sacrificial material layer 520 and the first sacrificial material layer 510 have a larger etching selection ratio (for example, the etching selection ratio is greater than or equal to 4:1), so that the etching rate of the second sacrificial material layer 520 can be increased, and the first sacrificial material layer 510 is prevented from being damaged greatly.
In addition, the opening size of the formed second recess 620 may be adjusted by controlling the etching time of the etching process. For example, the etching time of the second sacrificial material layer 520 may be increased to increase the opening size of the second recess 620; conversely, the etching time of the second sacrificial material layer 520 may be reduced to reduce the opening size of the second recess 620.
In this embodiment, by forming the bit line trench 600 with a narrow top and a wide bottom, the bit line trench 600 can be filled more quickly when the first conductive layer is formed by a subsequent rapid deposition process, so as to improve the preparation efficiency of the bit line contact plug.
In a further aspect, the bottom of the bit line trench 600 also extends into the substrate 100, i.e., the bit line trench 600 also extends from above the top surface of the insulating material layer 210 to a predetermined depth position of the insulating material layer, which is above the top surface of the buried gate electrode 200. And, the portion of the bit line trench 600 extending into the substrate 100 forms a third recess 630, and the third recess 630 exposes the active area AA.
Specifically, the method for forming the third recess 630 in the bit line trench 600 includes: portions of the substrate 100 corresponding to the active area AA are etched through the first recess 610 and the second recess 620 to form a third recess 630 in the substrate 100. In this embodiment, the third recess 630 exposes the first source/drain region 110 in the active area AA.
Optionally, a length dimension of the bottom surface of the third recess 630 in the first direction may be greater than or equal to a length dimension of the first source/drain region 110 in the first direction, so that the first source/drain region 110 may expose the contact surface to a greater extent to increase a contact area between a subsequently formed bit line and the first source/drain region 110.
In this embodiment, the length dimension of the bottom surface of the third recess 630 in the first direction is greater than the length dimension of the first source/drain region 110 in the first direction, so that the third recess 630 extends into the word line trench 200a and stops at the insulating material layer 210 in the word line trench 200 a.
In addition, as described above, the isolation layer 400 is further formed on the top surface of the substrate 100, and based on this, the isolation layer 400 located above the first source/drain region 110 is further etched to expose the first source/drain region 110 when the bit line trench 600 is formed.
In step S420 of preparing the bit line contact plug 310, as shown in fig. 4d, a first conductive layer is filled in the bit line trench 600, and at least one void 310a is further formed in the first conductive layer, so as to constitute the bit line contact plug 300 with the first conductive layer.
In this embodiment, the bit line trench 600 includes a third recess 630, a second recess 620 and a first recess 610 which are connected up and down. Based on this, a deposition process may be performed when the first conductive layer is formed, and the deposited first conductive material fills the third groove 630, the second groove 620, and the first groove 610. Wherein the deposition process comprises, for example, a chemical vapor deposition process.
It should be noted that, since the second recess 620 has a larger opening size, when the first conductive material is deposited, the void 310a is easily formed in the first conductive material filled in the second recess 620. For example, during the deposition process, the first conductive material grows along the inner wall of the second recess 620 and closes at the top of the second recess 620, so that the voids 310a are formed in the second conductive material formed in the second recess 620.
In particular, in the present embodiment, the first groove 610 with a smaller opening size is further communicated above the second groove 620, so that in the process of depositing the first conductive material, the first conductive material filled in the second groove 620 is more easily closed at a position adjacent to the first groove 610, and further the gap 310a is formed.
Further, the method for forming the bit line contact plug 310 further includes a planarization process. That is, when a first conductive material is deposited on the substrate 100 using a deposition process, the first conductive material fills the bit line trench 600 and protrudes out of the bit line trench while also covering the top surface of the sacrificial layer; then, the first conductive material is planarized by a planarization process to remove the first conductive material higher than the bit line trench 600, and the first conductive material filled in the bit line trench 600 remains to form the bit line contact plug 310, so that the formed bit line contact plug 310 is not higher than the sacrificial layer (e.g., the top surface of the bit line contact plug 310 is flush with the top surface of the sacrificial layer).
That is, in the present embodiment, the width dimension of the formed first conductive layer is adjusted by using the bit line trench 600 in the sacrificial layer, so as to ensure the contact area between the formed bit line contact plug 310 and the active area AA. At this time, even if the void 310a is formed in the bit line contact plug 310, the electrical performance of the bit line contact plug 310 may be ensured, and since the void 310a is allowed to be formed in the bit line contact plug 310, the first conductive layer may be formed using a rapid deposition process to improve the fabrication efficiency of the semiconductor device.
In a further aspect, the semiconductor device further includes: in step S500, a second conductive layer is formed on the bit line contact plug 310.
Specifically, in step S500, referring specifically to fig. 4e, a second conductive layer 320 is formed on the bit line contact plug 310. In this embodiment, the second conductive layer 320 and the bit line contact plug 310 are used to form a bit line 300 of a memory, and the maximum width dimension of the second conductive layer 320 is smaller than the maximum width dimension of the bit line contact plug 310.
The second conductive layer 320 is formed by a deposition process and a patterning process. Specifically, the method for forming the second conductive layer 320 includes: first, a deposition process is performed to deposit a second conductive material layer on the substrate 100, the second conductive material layer covering the sacrificial layer and the bit line contact plugs 310; next, a patterning process is performed to pattern the second conductive material layer to form the second conductive layer 320, and the second conductive layer 320 is formed on the bit line contact plug 310. In this embodiment, the width of the second conductive layer 320 is the same as or similar to the width of the portion of the bit line contact plug 310 formed in the first groove 610.
Further, the method of patterning the second conductive material layer to form the second conductive layer 320 includes: and forming a patterned mask layer on the second conductive material layer, and etching the second conductive material layer by using the mask layer as a mask to form the second conductive layer 320. In this embodiment, after the second conductive material layer is etched, the mask layer is remained to form the cap layer 340 in the bit line 300.
With continued reference to fig. 4e, the bit line 300 of the present embodiment further includes a third conductive layer 330, wherein the third conductive layer 330 is formed between the bit line contact plug 310 and the second conductive layer 320. The third conductive layer 330 and the second conductive layer 320 may be formed by using the same patterning process. That is, after the second conductive material layer is etched using the mask layer as a mask, the exposed third conductive material layer is further etched to form the third conductive layer 330. The sidewalls of the second and third conductive layers 320 and 330 may be made flush.
It should be noted that, in this embodiment, after the bit line contact plug 310 is formed, the sacrificial layer (including the first sacrificial material layer 510 and the second sacrificial material layer 520) is not removed, and at this time, a flat surface can be formed by the sacrificial layer and the bit line contact plug 310, so that a flat surface can be provided when the third conductive layer 330 and the second conductive layer 320 are formed subsequently. It should be appreciated that the planar surface is advantageous to improve the process accuracy of the deposition process, the photolithography process, and the etching process, so that the patterns of the second conductive layer 320 and the third conductive layer 330 can be more precisely defined, and accordingly, the pattern accuracy of the formed bit line 300 is improved.
And, after the bit line 300 is formed, the sacrificial layer may be removed.
Example two
The difference from the first embodiment is that the cross-sectional shape of the bit line contact plug in the present embodiment is a trapezoid, and the length of the lower base of the trapezoid cross-section of the bit line contact plug is greater than the length of the upper base. That is, in this embodiment, the width of the bit line contact plug is sequentially increased from top to bottom, so that the bottom of the bit line contact plug can be in full contact with the active region.
Fig. 5 is a schematic structural view of a semiconductor device according to a second embodiment of the present invention, and as shown in fig. 5, a cross section of the bit line contact plug 310 'in a direction perpendicular to the first direction is a trapezoidal cross section (i.e., a cross section of the bit line contact plug 310' in a width direction is a trapezoidal cross section). Wherein, the portion of the bit line contact plug 310' extending from the top surface of the insulating material layer 210 to the predetermined depth position constitutes a lower portion of the bit line contact plug, the cross section of the lower portion of the bit line contact plug is correspondingly a trapezoidal cross section, and the length of the lower base of the trapezoidal cross section of the lower portion of the bit line contact plug is greater than the length of the upper base.
In this embodiment, the length dimension of the lower bottom edge of the trapezoidal cross section of the bit line contact plug 310' is further greater than the width dimension of the second conductive layer 320. Further, the length dimension of the upper base of the trapezoidal cross section of the bit line contact plug 310' is the same as or similar to the width dimension of the second conductive layer 320.
With continued reference to fig. 5, the bit line contact plug 310 ' has a void 310a ' formed therein, wherein the void 310a ' may be formed in a portion of the bit line contact plug 310 ' above the top surface of the substrate such that the void 310a ' is distant from the active region AA. Of course, the void 310a 'may also be located in a portion where the bit line contact plug 310' is embedded in the substrate, that is, the void 310a 'may also be located below the bit line contact plug as long as the void 310 a' does not contact the surface of the active region AA.
Similar to the embodiment, when the bit line contact plug 310 'is prepared, a sacrificial layer may be preferentially used to define a bit line trench, and then a first conductive layer may be refilled in the bit line trench, thereby forming the bit line contact plug 310'.
It should be noted that the bit line contact plugs 310' formed in the present embodiment have a trapezoidal shape with a lower base longer than an upper base. Based on this, when the bit line trench is prepared, the preparation method thereof includes, for example:
forming a first pattern layer on the substrate, wherein the first pattern layer corresponds to the pattern of the bit line groove, and two side walls of the first pattern layer along the extending direction are inclined side walls;
filling second graphic layers on two sides of the first graphic layer, wherein the side wall of each second graphic layer is correspondingly attached to the inclined side wall of the first graphic side to form an inclined side wall, and the connecting angle between the inclined side wall of each second graphic layer and the substrate is an acute angle;
and then, removing the first graphic layer, wherein the vacant space corresponds to the bit line groove, and the bit line groove is in a trapezoidal structure with a narrow top and a wide bottom.
Further, the bit line trench may further extend into the substrate, similar to the embodiment. That is, the bit line trench also extends from above the top surface of the insulating material layer 210 to a predetermined depth position of the insulating material layer 210, which is above the top surface of the buried gate electrode 200. And, a portion of the bit line trench extending from the top surface of the insulating material layer 210 to the predetermined depth position constitutes a third groove, a cross section of the third groove is further a trapezoidal cross section, and a length of a lower base of the trapezoidal cross section of the third groove is greater than a length of an upper base.
In addition, after the bit line contact plug 310' is formed, the third conductive layer 330, the second conductive layer 320 and the cover layer 340 may be formed continuously, and the forming method thereof is similar to that of the embodiment and is not repeated herein.
In summary, in the semiconductor device provided in the present embodiment, since the bit line contact plug can be sufficiently contacted with the active region, even if the bit line contact plug has a void formed therein, the electrical transmission performance between the bit line contact plug and the active region can be ensured. And aiming at the bit line contact plug which is allowed to form the gap, the manufacturing difficulty is lower, the preparation process of the bit line contact plug is facilitated to be accelerated, the productivity of a semiconductor device is correspondingly improved, and the utilization rate of semiconductor processing equipment is improved.
Particularly for the memory, the maximum width dimension of the bit line contact plug of the bit line can be further larger than the dimension of the second conductive layer, so that the electrical transmission performance of the bit line contact plug can be improved, and the contact area between the bit line contact plug and the active region can be increased.
Furthermore, the bit line contact plug in the bit line can be extended into the substrate to be electrically connected with the active region in the substrate, so that the contact area between the bit line contact plug and the active region can be further increased, the bit line contact plug can be electrically connected with a region with high ion concentration in the active region, and the signal transmission performance between the bit line contact plug and the active region can be further improved.
It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims (20)

1. A semiconductor device, comprising:
the semiconductor device comprises a substrate, a plurality of active regions and at least one grid groove, wherein the grid groove is at least partially positioned in the active regions;
the buried gate electrode and the insulating material layer are sequentially filled in the gate trench; and the number of the first and second groups,
a bit line contact plug formed locally on the insulating material layer and coupled to the active region, and a void provided in the bit line contact plug.
2. The semiconductor device of claim 1, wherein the bit line contact plug extends from above a top surface of the layer of insulating material to a predetermined depth position of the layer of insulating material, the predetermined depth position being above a top surface of the buried gate electrode.
3. The semiconductor device according to claim 2, wherein a portion of the bit line contact plug extending from the top surface of the insulating material layer to the predetermined depth position constitutes a bit line contact plug lower portion, a cross section of the bit line contact plug lower portion is a trapezoidal cross section, and a length of a lower base of the trapezoidal cross section of the bit line contact plug lower portion is larger than a length of an upper base.
4. The semiconductor device according to claim 1, wherein the bit line contact plug has two convex-type sidewalls facing each other, and the void is formed in a region between the two convex-type sidewalls facing each other.
5. The semiconductor device of claim 4, wherein the convex sidewall is an arcuate sidewall.
6. A memory, comprising:
a substrate having a plurality of active regions formed therein;
the bit line comprises a first conductive layer and a second conductive layer which are stacked from bottom to top, the first conductive layer is coupled to the active region and used for forming a bit line contact plug, the maximum width dimension of the bit line contact plug is larger than that of the second conductive layer, and at least one gap is formed in the bit line contact plug.
7. The memory according to claim 6, wherein the first conductive layer has an arc-shaped sidewall that is convex with respect to the second conductive layer, among sidewalls extending in the first direction.
8. The memory of claim 7, wherein the two opposing sidewalls of the first conductive layer extending along the first direction each have the curved sidewalls, and wherein the two curved sidewalls are disposed in facing relation, and wherein the void is formed in a region between the two curved sidewalls of the first conductive layer in facing relation to each other.
9. The memory according to claim 6, wherein a cross section of the first conductive layer in a direction perpendicular to the first direction is a trapezoidal cross section, and a length dimension of a lower base of the trapezoidal cross section is larger than a width dimension of the second conductive layer.
10. The memory of claim 6, wherein the void is formed in a portion of the first conductive layer above a top surface of the substrate.
11. The memory of claim 6, wherein the first conductive layer includes a first portion and a second portion, the first portion is on the second portion, and a sidewall of the second portion is convexly disposed with respect to a sidewall of the first portion, and the void is formed in the second portion.
12. A method of forming a semiconductor device, comprising:
providing a substrate, wherein a plurality of active regions are defined in the substrate;
forming at least one gate trench in the substrate, the gate trench being at least partially located in the active region;
sequentially filling a buried gate electrode and an insulating material layer in the gate trench; and the number of the first and second groups,
forming a bit line contact plug on the substrate, the bit line contact plug also being formed partially on the insulating material layer and coupled to the active region, and a void being formed in the bit line contact plug.
13. The method for forming a semiconductor device according to claim 12, wherein the method for forming the bit line contact plug comprises:
forming a sacrificial layer on the substrate, wherein at least one bit line groove is formed in the sacrificial layer and extends along a first direction; and the number of the first and second groups,
and filling a first conductive layer in the bit line trench, wherein the first conductive layer is used for forming the bit line contact plug, and at least one gap is formed in the first conductive layer.
14. The method for forming a semiconductor device according to claim 13, wherein the method for forming the sacrificial layer having the bit line trench includes:
sequentially forming a second sacrificial material layer and a first sacrificial material layer on the substrate;
patterning the first sacrificial material layer to form a first groove in the first sacrificial material layer, the first groove extending along a first direction; and the number of the first and second groups,
and etching the second sacrificial material layer through the first groove in the first sacrificial material layer to form a second groove in the second sacrificial material layer, wherein the side wall of the second groove is recessed relative to the side wall of the first groove, so that the maximum opening size of the second groove is larger than that of the first groove.
15. The method of forming a semiconductor device according to claim 14, wherein a sidewall of the second groove recess is an arc-shaped sidewall.
16. The method for forming a semiconductor device according to claim 14, wherein the method for forming the first conductive layer comprises:
depositing a first conductive material on the substrate to fill the second recess and the first recess, and forming the void in the first conductive material formed in the second recess.
17. The method of forming a semiconductor device of claim 13, wherein the bit line trench further extends from above a top surface of the layer of insulating material to a predetermined depth position of the layer of insulating material, the predetermined depth position being above a top surface of the buried gate electrode.
18. The method for forming a semiconductor device according to claim 17, wherein a portion of the bit line trench extending from the top surface of the insulating material layer to the predetermined depth position constitutes a third groove, a cross section of the third groove is a trapezoidal cross section, and a length of a lower base of the trapezoidal cross section of the third groove is larger than a length of an upper base.
19. The method of forming a semiconductor device according to claim 12, further comprising, after forming the bit line contact plug:
forming a second conductive layer on the bit line contact plug, and a maximum width dimension of the second conductive layer is smaller than a maximum width dimension of the first conductive layer.
20. The method for forming a semiconductor device according to claim 19, wherein the method for forming the second conductive layer comprises:
performing a deposition process to form a second conductive material layer on the substrate, the second conductive material layer covering the bit line contact plug;
and performing a patterning process to pattern the second conductive material layer to form a second conductive layer, wherein the second conductive layer is formed on the first conductive layer and extends along the first direction.
CN201910877052.XA 2019-09-17 2019-09-17 Semiconductor device, forming method thereof and memory Pending CN111640746A (en)

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US16/635,465 US11164877B2 (en) 2019-09-17 2019-12-11 Semiconductor device having void in bit line contact plug
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