CN111640743B

CN111640743B - Memory and forming method thereof

Info

Publication number: CN111640743B
Application number: CN201910487210.0A
Authority: CN
Inventors: 詹益旺; 黄永泰; 童宇诚; 朱贤士; 黄丰铭; 巫俊良
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2019-06-05
Filing date: 2019-06-05
Publication date: 2022-02-08
Anticipated expiration: 2039-06-05
Also published as: CN111640743A

Abstract

The invention provides a memory and a forming method thereof. The width dimension of a first conductive layer of a bit line in the memory is smaller than that of a second conductive layer above the bit line, so that the bottom space dimension between adjacent bit lines can be larger than the top space dimension of the bit line. Therefore, the width dimension of the second conductive layer is satisfied to ensure the transmission performance of the bit line, and the bottom space dimension between the adjacent bit lines is increased, which is beneficial to further increasing the bottom dimension of the storage node contact part filled between the adjacent bit lines.

Description

Memory and forming method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a memory and a forming method thereof.

Background

A memory typically includes a storage capacitor for storing charge representative of stored information, and a storage transistor connected to the storage capacitor. And, the memory typically has a plurality of word lines and bit lines therein for controlling the selected memory transistors.

Fig. 1 is a schematic structural diagram of a conventional memory, and as shown in fig. 1, a bit line BL of the conventional memory includes a plurality of film layers stacked in sequence from bottom to top, and width dimensions of the film layers are all the same. Specifically, when the bit line BL is formed, the bit line BL is formed on the basis of the same mask pattern layer, and each film layer is usually etched by using an anisotropic etching process, so that the pattern in the mask pattern layer can be accurately copied to each film layer.

However, as the size of the memory device is continuously reduced, the space between adjacent bit lines BL is limited, which results in a smaller size of the storage node contact portion filled between adjacent bit lines BL, which is not favorable for the electrical connection between the storage node contact portion and the active region, and if the width of the bit line is directly reduced, the transmission performance of the bit line is inevitably affected.

Disclosure of Invention

The invention aims to provide a memory, which solves the problem that the transmission performance of bit lines and the space size between adjacent bit lines are difficult to balance in the conventional memory.

To solve the above technical problem, the present invention provides a memory, including:

the semiconductor device comprises a substrate, a plurality of bit line contact windows and a plurality of control circuits, wherein a plurality of active regions are formed in the substrate, and a plurality of bit line contact windows are also formed in the substrate, and at least part of the active regions are exposed in the bit line contact windows; and the number of the first and second groups,

the bit lines are formed on the substrate and extend along a first direction and intersect with corresponding active regions, the bit lines comprise a first conductive layer and a second conductive layer which are stacked from bottom to top, the width dimension of the first conductive layer is smaller than that of the second conductive layer, a bit line contact portion is formed by a part of the bit lines, which intersects with the active regions, and the bottom of the first conductive layer in the bit line contact portion extends into the bit line contact window.

Based on the memory, the invention also provides a forming method of the memory, which comprises the following steps:

providing a substrate, wherein a plurality of active regions are formed in the substrate;

forming a plurality of bit line contact windows in the substrate, wherein the bit line contact windows expose at least part of the active region;

sequentially forming a first conductive material layer and a second conductive material layer on the substrate, filling the bit line contact windows, and forming a patterned mask pattern layer on the second conductive material layer, wherein the mask pattern layer comprises a plurality of mask lines, and the mask lines extend along a first direction;

performing a first etching process by using the mask pattern layer as a mask, wherein the first etching process comprises etching the second conductive material layer to form a patterned second conductive layer; and the number of the first and second groups,

and executing a second etching process, wherein the second etching process comprises etching the first conductive material layer to form a patterned first conductive layer, in the process of executing the second etching process, an etchant laterally erodes the first conductive material layer positioned right below the second conductive layer so as to enable the width dimension of the formed first conductive layer to be smaller than that of the second conductive layer, and the first conductive layer and the second conductive layer are utilized to form a bit line of the memory.

In the memory provided by the invention, the width dimension of the first conductive layer in the bit line can be reduced, so that the first conductive layer has a smaller width dimension relative to the second conductive layer above the first conductive layer, the bottom space dimension between adjacent bit lines is increased, the second conductive layer has a sufficient width dimension, and the transmission performance of the bit line can be still ensured at the time. Or, the width of the first conductive layer may be reduced on the basis of increasing the width of the second conductive layer, so that the width of the first conductive layer is smaller than the width of the second conductive layer, and thus, the resistivity of the second conductive layer may be further reduced on the basis of satisfying the bottom space between adjacent bit lines, which is beneficial to improving the transmission performance of the bit lines.

Therefore, the memory provided by the invention can increase the bottom size of the storage node contact part filled between the adjacent bit lines on the basis of satisfying the transmission performance of the bit lines; for another example, it is possible to further improve the transfer performance of the bit line while ensuring the bottom dimension of the storage node contact filled between the adjacent bit lines.

Drawings

FIG. 1 is a schematic diagram of a conventional memory structure;

FIG. 2a is a top view of a memory illustrating bit lines according to a first embodiment of the present invention;

FIG. 2b is a schematic cross-sectional view of the memory shown in FIG. 2a along the directions aa 'and bb' according to the first embodiment of the invention;

FIG. 3a is a top view of a memory device according to a first embodiment of the present invention illustrating a storage node contact portion;

FIG. 3b is a schematic cross-sectional view of the memory shown in FIG. 3a along the directions aa ', bb ' and cc ' according to the first embodiment of the invention;

FIG. 4 is a flow chart illustrating a method for forming a memory according to a first embodiment of the invention;

FIGS. 5a to 5b and FIGS. 6a to 6b are schematic top views and cross-sectional views illustrating a method for forming a memory according to a first embodiment of the present invention when step S100 is performed;

FIGS. 7 a-7 b are schematic top view and cross-sectional view illustrating a method for forming a memory according to a first embodiment of the invention when performing step S200;

FIGS. 8a to 8b are schematic top view and cross-sectional view illustrating a method for forming a memory according to a first embodiment of the invention when step S300 is executed;

FIGS. 9a to 9b are schematic top view and cross-sectional view illustrating a method for forming a memory according to a first embodiment of the invention when performing step S400;

fig. 10a to 10b are schematic top view and cross-sectional view illustrating a method for forming a memory according to a first embodiment of the invention when step S500 is performed;

fig. 11 is a schematic cross-sectional view illustrating a method for forming a memory according to a first embodiment of the invention when performing step S600;

fig. 12a to 12b are schematic top view and cross-sectional view illustrating a method for forming a memory according to a first embodiment of the invention when performing step S700;

fig. 13a to 13b are schematic top view and cross-sectional view illustrating a method for forming a memory according to a first embodiment of the invention when performing step S800;

FIG. 14 is a cross-sectional view of a second embodiment of a method for forming a memory device after a first etching process is performed thereon;

fig. 15 is a cross-sectional view illustrating a method for forming a memory device according to a second embodiment of the present invention after a second etching process is performed.

Wherein the reference numbers are as follows:

100-a substrate;

110-an isolation structure;

200 a-bit line contact;

210 a-a first layer of conductive material; 210-a first conductive layer;

220 a-a second layer of conductive material; 220-a second conductive layer;

230 a-a third layer of conductive material; 230-a third conductive layer;

240-a mask pattern layer;

241-mask lines; 240-a capping layer;

300 a-word line trench;

310-a gate dielectric layer; 320-a gate conductive layer;

410-a first insulating layer; 420-a second insulating layer;

500-isolating the side wall; 510-a first isolation layer;

520-a second isolation layer; 530-a third isolation layer;

600 a-storage node contact window; 600 b-a groove;

AA-active region;

S/D1-first source/drain regions; S/D2-second source/drain regions;

BL-bit line; WL-word line;

a DC-bit line contact; SC-storage node contacts;

l1 — first isolation line; l2 — second isolation line;

z1 — first granularity; z2-second granularity.

Detailed Description

The memory and the forming method thereof according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

FIG. 2a is a top view of a bit line of the memory according to the first embodiment of the present invention, and FIG. 2b is a cross-sectional view along the direction aa' of the memory according to the first embodiment of the present invention shown in FIG. 2 a. It should be noted that, in order to illustrate the memory structure in this embodiment more clearly, part of the components are omitted from fig. 2a, for example, the substrate and part of the insulating layer are not illustrated in fig. 2 a.

As shown in fig. 2a and fig. 2b, in this embodiment, the memory includes a substrate 100 and a bit line BL formed on the substrate 100, the bit line BL has a first conductive layer 210 and a second conductive layer 220, and a width of the first conductive layer 210 is smaller than a width of the second conductive layer 220 above the first conductive layer.

Specifically, a plurality of active regions AA are formed in the substrate 100, and the active regions AA have first source/drain regions S/D1 and second source/drain regions S/D2 therein.

In this embodiment, the active area AA extends obliquely with respect to the first direction (i.e., the active area AA extends along the Z direction). And the first source/drain region S/D1 in each of the active regions AA corresponds to a middle region of the active region AA, and the second source/drain regions S/D2 are formed on both ends of the active region AA (i.e., two second source/drain regions S/D2 are respectively disposed at both sides of the first source/drain region S/D1).

Further, a plurality of isolation structures 110 are formed in the substrate 100, and the isolation structures 110 surround the periphery of the active area AA and are used for isolating adjacent active areas AA. It will also be appreciated that the active area AA is defined by forming the isolation structure 110. The Isolation structure 110 may be a Shallow Trench Isolation (STI) structure.

The active area AA is used to form a memory cell of the memory, such as a memory transistor. And the first source/drain region S/D1 and the second source/drain region S/D2 may be used to form drain and source regions of the memory transistor, and the first source/drain region S/D1 is electrically connected to a bit line, and the second source/drain region S/D2 is electrically connected to a storage node contact SC to further electrically connect to a storage capacitor through the storage node contact SC.

As shown with particular reference to fig. 2a and 2b, the bit lines BL extend along a first direction (Y direction) and intersect the respective active areas AA. Specifically, a portion of the bit line BL intersecting the active area AA forms a bit line contact DC, and a bottom of the bit line contact DC is electrically connected to the active area AA. Each of the bit lines BL intersects with a plurality of active regions AA and has a plurality of bit line contacts DC, and the bit lines BL further have bit line connections connecting adjacent bit line contacts DC. It is understood that the bit line connections and the bit line contacts DC are alternately connected to constitute bit lines BL extending along the first direction (Y direction).

Further, the bit line BL includes a first conductive layer 210 and a second conductive layer 220 stacked from bottom to top, wherein the first conductive layer 210 in the bit line contact portion DC is used for electrically contacting the active area AA, and the second conductive layer 220 is disposed above the first conductive layer 210 to further achieve electrical transmission.

With continued reference to fig. 2a and 2b, the width dimension of the first conductive layer 210 is less than the width dimension of the second conductive layer 220. That is, the first conductive layer 210 is recessed with respect to the second conductive layer 220, so that the bottom space between adjacent bit lines BL is increased. Specifically, between adjacent bit lines BL, a first spacing dimension Z1 corresponding to the height position of the first conductive layer is larger than a second spacing dimension Z2 corresponding to the height position of the second conductive layer.

It should be noted that, since the second conductive layer 220 still maintains a larger width dimension, the resistivity of the second conductive layer 220 can be ensured, and the transmission performance of the bit line BL can be maintained. Therefore, the first conductive layer 210 has a relatively small width, so that the space between adjacent bit lines BL can be further increased without affecting the transmission performance of the bit lines BL. As a result, the bottom size of the storage node contact SC filled between adjacent bit lines can be increased, for example.

Alternatively, it can be understood that by further increasing the width dimension of the second conductive layer 220, the resistivity of the second conductive layer 220 is effectively improved, and the transmission performance of the bit line BL is improved. At this time, the bottom space between the adjacent bit lines BL is still large, so that the bottom size of the storage node contact SC filled between the adjacent bit lines can be secured.

With continued reference to fig. 2a and 2b, in the present embodiment, the bit line contact DC of the bit line BL is also embedded in the substrate of the active area AA. Specifically, the substrate 100 has bit line contacts 200a formed therein, and at least a portion of the active regions AA is exposed in the bit line contacts 200a (e.g., at least a portion of the first source/drain regions S/D1 is exposed in the bit line contacts 200 a). in this embodiment, the bit line contacts 200a also extend laterally from the active regions AA to the isolation structures 110 adjacent to the corresponding active regions. And, the bottom surface of the bit line contact window 200a is higher than the bottom boundary of the first source/drain region S/D1, i.e., the recess depth of the bit line contact window 200a is smaller than the doping depth of the first source/drain region S/D1.

Referring to fig. 2b, in the bit line BL, the bottom of the first conductive layer 210 in the bit line contact portion DC extends into the bit line contact windows 200a to be electrically connected to the active regions AA, and the bit line connection portion is formed on the top surface of the substrate between the adjacent bit line contact windows 200 a. Further, the top of the first conductive layer 210 in the bit line contact DC also extends out of the bit line contact 200a and is connected to the first conductive layer in the bit line connection, that is, the top surface of the first conductive layer 210 in the bit line contact DC is higher than the top of the bit line contact 200 a.

Further, the opening size of the bit line contact window 200a is larger than the width size of the first conductive layer 210 of the bit line BL (i.e., the opening size of the bit line contact window 200a in the X direction is larger than the width size of the first conductive layer 210 in the X direction), so that the first conductive layer 210 in the bit line contact DC is spaced from the sidewall of the bit line contact DC in the direction perpendicular to the first direction. In this embodiment, an insulating material layer is further filled in a spaced area between the first conductive layer 210 of the bit line contact DC and the sidewall of the bit line contact window 200 a.

With continued reference to fig. 2a, in the present embodiment, the opening of the bitline contact 200a has an elliptical shape. However, it should be appreciated that in other embodiments, the opening shape of the bitline contact 200a may also be circular, rectangular, diamond-shaped, or other polygonal shapes, and the like, which is not limited herein.

Further, the bit line BL further includes a third conductive layer 230 and a cap layer 240, the third conductive layer 230 is formed between the first conductive layer 210 and the second conductive layer 220, and the cap layer 240 is formed on the second conductive layer 220. Wherein, the material of the first conductive layer 210 includes, for example, a doped semiconductor material, more specifically, doped polysilicon (poly); the second conductive layer 220 may be a metal material layer, the material of which includes, for example, tungsten (W); the material of the third conductive layer 230 includes, for example, titanium nitride (TiN); and, the material of the cap layer 240 includes, for example, silicon nitride (SiN).

In this embodiment, the width of the third conductive layer 230 is equal to the width of the second conductive layer 220, that is, the width of the third conductive layer 230 is greater than the width of the first conductive layer 210 and equal to the width of the second conductive layer 220. However, in other embodiments, the width dimension of the third conductive layer may be smaller than the width dimension of the second conductive layer 220 and equal to the width dimension of the first conductive layer 210. Alternatively, in another embodiment, the width of the third conductive layer 230 may be greater than the width of the first conductive layer 210 and smaller than the width of the second conductive layer 220, that is, the width of the third conductive layer 230 is between the width of the first conductive layer 210 and the width of the second conductive layer 220.

With continued reference to fig. 2a and 2b, the memory further includes a plurality of word lines WL buried in the substrate 100, and extending along a second direction (X direction) and intersecting the respective active areas AA. In this embodiment, the first and second source/drain regions S/D1 and S/D2 in the active region AA are disposed at both sides of the word line WL, respectively. It is considered that the portion of the word line WL intersecting the active region AA may be used to form a gate structure of the memory transistor.

Specifically, a word line trench is formed in the substrate 100, and the word line WL is filled in the word line trench. In this embodiment, the top surface of the word line WL is lower than the top of the word line trench, and the word line trench above the word line WL is further filled with a first insulating layer 410, and the first insulating layer 410 correspondingly covers the word line WL.

In a further aspect, the memory further includes: and the isolation side wall 500 conformally covers the side wall of the bit line BL. In addition, the bit line BL and the isolation sidewall spacers 500 may further form a first isolation line L1 to further separate the storage node contacts SC adjacent in the second direction (X direction) by the first isolation line L1.

FIG. 3a is a top view of a memory device according to a first embodiment of the present invention illustrating a storage node contact portion; FIG. 3b is a schematic cross-sectional view of the memory shown in FIG. 3a along the directions aa 'and bb' according to the first embodiment of the invention. Referring to fig. 3a and fig. 3b, the isolation sidewall 500 conformally covers the sidewalls of the bit lines BL, so the outer sidewalls of the isolation sidewall 500 may reflect the outer sidewall topography of the bit lines BL.

Specifically, a first portion of the bit line BL corresponding to the first conductive layer 210 is recessed relative to a second portion of the bit line BL corresponding to the second conductive layer 220, so that an outer sidewall of the bit line BL is bent, and the isolation sidewall 500 conforms to the outer sidewall of the bit line BL and is correspondingly bent. Therefore, even if the isolation spacers 500 are formed, the bottom space between adjacent bit lines BL can be larger than the top space.

The isolation sidewall 500 may have a single-layer structure or a multi-layer structure. In this embodiment, the isolation sidewall spacer 500 has a multi-layer structure, for example, including a first isolation layer, a second isolation layer, and a third isolation layer. The material of the first isolation layer and the third isolation layer each include, for example, silicon oxide, and the material of the second isolation layer includes, for example, silicon nitride.

Further, the first isolation layer in the isolation sidewall 500 is closest to the bit line BL and is tightly attached to the sidewall of the bit line BL. In this embodiment, the outer sidewall boundary of the first isolation layer covering the first conductive layer does not exceed the outer sidewall boundary of the second conductive layer, i.e., the outer sidewall boundary of the first isolation layer covering the first conductive layer is recessed relative to the outer sidewall boundary of the second conductive layer. It can be understood that a thickness dimension of the first isolation layer in a direction perpendicular to the bit line sidewall is smaller than a retraction dimension of the first conductive layer 210 relative to the second conductive layer 220, wherein the retraction dimension of the first conductive layer 210 relative to the second conductive layer 220 is, for example: (first spacing dimension Z1-second spacing dimension Z2)/2.

And the second isolation layer in the isolation sidewall spacers 500 covers the first isolation layer to separate the first isolation layer and cover the sidewall of the bit line BL. The outer side wall boundary of the second isolation layer covering the first conductive layer can exceed the outer side wall boundary of the second conductive layer or be flush with the outer side wall of the second conductive layer. Specifically, the thickness dimension of the second isolation layer in the direction perpendicular to the bit line side wall is larger than the thickness dimension of the first isolation layer in the direction perpendicular to the bit line side wall.

In addition, in this embodiment, the "first isolation layer and the second isolation layer" are defined as a part of the "isolation sidewall spacer", that is, the "isolation sidewall spacer includes the first isolation layer and the second isolation layer". However, it is also understood that the "first isolation layer" and the "second isolation layer" exist independently from the "isolation sidewall spacer", for example, before the isolation sidewall spacer is formed, the first isolation layer and the second isolation layer are sequentially formed on the sidewall of the bit line BL, and then the isolation sidewall spacer is formed.

As shown in fig. 2a and fig. 3a, the second source/drain regions S/D2 at least partially correspond to adjacent first isolation lines L1. Accordingly, the storage node contacts SC in the memory are correspondingly filled between the adjacent first isolation lines L1 to be electrically connected to the second source/drain regions S/D2.

It should be appreciated that since the outer sidewalls of the first isolation lines L1 correspond to the outer sidewalls of the bit lines BL such that the adjacent first isolation lines L1 have a larger bottom space size therebetween, the contact area between the storage node contacts SC and the second source/drain regions S/D2 may be increased accordingly. Specifically, the width dimension of the storage node contact SC at a high position corresponding to the first conductive layer 210 is greater than the width dimension of the storage node contact SC at a high position corresponding to the second conductive layer 220.

In a specific embodiment, the memory further includes a plurality of second isolation lines L2, the second isolation lines L2 are formed on the substrate 100, and the second isolation lines L2 extend along a second direction (X direction) and intersect the first isolation lines L1 to define a plurality of storage node contact windows 600a together with the first isolation lines L1, and each of the second source/drain regions S/D2 corresponds to one of the storage node contact windows 600 a. And, the storage node contact portion SC is filled in the storage node contact window 600 a.

It can be considered that the first isolation line L1 is used to separate storage node contacts SC adjacent in the second direction (X direction), and the second isolation line L2 is used to separate storage node contacts SC adjacent in the first direction (Y direction).

In this embodiment, the second isolation line L2 is located right above the word line WL, and a projection pattern of the second isolation line L2 on the substrate surface is the same as a projection pattern of the word line WL on the substrate surface. Based on this, the patterns of the word lines WL and the second isolation lines L2 may be defined using the same reticle, i.e., the pattern of the second isolation lines L2 and the pattern of the word lines WL correspond to the same mask pattern.

Referring to fig. 2b and 3b with emphasis, in the present embodiment, a groove 600b is further formed in the substrate 100, the groove 600b is in up-and-down communication with the storage node contact 600a, and the second source/drain region S/D2 is at least partially exposed in the groove 600 b. Based on this, in this embodiment, the bottom of the storage node contact SC further extends into the groove 600b to electrically connect with the second source/drain region S/D2.

Based on the memory described above, the following description is continued on the method of forming the memory in the present embodiment.

Fig. 4 is a flowchart illustrating a method for forming a memory according to a first embodiment of the invention. The steps of forming the memory in this embodiment will be described in detail below with reference to the accompanying drawings.

Fig. 5a to 5b and fig. 6a to 6b are schematic top views and cross-sectional views illustrating a method for forming a memory according to a first embodiment of the present invention when step S100 is performed.

In step S100, specifically referring to fig. 5a to 5b and fig. 6a to 6b, a substrate 100 is provided, a plurality of active regions AA are formed in the substrate 100, and a plurality of bit line contacts 200a are further formed in the substrate 100, wherein at least a portion of the active regions AA are exposed by the bit line contacts 200 a. Note that illustration of the substrate structure is omitted in each of fig. 5a and 6a, and the first insulating layer and the second insulating layer are not illustrated in fig. 6 a.

A plurality of isolation structures 110 may be formed in the substrate 100 to define a plurality of active regions AA. And, the first and second source/drain regions S/D1 and S/D2 in the active area AA may be formed by an ion implantation process.

Further, a plurality of Word Lines (WL) extending along a second direction (X direction) and intersecting the corresponding active regions AA are formed in the substrate 100, and the first and second source/drain regions S/D1 and S/D2 in the active regions AA are disposed at both sides of the Word lines WL, respectively.

It should be noted that the forming sequence of the word lines WL and the source/drain regions S/D may be adjusted according to actual conditions. In this embodiment, the word line WL is formed first, and then the first source/drain region S/D1 and the second source/drain region S/D2 are formed.

Specifically, the method for forming the word line WL includes the following steps, for example.

A first step, shown with particular reference to fig. 6a and 6b, of forming a plurality of word line trenches 300a in said substrate 100; the word line trenches 300a extend along the second direction (X direction), and the word line trenches 300a also pass through the corresponding active regions AA, so that the subsequently formed word lines WL intersect the corresponding active regions AA.

A second step, continuing to refer to fig. 6a and 6b, of filling word line material in the word line trenches 300a to form word lines WL extending in the second direction (X-direction).

Specifically, the word line WL includes a gate dielectric layer 310 and a gate conductive layer 320, the gate dielectric layer 310 is formed on the sidewall and the bottom of the word line trench 300a, and the gate conductive layer 320 is formed on the gate dielectric layer 310 and fills the word line trench 300 a. The gate dielectric layer 310 is made of, for example, silicon oxide, silicon nitride, and/or silicon oxynitride, and the gate conductive layer 320 is, for example, a polysilicon layer or a metal layer.

In this embodiment, after the word line material is deposited, an etch-back process may be further performed on the word line material to reduce the height of the word line WL, so that the top surface of the finally formed word line WL is lower than the top of the word line trench 300 a.

With continued reference to fig. 6a and 6b, the word line WL does not completely fill the word line trench 300a, so that a first insulating layer 410 may be continuously filled in the word line trench above the word line WL, and the first insulating layer 410 covers the word line WL to prevent the word line WL from being electrically connected to other devices. And, after the first insulating layer 410 is formed, a second insulating layer 420 may be further formed on the substrate 100, the second insulating layer 420 covering the first and second source/drain regions S/D1 and S/D2. Wherein, the materials of the first insulating layer 410 and the second insulating layer 420 each include, for example, silicon nitride (SiN), silicon oxide (SiO), or the like.

Wherein the second insulating layer 420 and the first insulating layer 410 may be simultaneously formed. The forming method comprises the following steps:

first, a layer of insulating material is deposited on the substrate 100, covering the top surface of the substrate and filling the word line trenches above the word lines WL;

next, the insulating material layer may be planarized by a polishing process, and a portion of the polished insulating material layer filled in the word line trench 300a constitutes the first insulating layer 410, and a portion of the polished insulating material layer covering the substrate surface constitutes the second insulating layer 420.

Fig. 7a to 7b are schematic top view and cross-sectional view of a method for forming a memory according to a first embodiment of the invention when the method performs step S200.

In step S200, referring to fig. 7a to 7b, a plurality of bit line contacts 200a are formed in the substrate 100, wherein the bit line contacts 200a expose at least a portion of the active area AA. In this embodiment, the bit line contact 200a exposes at least a portion of the first source/drain region S/D1 (i.e., the projection of the bit line contact 200a in the height direction and the projection of the first source/drain region S/D1 in the height direction at least partially overlap).

The bit line contact 200a may be formed by performing a photolithography process on the basis of a mask, and further performing an etching process on the substrate, which is not described herein again.

With continued reference to fig. 7a and 7b, the opening size of the bitline contact 200a is larger than the size of the first source/drain region S/D1, such that the first source/drain region S/D1 is exposed to a greater extent, such that the first source/drain region S/D1 can be electrically contacted with a subsequently formed bitline contact DC with a larger area. For example, in the present embodiment, the width dimension of the bit line contact window 200a is greater than the width dimension of the first source/drain region S/D1 in both the direction perpendicular to the extension direction of the active region and in the extension direction along the active region. That is, the bit line contact 200a exposes the first source/drain region S/D1 and further exposes the isolation structure 110 adjacent to the first source/drain region in a direction perpendicular to the Z direction; and, the bit line contact 200a further exposes the first insulating layer 410 above the word line WL along the Z direction.

As described above, in the present embodiment, the opening of the bit line contact 200a is oval, however, in other embodiments, the opening of the bit line contact 200a may also be round, rectangular, diamond, or other polygons, and the like, which is not limited herein.

Fig. 8a to 8b are schematic top view and cross-sectional view illustrating a method for forming a memory according to a first embodiment of the invention when step S300 is performed.

In step S300, referring to fig. 8a to 8b in particular, a first conductive material layer 210a and a second conductive material layer 220a are sequentially formed on the substrate 100, the bit line contact window 200a is filled, and a patterned mask pattern layer 240a is formed on the second conductive material layer 220 a.

Further, the material of the first conductive material layer 210a includes, for example, a doped semiconductor material, and more specifically, doped polysilicon (poly); and, the second conductive material layer 220a may be a metal material layer, a material of which includes, for example, tungsten (W).

In this embodiment, after forming the first conductive material layer 210a and before forming the second conductive material layer 220a, a third conductive material layer 230a is formed, the third conductive material layer 230a is located between the first conductive material layer 210a and the second conductive material layer 220a, and a material of the third conductive layer 230a includes, for example, titanium nitride (TiN).

Specifically, the first conductive material layer 210a, the third conductive material layer 230a and the second conductive material layer 220a are formed by, for example:

first, a first conductive material layer 210a is deposited on the substrate 100, the first conductive material layer 210a covering the top surface of the substrate 100 and filling the bit line contact window 200 a; in this embodiment, the first conductive material layer 210a covers the second insulating layer 420 on the substrate, and the forming of the first conductive material layer 210a includes performing a planarization process, that is, the first conductive material layer 210a is a planarized film, and the planarized first conductive material layer 210a covers the surface of the substrate and fills the bit line contact 200 a;

next, the work function material layer 230a and the second conductive material layer 220a are sequentially formed on the first conductive material layer 210 a.

At this time, the work function material layer 230a and the second conductive material layer 220a are formed on the relatively flat first conductive material layer 210a, so that the top surface of the second conductive material layer 220a is correspondingly flat, and further, the mask pattern layer 240a can be formed on the second conductive material layer 220a having a flat surface, which is beneficial to improving the pattern precision in the mask pattern layer 240 a.

Referring specifically to fig. 8a, the patterned mask pattern layer 240a is used to define bit line patterns. Specifically, the mask pattern layer 240a includes a plurality of strip-shaped mask lines 241, the mask lines 241 extend along a first direction (Y direction), and each mask line 241 corresponds to a bit line pattern.

In an alternative, the mask pattern layer 240a is remained after the subsequent etching process is performed to form a cover layer for covering the formed second conductive layer and further forming a portion of the bit line BL. Accordingly, the material of the mask pattern layer 240a includes an insulating material, for example, silicon nitride (SiN).

Fig. 9a and 9b are a top view and a cross-sectional view of a method for forming a memory according to a first embodiment of the invention when step S400 is performed.

In step S400, referring to fig. 9a and 9b specifically, a first etching process is performed with the mask pattern layer 240a as a mask, where the first etching process includes etching the second conductive material layer 220a to form the patterned second conductive layer 220.

With continued reference to fig. 9b, in this embodiment, the first etching process further includes etching the third conductive material layer 230a to form a patterned third conductive layer 230. That is, in the first etching process, the second conductive material layer 220a and the third conductive material layer 230a are sequentially etched, and the etching is stopped on the first conductive material layer 210 a. At this time, the width dimensions of the third conductive layer 230 and the second conductive layer 220 may be the same as or close to the same as the width dimensions of the mask line 241. And, in a subsequent process, the first conductive material layer 210a may be etched using a second etching process.

However, in other embodiments, the first etching process includes etching the second conductive material layer 220a, and the etching stops at the third conductive material layer 230a, so that the width dimensions of the formed second conductive layer 220 and the mask line 241 are the same or nearly the same. And in a subsequent process, the third conductive material layer 230a and the first conductive material layer 210a may be etched using a second etching process.

Further, the first etching process may be an anisotropic etching process, for example, including a dry etching process, so that the pattern of the mask line 241 in the mask pattern layer 240a may be more accurately copied to the second conductive layer 220 and the third conductive layer 230.

Fig. 10a and 10b are a top view and a cross-sectional view of a method for forming a memory according to a first embodiment of the invention when step S500 is performed.

In step S500, referring to fig. 10a and 10b specifically, a second etching process is performed, where the second etching process includes etching the first conductive material layer 210a to form a patterned first conductive layer 210, and during the second etching process, an etchant laterally attacks the first conductive material layer directly under the second conductive layer 220, so that the size of the formed first conductive layer 210 is smaller than the size of the second conductive layer 220 (specifically, in an extending direction perpendicular to the bit line, the width of the first conductive layer 210 is smaller than the width of the second conductive layer 220).

It should be noted that, in the present embodiment, by reducing the width of the second conductive layer 220, the dimension of the space between the first conductive layers 210 in the adjacent bit lines BL is increased, that is, the dimension of the space between the bottoms of the adjacent bit lines BL is increased. In addition, the size of the second conductive layer 220 in the bit line BL is not reduced, so that the resistivity of the second conductive layer 220 can be ensured, and the formed bit line BL has better telecommunication transmission performance.

Alternatively, it can be further understood that, when the bit line pattern is defined by using the mask line 241, the width dimension of the mask line 241 may be increased, so that after the first etching process, the width dimension of the formed second conductive layer 220 may be correspondingly increased, and in the second etching process, the over-etching time of the first conductive material layer 210a is adjusted to retract the formed first conductive layer 210 relative to the second conductive layer. Thus, the width of the second conductive layer 220 can be further increased on the basis of ensuring the bottom space between adjacent bit lines BL, thereby improving the transmission performance of the bit lines BL.

With continued reference to fig. 10a, the second source/drain region S/D2 in the active region AA at least partially corresponds to the adjacent bit line BL, so that when the bottom of the adjacent bit line BL has a larger space dimension, the storage node contact window corresponding to the second source/drain region S/D2 is correspondingly provided with a larger opening dimension, thereby facilitating the subsequent filling of conductive material in the storage node contact window and increasing the contact area of the formed storage contact with the second source/drain region S/D2.

As described above, after the etching process is performed, the mask line 241 may be left and used to constitute a capping layer of the bit line BL. Therefore, in the present embodiment, the bit line BL includes a first conductive layer 210, a third conductive layer 230, a second conductive layer 220, and a capping layer 240. It should be appreciated that the remaining cap layer 240 has insulating properties, so as to cover the top of the second conductive layer 220 in the bit line, thereby preventing the second conductive layer 220 from being electrically connected to other devices.

In this embodiment, the second etching process may be an isotropic etching process, for example, a wet etching process. Therefore, the etchant in the second etching process can not only attack the first conductive material layer 210a vertically, but also attack the first conductive material layer 210a laterally, so that the etchant can attack the first conductive material layer directly under the second conductive layer 220 laterally, and the width of the finally formed first conductive layer 210 is reduced relative to the width of the second conductive layer 220. The reduction value of the width dimension of the first conductive layer 210 relative to the second conductive layer 220 can be adjusted according to actual conditions, and the required reduction value can be obtained by adjusting the over-etching time of the second etching process.

Further, in the second etching process, a larger etching selection ratio is provided between the first conductive material layer and the second conductive material layer (for example, the etching selection ratio between the first conductive material layer and the second conductive material layer is greater than or equal to 10:1), so that the second conductive layer 220 can be prevented from being consumed or only slightly consumed when the first conductive material layer 210a is laterally eroded.

It should be noted that, in this embodiment, the first etching process includes etching the third conductive material layer 230a to form the patterned third conductive layer 230, and therefore the second etching process only includes etching the first conductive material layer 210 a.

However, in other embodiments, when the first etching process does not include etching the third conductive material layer 230a and the etching stops at the third conductive material layer 230a, the second etching process includes sequentially etching the third conductive material layer and the first conductive material layer to form the patterned third conductive layer and the patterned first conductive layer. At this time, the etchant in the second etching process also laterally attacks the third conductive material layer, so that the width of the formed third conductive layer is correspondingly smaller than the width of the second conductive layer 220. That is, in other embodiments, the width dimension of the third conductive layer is the same as the width dimension of the first conductive layer 210, and is smaller than the width dimension of the second conductive layer 220.

Alternatively, in another embodiment, the first etching process does not include etching the third conductive material layer 230a, and the second etching process includes etching the third conductive material layer and the first conductive material layer, but the second etching process has different etching selectivity for the third conductive material layer and the first conductive material layer, for example, the etching rate for the first conductive material layer is higher than that for the third conductive material layer. Thus, the width dimension of the formed third conductive layer is between the first conductive layer and the second conductive layer.

With continuing reference to fig. 10a and 10b, and as shown in fig. 9a, the width dimension of the mask line 241 in the mask pattern layer 240a in the direction perpendicular to the extension direction of the bit line is smaller than the width dimension of the bit line contact 200a in the direction perpendicular to the extension direction of the bit line (i.e., in the X direction, the width dimension of the mask line 241 is smaller than the width dimension of the bit line contact 200 a). Based on this, in the formed bit line BL, a part of the sidewall of the first conductive layer 210 is spaced from the sidewall of the bit line contact 200 a.

In a further aspect, after forming the bit line BL, the method further includes: step S600, forming an isolation sidewall, where the isolation sidewall at least covers the sidewall of the bit line BL, so as to prevent the sidewalls of the first conductive layer 210 and the second conductive layer 220 in the bit line BL from being exposed.

Fig. 11 is a cross-sectional view illustrating a method for forming a memory according to a first embodiment of the invention when performing step S600. Referring to fig. 11, the isolation sidewall spacers 500 are conformal sidewalls covering the bit lines BL.

Specifically, a first portion of the bit line BL corresponding to the first conductive layer 210 is recessed relative to a second portion of the bit line BL corresponding to the second conductive layer 220, so that an outer sidewall of the bit line BL is bent, and the isolation sidewall 500 conforms to the outer sidewall of the bit line BL and is correspondingly bent. In this way, even after the isolation spacers 500 are formed, the bottom of the adjacent bit lines BL is still larger than the top of the adjacent bit lines BL.

In an optional scheme, the isolation sidewall spacers 500 further cover the top of the bit line BL, and also cover the substrate 100. In this embodiment, the isolation sidewall spacers 500 further fill the bit line contact windows 200 a. It can be understood that, in this embodiment, the bit line contact 200a is further filled with a material of the isolation sidewall spacer while the isolation sidewall spacer 500 is formed.

Specifically, the isolation sidewall 500 may have a single-layer structure or a multi-layer structure. In this embodiment, the isolation sidewall spacer 500 includes a first isolation layer 510, a second isolation layer 520, and a third isolation layer 530. The following explains a method for forming the isolation sidewall 500 in this embodiment by taking the formation of the isolation sidewall with a multi-layer structure as an example.

A first step of conformally forming a first isolation layer 510 on the substrate 100, wherein the first isolation layer 510 conformally covers the sidewall of the bit line BL following the sidewall topography of the bit line BL and further covers the top of the bit line BL, and in this embodiment, the first isolation layer 510 also covers the sidewall of the bit line contact 200 a.

A second step of conformally forming a second spacer 520 on the sidewalls of the bit line BL, where the second spacer 520 partially covers the first spacer 510; the second isolation layer 520 may be formed on the sidewalls of the bit lines BL in a self-aligned manner, for example, by a deposition process and an etch-back process;

a third step of conformally forming a third isolation layer 530 on the substrate, similar to the first isolation layer 510, the third isolation layer 530 conformally covering the sidewalls of the bit lines BL following the sidewall topography of the bit lines BL and further covering the tops of the bit lines BL. In this embodiment, when the third isolation layer 530 is formed, the bit line contact 200a is further filled with a material of the third isolation layer.

Wherein the material of the first isolation layer 510 and the third isolation layer 530 are different from the material of the second isolation layer 520. For example, the first isolation layer 510 and the third isolation layer 530 are made of the same material, and may specifically include silicon oxide (SiO); and, the material of the second isolation layer 520 may specifically include silicon nitride (SiN). Accordingly, when the second isolation layer 520 is formed by using the etch-back process, the exposed first isolation layer 510 is prevented from being damaged.

As described above, in the present embodiment, the bit line contact 200a is further filled with the material of the isolation sidewall spacers while the isolation sidewall spacers 500 are formed. However, it should be noted that in other embodiments, the insulating material may also be filled in the bit line contact window 200a alone. For example, after the first isolation layer 510 is formed, an insulating material is separately filled in the bit line contact 200a, and then, the second isolation layer 520 and the third isolation layer 530, etc. are sequentially formed.

It should be noted that, under the isolation of the isolation sidewall spacers 500, a first isolation line L1 extending along the first direction (Y direction) may be formed by using the isolation sidewall spacers 500 and the bit lines BL, and second source/drain regions S/D2 adjacent to each other in the second direction (X direction) are respectively located at two sides of the first isolation line L1. And, in a subsequent process, the storage node contacts SC adjacent in the X direction may be spaced apart from each other based on the first isolation line L1.

In a further aspect, the method for forming the memory further includes: in step S700, a plurality of second isolation lines L2 extending along the second direction (X direction) is formed, as follows.

Fig. 12a to 12b are schematic top view and cross-sectional view illustrating a method for forming a memory according to a first embodiment of the invention when step S700 is performed.

In step S700, referring to fig. 12a and 12b with emphasis, a plurality of second isolation lines L2 are formed on the substrate 100, the second isolation lines L2 extend along the second direction (X direction) and intersect with the first isolation lines L1 to define a plurality of cells, and each of the second source/drain regions S/D2 corresponds to one cell. Specifically, the cells are used to form storage node contact windows 600a, and each of the second source/drain regions S/D2 corresponds to one storage node contact window 600 a.

Note that, in the storage node contact window 600a, the bottom opening size is larger than the top opening size. Specifically, the storage node contact 600a has a bottom width greater than a top width in the second direction (X direction).

Referring to fig. 12a and 12b in particular, in the present embodiment, the second isolation line L2 is formed directly above the word line WL. Alternatively, the second isolation line L2 may be formed based on a reticle of the word line WL.

Specifically, the method for forming the second isolation line L2 includes the following steps, for example.

Step one, forming a sacrificial layer on the substrate 100, wherein the sacrificial layer fills gaps between adjacent first isolation lines L1; wherein the top surface of the sacrificial layer may be also higher than the top surface of the first isolation line L1 to further cover the first isolation line L1;

step two, performing a photoetching process by using a mask plate with a word line pattern, and further performing an etching process on the sacrificial layer to form a groove in the sacrificial layer, wherein the groove correspondingly extends along a second direction and is correspondingly right above the word line WL;

depositing an isolation material in the groove, wherein the isolation material also covers the top surface of the sacrificial layer;

and fourthly, performing a planarization process to remove the isolation material on the top surface of the sacrificial layer, so that the residual isolation material is only filled in the trench to form a second isolation line L2 extending along the second direction (X direction). The planarization process includes, for example, a chemical mechanical polishing process.

It should be noted that, when the top surface of the sacrificial layer is higher than the top surface of the first isolation line L1, a portion of the second isolation line L2 intersecting the first isolation line L1 also covers the first isolation line L1 accordingly.

Based on this, in an alternative scheme, after the isolation material on the top surface of the sacrificial layer is removed, the planarization process may be further performed, and the first isolation line L1 is used as a polishing stop layer to stop polishing on the top of the first isolation line L1. Thus, the isolation material covering the first isolation line L1 is removed, and the top surface of the second isolation line L2 is not higher than the top surface of the first isolation line L1.

Step five, the sacrificial layer is removed, and at this time, the first isolation line L1 and the second isolation line L2 remaining on the substrate 100 define a plurality of storage node contacts 600 a.

In an alternative embodiment, specifically referring to fig. 12b, after the memory node contact 600a is defined, the method further includes: and etching the substrate 100 by using the first isolation line L1 and the second isolation line L2 as masks to form a groove 600b, wherein the groove 600b exposes the second source/drain region S/D2. Wherein the bottom surface of the recess 600b is higher than the bottom boundary of the second source/drain region S/D2. In this embodiment, the bottom surface of the recess 600b is further higher than the bottom surface of the bit line contact 200 a.

Specifically, the second source/drain region S/D2 at least partially corresponds to the storage node contact 600a, so that when the substrate 100 is etched through the storage node contact 600a to form the recess 600b, the recess 600b is in upper and lower communication with the storage node contact 600a, and the second source/drain region S/D2 in the substrate 100 is exposed. In this embodiment, the recess 600b further exposes the isolation structure 110 adjacent to the second source/drain region S/D2.

It should be noted that, the dimension of the space between the adjacent first isolation lines L1 at the bottom thereof is larger, so that when the groove 600b is formed, it is advantageous to increase the dimension of the opening of the groove 600a in the direction perpendicular to the first direction, so as to increase the surface area of the second source/drain region S/D2 exposed in the groove 600 b.

In this embodiment, the first isolation layer 510 and the third isolation layer 530 in the first isolation line L1 further cover the top of the bit line BL, and the first isolation layer 510 and the third isolation layer 530 further cover the surface of the substrate 100, so that a portion of the first isolation layer 510 and a portion of the third isolation layer 530 correspond to the storage node contact window 600 a. Based on this, when the recess 600b is formed, the first and third isolation layers exposed in the storage node contact window 600a and also the first and third isolation layers on top of the bit line BL are removed accordingly, and the capping layer 240 in the bit line BL is exposed.

Further, the method for forming the memory further comprises the following steps: in step S800, a conductive material is filled in the storage node contact window 600a to form a storage node contact SC.

Fig. 13a to 13b are schematic top view and cross-sectional view illustrating a method for forming a memory according to a first embodiment of the invention when step S800 is performed. Referring to fig. 13a and 13b, in the present embodiment, the conductive material further fills the recess 600b, so that the storage node contact SC is formed to extend into the recess 600b, to be embedded into the substrate 100, and to be electrically connected to the second source/drain region S/D2.

As described above, the bottom of the storage node contact 600a is larger in size, and thus the width of the storage node contact SC at the bottom of the contact can be made larger than the width of the storage node contact SC at the top of the contact. And, in this embodiment, there is also a groove 600b communicated below the storage node contact window 600a, and the groove 600b exposes the second source/drain region S/D2 with a larger area, so that a larger contact area can be provided between the storage node contact SC and the second source/drain region S/D2.

Example two

The difference from the first embodiment is that, in the method for forming the memory of the embodiment, when the first etching process is performed, the first etching process includes sequentially etching the second conductive material layer and the first conductive material layer by using an anisotropic etching process, and a side boundary of the first conductive material layer after the first etching process is flush with a side boundary of the second conductive layer; then, in the second etching process, the etchant only laterally erodes the sidewall of the first conductive material layer to further laterally reduce the size of the first conductive material layer, so that the size of the formed first conductive layer is smaller than that of the second conductive layer.

Fig. 14 is a schematic structural diagram of a memory forming method in the second embodiment of the present invention after a first etching process is performed.

Specifically referring to fig. 14, when the first etching process is performed, the second conductive material layer, the third conductive material layer and the first conductive material layer are sequentially etched by using the mask line 241 as a mask, so as to form the second conductive layer 220 and the third conductive layer 230. And, under the anisotropic etching, making the side boundary of the first conductive material layer 210 'after the first etching process flush with the side boundary of the second conductive layer 220, i.e., the width dimension of the first conductive material layer 210' after the first etching process is the same or nearly the same as the width dimension of the second conductive layer 220.

Fig. 15 is a schematic structural diagram of the memory forming method according to the second embodiment of the invention after the second etching process is performed.

As shown in fig. 14 and fig. 15, in the second etching process, for example, a wet etching process is used to laterally erode the first conductive material layer 210', so that the width of the formed first conductive layer 210 is reduced.

Similar to the embodiment, in the second etching process, the first conductive material layer and the second conductive material layer have a larger etching selection ratio, for example, the etching selection ratio of the first conductive material layer to the second conductive material layer is greater than or equal to 10: 1.

In summary, in the memory provided by the invention, since the width of the first conductive layer in the bit line is smaller than that of the second conductive layer, the bottom space between adjacent bit lines is larger than the top space between adjacent bit lines.

It is considered that, when the width dimension of the second conductive layer is maintained and the width dimension of the first conductive layer is reduced, the increase of the spacing dimension of the bottom portion between the adjacent bit lines can be realized on the basis of satisfying the resistivity of the second conductive layer, and thus, for example, the bottom dimension of the storage node contact filled between the adjacent bit lines can be further increased to improve the connection performance of the storage node contact with the active region. Or, when the width of the second conductive layer is increased to make the width of the second conductive layer larger than the width of the first conductive layer, the resistivity of the second conductive layer is reduced, the transmission performance of the bit line is improved, and a sufficient bottom space between adjacent bit lines can be ensured to ensure that the size of the storage node contact part filled between the adjacent bit lines meets the requirement. Of course, the width of the second conductive layer can be increased and the width of the first conductive layer can be reduced compared to the prior art.

It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. Moreover, the above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

In addition, it should be further noted that the terms "first", "second", third "and the like in the description are used for distinguishing various components, elements, steps and the like in the description, and are not used for indicating a logical relationship or a sequential relationship between the various components, elements, steps and the like unless otherwise specified or indicated.

Claims

1. A memory, comprising:

a plurality of bit lines formed on the substrate, the bit lines extending along a first direction and intersecting with corresponding active regions, the bit lines including a first conductive layer and a second conductive layer stacked successively from bottom to top; or the bit line comprises a first conductive layer, a third conductive layer and a second conductive layer which are stacked successively from bottom to top;

the width dimension of the first conductive layer is smaller than that of the second conductive layer, and the part of the bit line, which intersects with the active region, forms a bit line contact part, and the bottom of the first conductive layer in the bit line contact part extends into the bit line contact window.

2. The memory of claim 1, wherein a dimension of an opening of the bit line contact in a direction perpendicular to the first direction is larger than a width dimension of the first conductive layer in the bit line contact, such that the first conductive layer in the bit line contact is spaced apart from sidewalls of the bit line contact in the direction perpendicular to the first direction;

and an insulating material layer is filled between the first conductive layer of the bit line contact part and the side wall of the bit line contact window.

3. The memory of claim 1, wherein the substrate further has a plurality of isolation structures formed therein, the isolation structures surrounding a periphery of the active region; wherein the bit line contact window also extends laterally from the active region to an isolation structure adjacent to the active region.

4. The memory of claim 1, wherein the memory further comprises:

the isolation side wall covers the side wall of the bit line in a shape-preserving mode, the isolation side wall comprises at least two isolation layers, and the materials of the at least two isolation layers comprise silicon nitride and silicon oxide.

5. The memory of claim 1, wherein the memory further comprises:

and the first isolation layer conformally covers the side wall of the bit line, wherein the outer side wall boundary of the first isolation layer covering the first conducting layer does not exceed the outer side wall boundary of the second conducting layer.

6. The memory of claim 1, wherein the memory further comprises:

and the second isolation layer covers the side wall of the bit line, wherein the outer side wall boundary of the second isolation layer covering the first conducting layer exceeds the outer side wall boundary of the second conducting layer.

7. The memory according to claim 1, wherein a width dimension of the third conductive layer is larger than a width dimension of the first conductive layer and equal to or smaller than a width dimension of the second conductive layer; or the width dimension of the third conductive layer is smaller than that of the second conductive layer and is larger than or equal to that of the first conductive layer.

8. The memory of claim 1, wherein the bit line has the bit line contacts and bit line connections connecting adjacent bit line contacts, the bit line connections being formed on a top surface of the substrate between adjacent bit line contacts.

9. The memory of claim 8, wherein a top portion of the first conductive layer in the bit line contact extends out of the bit line contact window and is connected to the first conductive layer in the bit line connection.

10. A method for forming a memory, comprising:

11. The method of forming a memory of claim 10, further comprising, after forming the first layer of conductive material and before forming the second layer of conductive material:

a third conductive material layer is formed on the first conductive material layer.

12. The method of claim 11, wherein the first etching process further comprises etching the third conductive material layer to form a third conductive layer, wherein a width dimension of the third conductive layer is greater than a width dimension of the first conductive layer and less than or equal to a width dimension of the second conductive layer.

13. The method of forming a memory of claim 11, wherein the second etching process further comprises etching the third conductive material layer to form a third conductive layer;

during the second etching process, the etchant also laterally erodes a third conductive material layer located right below the second conductive layer, so that the width of the formed third conductive layer is smaller than that of the second conductive layer and is greater than or equal to that of the first conductive layer.

14. The method of claim 10, wherein the first etching process comprises anisotropically etching the second conductive material layer and etching to stop at the first conductive material layer;

and the second etching process comprises isotropically etching the first conductive material layer.

15. The method of claim 10, wherein the first etching process comprises anisotropically etching the second conductive material layer and the first conductive material layer such that a side boundary of the first conductive material layer after the first etching process is flush with a side boundary of the second conductive layer;

and the second etching process comprises laterally eroding the first conductive material layer below the second conductive layer.

16. The method of claim 10, wherein forming the first conductive material layer comprises performing a planarization process such that the planarized first conductive material layer covers the surface of the substrate and fills the bit line contact windows.

17. The method of forming a memory of claim 10, further comprising, after forming the bit line:

and sequentially forming at least two layers of isolation layers to form an isolation side wall, wherein the isolation side wall conformally covers the side wall of the bit line.

18. A memory, comprising:

the bit lines are formed on the substrate, extend along a first direction and intersect with corresponding active regions, the bit lines comprise a first conductive layer and a second conductive layer which are stacked from bottom to top, the width dimension of the first conductive layer is smaller than that of the second conductive layer, a part of the bit lines, which intersects with the active regions, forms a bit line contact part, and the bottom of the first conductive layer in the bit line contact part extends into the bit line contact window;

and the isolation side wall conformally covers the side wall of the bit line, the isolation side wall comprises at least one isolation layer, and the isolation layer integrally and continuously covers the side walls of the first conducting layer and the second conducting layer.