CN111640753B - Memory and forming method thereof - Google Patents

Abstract

The invention provides a memory and a forming method thereof. The first contact part at the edge position in the plurality of node contact parts is provided with an insulating contact column, so that the first contact part and the corresponding active region (namely, the active region at the edge position) are electrically insulated, and the formed memory cell at the edge position forms a non-functional memory cell. In this way, the adverse effect of the non-functional memory cells at the edge position on the device performance of the memory due to the abnormal performance of the non-functional memory cells is avoided.

Description

Memory and forming method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a memory and a forming method thereof.

Background

A Memory, such as a Dynamic Random Access Memory (DRAM), generally has a Memory cell array including a plurality of Memory cells arranged in an array. And the memory further comprises a plurality of bit lines, each bit line is electrically connected with a corresponding memory cell, the memory further comprises a storage capacitor, the storage capacitor is used for storing charges representing stored information, and the memory cells can be electrically connected with the storage capacitor through a node contact part, so that the storage function of each memory cell is realized.

At present, based on the existing semiconductor manufacturing process, the memory cells located at the edge position are prone to have insufficient performance when the memory cell array is manufactured, so that the device performance of the whole memory is easily affected.

Disclosure of Invention

The invention aims to provide a memory to solve the problem that the performance of the memory is affected because the performance of the memory at the edge position of the existing memory is easy to be insufficient.

To solve the above technical problem, the present invention provides a memory, including:

the semiconductor device comprises a substrate, a plurality of first transistors and a plurality of second transistors, wherein a memory area and a peripheral area are defined on the substrate, the peripheral area is located on the outer side of the memory area, and a plurality of active areas are formed in the memory area of the substrate;

a bit line group formed in the memory region of the substrate, the bit line group including a plurality of bit lines extending in a predetermined direction, the bit lines intersecting corresponding ones of the plurality of active regions, and bit lines arranged at edge positions in the bit line group constituting first bit lines, and bit lines on a side of the first bit lines away from a peripheral region in the bit line group constituting second bit lines; and the number of the first and second groups,

a plurality of node contacts, each of which is at least partially located on one side of the bit line and is formed on the corresponding active region, and of which the node contacts arranged at edge positions constitute first contacts and the node contacts located on one side of the first contacts away from the peripheral region constitute second contacts; the first contact part comprises an insulating contact column which is formed on the substrate and is electrically insulated from the contacted active area, and the second contact part comprises a conductive contact layer which is formed on the substrate and is electrically connected with the contacted active area.

Optionally, the memory further comprises an isolation layer covering a top surface of the bit line, and a portion of the isolation layer covering the first bit line constitutes a first isolation portion; and the insulated contact column of the first contact portion is positioned at one side of the first bit line, and the first contact portion further comprises a first electrically conductive layer which covers the top surface of the insulated contact column and extends transversely to the first isolation portion, so that the maximum width dimension of the first contact portion is larger than that of the second contact portion.

Optionally, the insulated contact pillar of the first contact portion is located on a side of the first bit line close to the second bit line, so that the insulated contact pillar is located between the first bit line and an adjacent second bit line, and the first electrically conductive layer of the first contact portion further extends to the first isolation portion in a direction away from the second bit line.

Optionally, a top surface of the conductive contact layer of the second contact is lower than a top surface of the bit line; and the second contact part also comprises a second electric conduction layer which is formed on the electric conduction contact layer and extends upwards along the height direction so as to enable the top surface of the second electric conduction layer to be flush with the top surface of the first electric conduction layer.

Optionally, the maximum width dimension of the first contact portion is greater than 1 time and less than or equal to 2 times the maximum width dimension of the second contact portion.

Optionally, a portion of the isolation layer covering the second bit line constitutes a second isolation portion, and a top surface of the second contact portion is higher than a top surface of the second isolation portion; and the memory further comprises an interval insulating layer, wherein the interval insulating layer is formed on the isolation layer, the part of the interval insulating layer formed on the first isolation part forms an interval side wall, the part of the interval insulating layer formed on the second isolation part forms an interval filling part, and the interval filling part is formed between the adjacent node contact parts.

Optionally, a first portion of the first isolation portion covered by the first electrically conductive layer is higher than a second portion of the first isolation portion uncovered by the first electrically conductive layer, so that a sidewall of the first portion and a top surface of the second portion are connected to present a step-like structure, and the spacer sidewall is formed on the top surface of the second portion and covers the sidewall of the first portion.

Optionally, a width dimension of the first bit line is greater than a width dimension of the second bit line.

Optionally, the width of the first bit line is greater than 1 time and less than or equal to 2 times the width of the second bit line.

In addition, the invention also provides a forming method of the memory, which comprises the following steps:

providing a substrate, wherein a memory area and a peripheral area are defined on the substrate, the peripheral area is positioned outside the memory area, and a plurality of active areas are formed in the memory area of the substrate;

forming a bit line group in the memory region of the substrate, wherein the bit line group comprises a plurality of bit lines extending along a predetermined direction, the bit lines intersect with corresponding active regions in the plurality of active regions, and a plurality of node contact windows are defined by the bit lines, the node contact windows arranged at edge positions in the plurality of node contact windows form first contact windows, and the node contact windows positioned at one side of the first contact windows far away from the peripheral region form second contact windows; and the number of the first and second groups,

the first contact window is filled with an insulating contact column which is electrically insulated from an active region below the insulating contact column, and the second contact window is filled with a conductive contact layer which is electrically connected with an active region below the conductive contact layer.

Optionally, the forming method further includes:

forming a layer of electrically conductive material overlying the insulated contact stud and the conductive contact layer; and the number of the first and second groups,

and patterning the electric conduction material layer to form an electric conduction layer, wherein the electric conduction layer corresponding to the second contact window forms a second electric conduction layer, the second electric conduction layer is formed above the conductive contact layer, the electric conduction layer corresponding to the first contact window forms a first electric conduction layer, the first electric conduction layer covers the insulated contact column and transversely extends to be positioned right above the first bit line, so that the width dimension of the first electric conduction layer is larger than that of the second electric conduction layer.

Optionally, the method for patterning the electrically conductive material layer to form an electrically conductive layer includes:

forming a patterned mask layer on the electrically conductive material layer, the patterned mask layer including a first pattern and a second pattern, the first pattern covering the first contact and extending laterally to the first bit line for defining a pattern of the first electrically conductive layer, and the second pattern covering the second contact for defining a pattern of the second electrically conductive layer; and the number of the first and second groups,

and etching the electric conduction material layer by taking the patterned mask layer as a mask to form the first electric conduction layer and the second electric conduction layer, wherein the width dimension of the first electric conduction layer is larger than that of the second electric conduction layer.

In the memory provided by the invention, the first contact part at the edge position in the node contact part array is provided with the insulated contact column, so that the first contact part and the corresponding active region (namely, the active region at the edge position) are electrically insulated, and the formed memory cell at the edge position forms a non-functional memory cell. In this way, the adverse effect of the non-functional memory cells at the edge position on the device performance of the memory due to the abnormal performance of the non-functional memory cells is avoided.

Drawings

Fig. 1 is a layout structure of a bit line group of a memory according to a first embodiment of the present invention;

FIG. 2a is a cross-sectional view of a memory device with a bit line set according to one embodiment of the present invention;

FIG. 2b is a cross-sectional view of a memory device with a node contact according to a first embodiment of the present invention;

FIG. 2c is a cross-sectional view of a memory device with a spacer insulating layer according to a first embodiment of the present invention;

FIG. 3 is a flow chart illustrating a method for forming a memory according to a first embodiment of the invention;

FIGS. 4a to 4e are schematic structural diagrams of a memory in a first embodiment of the invention during a manufacturing process thereof;

fig. 5 is a schematic cross-sectional view of a memory according to a second embodiment of the invention.

Wherein the reference numbers are as follows:

100-a substrate;

100A-memory region;

100B-peripheral zone;

110-a first trench isolation structure;

120-a second trench isolation structure;

a 200-bit line group;

200 a-a first bit line conductive layer;

200 b-a second bit line conductive layer;

200 c-a third bitline conductive layer;

200 d-bit line shield layer;

200 e-isolation side wall;

210-a first bit line;

220-second bit line;

310-a first partition;

320-a second partition;

400 a-a first layer of conductive material;

400 b-a second layer of conductive material;

410-a first contact;

410 a-insulated contact posts;

410 b-a first electrically conductive layer;

420-a second contact;

420 a-a conductive contact layer;

420 b-a second electrically conductive layer;

430-third contact;

430 a-insulating column;

430 b-a third electrically conductive layer;

440-a fourth contact;

510-a first contact;

520-a second contact window;

600-an insulating dielectric layer;

710-a first graphic;

720-a second graphic;

800-parting line;

AA 1-first active region;

AA 2-second active region.

Detailed Description

The memory and the forming method thereof according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Fig. 1 is a layout structure of a memory according to a first embodiment of the present invention, illustrating a bit line group, fig. 2a is a schematic cross-sectional view of a memory according to a first embodiment of the present invention, in which a bit line group is formed, and fig. 2b is a schematic cross-sectional view of a memory according to a first embodiment of the present invention, in which a node contact is formed.

As shown in fig. 1 and fig. 2a to 2b, the memory includes: a substrate 100, a set of bit lines 200 formed on the substrate 100, and a plurality of node contacts.

Specifically, a plurality of active regions are formed in the substrate 100, and the active regions are arranged in an array, for example, to form an active region array, wherein adjacent active regions may be separated from each other, for example, by using a first trench isolation structure 110, and memory cells are formed on the active regions based on the active regions. Wherein the active regions arranged at edge positions in the active region array constitute a first active region AA1, and the active regions in the active region array surrounded by the first active region AA1 constitute a second active region AA 2.

It should be noted that, due to the limitation of the conventional semiconductor manufacturing process, the quality of the active regions (e.g., the first active region AA1) arranged at the edge positions in the formed active region array is low, and if a memory cell is further manufactured on the active region with low quality, the device performance of the memory cell formed based on the active region at the edge positions is affected, so that the memory cell with performance defect needs to be discarded, and at this time, the cost is inevitably wasted.

Based on this, in the present embodiment, at least the active region located at the edge position may be defined as a non-functional active region which is not used to form the memory cell, that is, the non-functional active region includes the first active region AA 1. And a second active region AA2 surrounded by the first active region AA1 is at least partially defined as a functional active region for forming a memory cell.

With continued reference to fig. 2a, in the present embodiment, a memory region 100A and a peripheral region 100B located outside the memory region 100A are defined on the substrate 100, and the active area array is formed in the memory region 100A. A second trench isolation structure 120 is formed in a region where the peripheral region 100B meets the memory region 100A, so as to isolate the semiconductor devices in the memory region 100A from the semiconductor devices in the peripheral region 100B. It should be appreciated that the first active region AA1 arranged at an edge position in the array of active regions is correspondingly close to the peripheral region 100B, and the active regions in the array of active regions on the side of the first active region AA remote from the peripheral region 100B constitute the second active region AA 2.

With continued reference to fig. 1 and 2a, the set of bit lines 200 is formed on the substrate 100, the set of bit lines 200 including a plurality of bit lines extending along a predetermined direction. And bit lines arranged at edge positions in the bit line group 200 constitute first bit lines 210, and bit lines arranged at a side of the first bit lines 210 away from the peripheral region 100B in the bit line group 200 constitute second bit lines 220. In this embodiment, the first bit line 210 intersects with a first active region AA1 in the active region array, and the second bit line 220 intersects with a second active region AA2 in the active region array.

Further, the width dimension of the first bit line 210 is greater than the width dimension of the second bit line 220. It should be noted that the circuit arrangement density of the bit lines (including the first bit lines 210) in the edge region is less dense than that of the bit lines in the middle region, so that the first bit lines 210 in the edge region are more vulnerable to a larger etching attack than the second bit lines 220 arranged inside when the patterning process is performed to form the bit line group 200. Based on this, in the present embodiment, the width of the first bit line 210 is greater than the width of the second bit line 220, so that even if the first bit line 210 is attacked by the etching during the preparation of the bit line group 200, the topography of the first bit line 210 can still be ensured. Moreover, under the blocking protection of the first bit line 210 with a larger width dimension, the problem of excessive erosion of the second bit line 220 adjacent to the first bit line 210 can be effectively alleviated.

In this embodiment, the first bit line 210 intersects the first active region AA1, and as mentioned above, the first active region AA1 is a non-functional active region, and the first bit line 210 is also used to constitute a non-functional bit line, for example. Based on this, the adjustment of the width dimension of the first bit line 210 is more flexible. For example, the width dimension D1 of the first bit line 210 may be greater than 1 time the width dimension D2 of the second bit line 220 and less than or equal to 2 times the width dimension D2 of the second bit line 220 (i.e., D2 < D1 ≦ 2 × D2).

With continued reference to fig. 2a, each bit line in the set of bit lines 200 includes a first bit line conductive layer 200a, a second bit line conductive layer 200b, and a third bit line conductive layer 200c stacked in sequence. The material of the first bit line conductive layer 200a includes, for example, doped polysilicon, the material of the second bit line conductive layer 200b includes, for example, titanium nitride, and the material of the third bit line conductive layer 200c includes, for example, tungsten.

Further, each bit line in the bit line group 200 may further include a bit line shielding layer 200d and an isolation sidewall spacer 200 e. The bit line shielding layer 200d is formed above the bit line conductive layers stacked in sequence, and the isolation side walls 200e at least cover the side walls of the bit line conductive layers stacked in sequence and the side walls of the bit line shielding layer 200 d.

With continued reference to FIG. 2a, the adjacent bitlines may further define node contacts for receiving node contacts. Wherein the bottom of at least a portion of the node contact may further extend into the substrate 100. In a specific embodiment, a plurality of separation lines (not shown in the figure) are further formed on the substrate 100, and the extension directions of the separation lines and the extension directions of the bit lines are, for example, perpendicular to each other, so that the separation lines and the bit lines intersect to surround the node contact windows.

As described above, the adjacent bit lines may further define node contact windows, and a plurality of node contact windows may be defined based on the plurality of bit lines in the bit line set 200, and the node contact windows may be arranged in an array, for example, to form a node contact window array. The node contacts arranged at edge positions in the node contact array form first contacts 510, that is, the first contacts 510 are closer to the peripheral region 100B; and the node contact in the node contact array located on the side of the first contact 510 away from the peripheral region 100B constitutes a second contact 520 (it can be considered that the node contact in the node contact array surrounded by the first contact 510 constitutes the second contact 520). In the present embodiment, the first contact 510 is defined by a first bit line 210 and an adjacent second bit line 220, and the second contact 520 is defined by an adjacent second bit line 220. At this time, the first contact 510 is correspondingly located on a side of the first bit line 210 close to the second bit line 220.

In this embodiment, in the node contact array, the bottom of the second contact 520 further extends into the substrate 100, so that the bottom of the second contact 420 filled in the second contact 520 is embedded into the substrate 100. And, the bottom of the first contact 510 stops at the top surface of the substrate 100 and thus does not extend into the substrate 100, so that the bottom surface of the first contact 410 filled in the first contact 510 stops at the top surface of the substrate 100 and is not embedded into the substrate 100.

Referring next to fig. 2b, the memory further includes an isolation layer covering the top surface of the bit line, and in this embodiment, the isolation layer covers the bit line shielding layer 200d of the bit line accordingly. As described above, the adjacent bit lines are used to define the node contact, and it is considered that the height of the node contact can be further increased by the isolation layer above the bit lines. Specifically, the isolation layer includes a first isolation portion 310 and a second isolation portion 320, wherein the first isolation portion 310 covers the first bit line 210, and the second isolation portion 320 covers the second bit line 220.

With continued reference to fig. 2b, the node contacts of the node contacts fill the node contact windows, and in this embodiment, the node contacts may be correspondingly arranged in an array to form a node contact array. And at least a portion of the node contact is located laterally to the bit line. In the node contact array, the node contacts filled in the first contact windows 510 constitute first contacts 410, and the node contacts filled in the second contact windows 520 constitute second contacts 420.

It is also understood that, in correspondence with the node contact array, the node contacts arranged at edge positions in the node contact array constitute first contacts 410, and the node contacts located on the side of the first contacts 410 away from the peripheral region 100B in the node contact array constitute second contacts 420. In this embodiment, the first contact portion 410 is partially located on a side of the first bit line 210 close to the second bit line 220, such that the first contact portion 410 is partially located between the first bit line 210 and the adjacent second bit line 220, and the second contact portion 420 is located between the adjacent second bit lines 220.

Further, the top position of each node contact part is further higher than the top position of the node contact window. Wherein the top of the first contact portion 410 further extends laterally onto the first isolation portion 310, such that the maximum width dimension of the first contact portion 410 is greater than the maximum width dimension of the second contact portion 420. In this embodiment, the top of the first contact portion 410 extends to the first isolation portion 310 away from the second bit line 220, so as to at least partially cover the first isolation portion 310.

With reference to fig. 2b, in the present embodiment, the thickness of the portion of the first isolation portion 310 covering the lower portion of the first contact portion 410 is greater than the thickness of the second isolation portion 320. That is, the first isolation part 310 has a portion having a thickness greater than that of the second isolation part 320, and the portion having the greater thickness of the first isolation part 310 is interposed in a space surrounded by the first bit line 210 and the first contact part 410. In this embodiment, a portion of the first isolation portion 310 covered under the first contact portion 410 is defined as a first portion, and a portion of the first isolation portion 310 uncovered by the first contact portion 410 is defined as a second portion.

Further, the thickness of the second portion of the first isolation portion 310 not covered by the first contact portion 410 may be the same as or similar to the thickness of the second isolation portion 320. That is, in the present embodiment, a thickness of a first portion of the first isolation portion 310, which is close to the first contact portion 410 and covered by the first contact portion 410, is larger, and a thickness of a second portion of the first isolation portion 310, which is far from the first contact portion 410 and not covered by the first contact portion 410, is smaller, so that the first isolation portion 310 has a step-like structure.

In this embodiment, the first contact 410 may also be defined as a non-functional contact, and there may be no electrical transmission between the first contact 410 and the active region below the first contact. Specifically, at least a portion of the first contact 410 may be formed on the first active region AA1, and there is no electrical transmission between the at least a portion of the first contact 410 and the first active region AA 1. And, the second contact 420 may be defined as a functional contact, and the second contact 420 is formed on the second active region AA2 such that the bottom of the second contact 420 is in contact with the second active region AA2 and there is electrical transmission with the second active region AA 2.

Specifically, the first contact portion 410 includes an insulating contact pillar 410a, and the insulating contact pillar 410a fills the first contact window 510 and is electrically insulated from the active regions contacting each other. And, the insulated contact column 410a of the first contact portion 410 is located at a side of the first bit line 210 close to the second bit line 220, such that the insulated contact column 410a is located between the first bit line 210 and the next adjacent second bit line 220. Wherein the insulated contact column 410a and the first isolation portion 310 are disposed in close proximity, and a top surface of the insulated contact column 410a and a top surface of the first isolation portion 310 are flush.

In this embodiment, the first contact portion 410 further includes a first electrically conductive layer 410b, and the first electrically conductive layer 410b covers the top surface of the insulated contact pillar 410a and laterally extends onto the first isolation portion 310, so that the first electrically conductive layer 410b has a larger width dimension. In this embodiment, the first electrically conductive layer 410b of the first contact portion 410 extends to the first isolation portion 310 away from the second bit line 220.

With continued reference to fig. 2b, the second contact portion 420 includes a conductive contact layer 420a, and the conductive contact layer 420a fills the second contact window 520 to electrically connect with the second active region AA 2. The top position of the conductive contact layer 420a is lower than the top position of the bit line, that is, the top position of the conductive contact layer 420a is lower than the top position of the second contact window 520, and at this time, the top position of the conductive contact layer 420a in the second contact portion 420 is correspondingly lower than the top position of the insulating contact pillar 410a in the first contact portion 410.

Further, the second contact portion 420 further includes a second electrically conductive layer 420b, and the second electrically conductive layer 420b fills the second contact hole and is formed on the conductive contact portion 420a to be electrically connected to the conductive contact portion 420 a. And, the top position of the second electrically conductive layer 420b is higher than the top position of the second contact window 520, i.e. the top surface of the second electrically conductive layer 420b is higher than the top surface of the second isolation portion 320.

As described above, the first electrically conductive layer 410b also extends laterally to the first isolation portion 310, so that the first electrically conductive layer 410b has a larger width dimension, and accordingly the width dimension of the first electrically conductive layer 410b in the first contact portion 410 is larger than the width dimension of the second electrically conductive layer 420b in the second contact portion 420.

In this embodiment, the top surface of the conductive contact pillar 420a of the second contact portion 420 is lower than the top surface of the second isolation portion 320, and the top surface of the insulating contact pillar 410a of the first contact portion 410 is higher than the top surface of the second isolation portion 320; and a second electrically conductive layer 420b in the second contact portion 420 is formed on the electrically conductive contact layer 420a and extends upward in a height direction such that a top surface of the second electrically conductive layer 420b in the second contact portion 420 is flush with a top surface of the first electrically conductive layer 410b in the first contact portion 410. Optionally, the first electrically conductive layer 410b and the second electrically conductive layer 420b are made of the same material, for example, both include a first conductive material layer and a second conductive material layer.

With continued reference to fig. 2b, in the first electrically conductive layer 410b, a first conductive material layer and a second conductive material layer are sequentially stacked on top of each other on the insulating contact pillar 410a and the first isolation portion 310. In the second electrically conductive layer 420b, the first electrically conductive material layer is formed between the electrically conductive contact layer 420a and the second electrically conductive material layer, and the first electrically conductive material layer surrounds a bottom surface and at least a portion of the sidewalls of the second electrically conductive material layer.

The first electrically conductive layer 410b in the first contact portion 410 and the second electrically conductive layer 420b in the second contact portion 420 can be formed on the basis of the same electrically conductive material layer by using a patterning process. The formation method of the first electrically conductive layer 410b and the second electrically conductive layer 420b will be described in detail below.

It should be noted that, when the first electrically conductive layer 410b and the second electrically conductive layer 420b are formed based on a patterning process, the first electrically conductive layer 410b located at the edge is subjected to a larger etching attack, so that the first electrically conductive layer 410b is easily corroded to a large extent and deformed. Accordingly, in the present embodiment, the width of the first electrically conductive layer 410b is greater than the width of the second electrically conductive layer 420b, so that even if the first electrically conductive layer 410b is subjected to a large etching attack, the morphology of the first electrically conductive layer 410b can be still ensured. Moreover, under the blocking protection of the first electrically conductive layer 410b with a larger width, the problem of excessive erosion of the second electrically conductive layer 420b adjacent to the first electrically conductive layer 410b can be effectively alleviated.

With reference to fig. 2b, in the present embodiment, the first contact 410 at the edge is at least disposed on a side of the first bit line 210 close to the second bit line 220, and an insulating dielectric layer 600 is further formed on a side of the first bit line 210 away from the second bit line 220. In this embodiment, the isolation layer further extends to cover the insulating dielectric layer 600, and it can be considered that a portion of the isolation layer extending to cover the insulating dielectric layer 600 constitutes a third isolation portion.

As described above, the top of the second contact portion 420 extends upward and is higher than the top surface of the second isolation portion 320, and the first contact portion 410 is also higher than the second isolation portion 320 and also covers the first portion of the first isolation portion 310, and the sidewall of the first portion of the first isolation portion 310 and the top surface of the second portion of the first isolation portion 310 are connected to present a stepped structure.

Based on this, referring to fig. 2c in particular, in the present embodiment, the memory further includes a spacer insulating layer formed on the isolation layer. Wherein the material of the spacing insulating layer comprises silicon nitride, for example. Further, a portion of the spacer insulating layer formed on the first isolation portion 310 forms a spacer sidewall 910, and a portion of the spacer insulating layer formed on the second isolation portion 320 forms a spacer filling portion 920.

Specifically, the space filling portion 920 is filled between the adjacent second contact portions 420, and is also filled between the first contact portion 410 and the second contact portion 420. And, the spacer sidewall 910 is formed on the top surface of the second portion of the first isolation portion 310 and covers the sidewall of the first portion of the first isolation portion 310.

In an alternative, the spacer insulating layer does not cover the third isolation portion of the isolation layer, i.e. the third isolation portion is exposed from the spacer insulating layer, and the top surface of the third isolation portion is further lower than the top surface of the second portion of the first isolation portion, and at this time, the top surface of the third isolation portion is correspondingly lower than the top surface of the second isolation portion.

Referring specifically to fig. 2c, in the present embodiment, the top surface of the insulated contact pillar 410a and the top surface of the first portion of the first isolation portion 310 are flush, for example, the top position of the insulated contact pillar 410a and the top position of the first portion of the first isolation portion 310 are both located at the first height position H1; the top surface of the second portion of the first isolation portion 310 may be flush with the top surface of the second isolation portion 320, for example, the top position of the second portion of the first isolation portion 310 and the top position of the second isolation portion 320 are both located at the second height position H2; and, the top surface of the third isolation portion is more sunken relative to the top surfaces of the second isolation portion 320 and the second portion of the first isolation portion 320, for example, the top position of the third isolation portion is located at a third height position H3. Wherein the first height position H1 is higher than the second height position H2, the second height position H2 is higher than the third height position H3.

The method for forming the memory device according to the present embodiment will be described in detail with reference to fig. 3 and 4a to 4 e. Fig. 3 is a schematic flow chart of a method for forming a memory according to a first embodiment of the invention, and fig. 4a to 4e are schematic structural diagrams of the memory according to the first embodiment of the invention during a manufacturing process thereof.

In step S100, referring to fig. 4a specifically, a substrate 100 is provided, a memory region 100A and a peripheral region 100B are defined on the substrate 100, and the peripheral region 100B is located outside the memory region 100A.

Specifically, an active area array is formed in the memory area 100A of the substrate 100. As described above, the active region array includes a plurality of active regions arranged in an array, wherein adjacent active regions may be separated from each other by the first trench isolation structure 110, for example. Wherein the active regions arranged at the edge positions in the active region array constitute a first active region AA1, and the active regions in the active region array located on the side of the first active region AA1 away from the peripheral region constitute a second active region AA 2.

In this embodiment, the active region at the edge position may be defined as a non-functional active region which is not used to form the memory cell, i.e., the non-functional active region includes the first active region AA 1. And a second active region AA2 surrounded by the first active region AA1 is at least partially defined as a functional active region for forming a memory cell.

Further, a second trench isolation structure 120 may be formed in the substrate at the periphery of the active area array, so as to isolate the active area array in the memory area 100A from the devices in the peripheral area 100B.

In step S200, with continued reference to fig. 4a, a bit line group is formed in the memory area 100A of the substrate 100, the bit line group includes a plurality of bit lines extending along a predetermined direction, and bit lines arranged at edge positions in the bit line group form first bit lines 210, bit lines in the bit line group on a side of the first bit lines 210 away from the peripheral area 100B form second bit lines 220, and a width dimension of the first bit lines 210 is greater than a width dimension of the second bit lines 220.

The bit lines in the bit line group can be used to define a node contact window array, the node contact windows arranged at the edge positions in the node contact window array form first contact windows, and the node contact windows surrounded by the first contact windows in the node contact window array form second contact windows. In this embodiment, an isolation material layer is further prepared in a subsequent process to define the node contact window array together with the bit line, so as to increase the height of the node contact window. This will be explained in detail in the subsequent steps.

Specifically, the method for forming the bit line group includes, for example: first, a bit line material layer is formed on the substrate 100; then, the bit line material layer is patterned to form the bit line group.

When the patterning process is performed to form the bit line group, since the first bit line 210 with a larger width dimension can be formed at the edge position, even if the first bit line 210 at the edge position is attacked by a larger etching, the profile of the formed first bit line 210 can be ensured; moreover, under the blocking protection of the first bit line 210 with a larger width, the second bit line 220 surrounded by the first bit line 210 can be effectively protected from a larger etching attack, and the appearance of the formed second bit line 220 is ensured. In this way, when the functional bit lines are formed by using the second bit lines 220, the device performance of the corresponding memory cells can be correspondingly guaranteed.

With continued reference to fig. 4b, in the present embodiment, the bit line material layer includes three conductive material layers sequentially stacked. Based on this, the formed bit line may include the first bit line conductive layer 200a, the second bit line conductive layer 200b, and the third bit line conductive layer 200 c.

Further, the bit line further includes a bit line shielding layer 200d, and the bit line shielding layer 200d may be a patterned film layer and is formed above the three conductive material layers. Alternatively, for example, the patterned bit line shielding layer 200d is used to sequentially perform a patterning process on the underlying conductive material layer.

In this embodiment, the method for forming each bit line in the bit line group further includes: isolation side walls 200e are formed on the sidewalls of the first bit line conductive layer 200a, the second bit line conductive layer 200b, the third bit line conductive layer 200c, and the bit line shielding layer 200 d.

In step S300, referring specifically to fig. 4b, an isolation material layer 300 is formed on the bit lines, the isolation material layer 300 and the bit lines therebelow form a plurality of isolation lines 800, and the isolation lines 800 define a node contact array. As described above, the node contact arranged at the edge in the node contact array forms the first contact 510, and the node contact located at the side of the first contact 510 away from the peripheral region 100B in the node contact array forms the second contact 520.

In a specific embodiment, the isolation material layer 300 and the bit lines thereunder constitute first isolation lines which follow the extending direction of the bit lines, for example, extend along a first direction. And a second partition line is further formed on the substrate 100, for example, extending along a second direction to intersect the first partition line, thereby defining the node contact array.

Further, after defining the node contact window array, further etching the bottom of the node contact window to extend at least part of the bottom of the node contact window further into the active region of the substrate. In this embodiment, the bottom of the second node contact 520 extends into the substrate 100, and the bottom of the first node contact 510 stops at the top surface of the substrate 100.

In step S400, referring specifically to fig. 4 c-4 d, an electrically conductive material layer (in the present embodiment, the electrically conductive material layer includes a first conductive material layer 400a and a second conductive material layer 400b) is formed, which fills at least a portion of the node contact window and also covers the top surface of the isolation material layer 300. Wherein the electrically conductive material layer is used to further form an electrically conductive layer in the node contact.

Optionally, before forming the electrically conductive material layer, the method further includes: and forming a contact layer in the node contact window. That is, in the present embodiment, in forming the electrically conductive material layer, the electrically conductive material layer is formed on the contact layer, and the contact layer and the electrically conductive material layer are used to constitute the node contact portion.

Referring specifically to fig. 4c, the method of forming the contact layer includes: the conductive contact layer 420a is filled in at least a portion of the node contact window. In this embodiment, the conductive contact layer 420a is filled in the second contact window 520 to be electrically connected to the second active region AA2 exposed in the second contact window 520. And, the method of forming the contact layer further comprises: the insulating contact pillar 410a is filled in the first contact window 510, and the insulating contact pillar 410a is electrically insulated from the active region therebelow. In the present embodiment, at least a portion of the first contact opening 510 exposes the first active region AA1, and based on this, at least a portion of the insulating contact pillar 410a contacts and is electrically insulated from the first active region AA 1.

It should be noted that the conductive contact layer 420a can be formed in the second contact window 520 first, and then the insulating contact pillar 410a can be formed in the first contact window 510. Alternatively, the insulating contact pillar 410a may be preferentially formed in the first contact hole 510, and then the conductive contact layer 420a may be formed in the second contact hole 520.

Further, the top position of the insulated contact pillar 410a in the first contact window may be the same as the top position of the first contact window, i.e., the top surface of the insulated contact pillar 410a is flush with the top surface of the isolation material layer 300. And the top position of the conductive contact layer 420a in the second contact window is lower than the top position of the second contact window 520. In this embodiment, the top surface of the conductive contact layer 420a is further lower than the top surface of the bit line.

With continued reference to fig. 4c and 4d, after the contact layer is formed, a layer of electrically conductive material is formed. In this embodiment, the method for forming the electrically conductive material layer may specifically include the following steps.

In a first step, specifically referring to fig. 4c, a first conductive material layer 400a is formed, the first conductive material layer 400a covers the sidewalls of the second contact window 520 and the top surface of the conductive contact layer 420a, and the first conductive material layer 400a also covers the top surface of the insulating contact pillar 410a and the top surface of the isolation material layer 300.

A second step, shown with particular reference to fig. 4d, forms a second conductive material layer 400b, said second conductive material layer 400b filling said second contact windows and also covering the top surfaces of said isolation material layer 300 and said insulated contact pillars 410 a. In this embodiment, the second conductive material layer 400b is a planarization film layer.

In step S500, referring to fig. 4d and 4e in particular, the electrically conductive material layer is patterned to form a node contact array, which includes a second contact 420 corresponding to the second contact window and a first contact 410 corresponding to the first contact window, and the top of the first contact 410 further extends laterally to the isolation material layer directly above the first bit line 210, so that the width dimension of the first contact 410 is greater than the width dimension of the second contact 420.

In this embodiment, the electrically conductive layer of the node contact is further formed by patterning the electrically conductive material layer. Specifically, the electrically conductive material layer is patterned to form a first electrically conductive layer 410b of the first contact portion 410 and a second electrically conductive layer 420b of the second contact portion 420. The top of the first electrically conductive layer 410b in the first contact portion 410 extends laterally to a position right above the first bit line 210, so that the width of the first electrically conductive layer 410b is greater than the width of the second electrically conductive layer 420 b.

The method for patterning the electrically conductive material layer specifically includes the following steps.

Step one, specifically referring to fig. 4d, a patterned mask layer is formed on the electrically conductive material layer, in this embodiment, the patterned mask layer is formed on the second electrically conductive material layer 400 b. Wherein, the patterned mask layer is, for example, a patterned photoresist layer.

Specifically, the patterned mask layer includes a first pattern 710 and a second pattern 720, the first pattern 710 covers the first contact window and laterally extends to the top of the first bit line 210 for defining a pattern of a first electrically conductive layer in the first contact portion; and the second pattern 720 covers the second contact hole to define a pattern of a second electrically conductive layer in the second contact portion. The width dimension of the first pattern 710 is greater than the width dimension of the second pattern 720.

It should be noted that, when forming the patterned mask layer, the first pattern 710 at the edge position also has the problem of being over-developed, thereby affecting the pattern accuracy of the first pattern 710. In contrast, in the present embodiment, the width of the first pattern 710 is larger than the width of the second pattern 720, so that the first pattern 710 can be ensured to meet the size requirement even after being over-developed. And, under the blocking protection of the first pattern 710 with a larger width dimension, the over-development of the second pattern 720 is avoided, and the pattern precision of the second pattern 720 is ensured.

Step two, referring to fig. 4e specifically, the patterned mask layer is used as a mask to etch the electrically conductive material layer, that is, the patterned mask layer is used as a mask to sequentially etch the second electrically conductive material layer 400b and the first electrically conductive material layer 400 a. Thus, the electrically conductive material layers corresponding to different node contact windows are mutually separated, and thus mutually separated electrically conductive layers are formed. Wherein, the electric conduction layers that separate each other specifically include: a first electrically conductive layer 410b for constituting the first contact portion 410 and a second electrically conductive layer 420b for constituting the second contact portion 420, and a width dimension of the first electrically conductive layer 410b is larger than a width dimension of the second electrically conductive layer 420 b.

Similarly, when the electrically conductive material layer is etched, the first electrically conductive layer 410b at the edge position is subjected to a larger etching attack, so that the first electrically conductive layer 410b is easily deformed by being eroded by a large amount. Accordingly, in the present embodiment, the width of the first electrically conductive layer 410b is larger than the width of the second electrically conductive layer 420b, so that even if the first electrically conductive layer 410b is attacked by a larger etching attack, the morphology of the first electrically conductive layer 410b can still be ensured. Moreover, under the blocking protection of the first electrically conductive layer 410b with a larger width, the problem of excessive erosion of the second electrically conductive layer 420b adjacent to the first electrically conductive layer 410b can be effectively alleviated.

With continued reference to fig. 4e, in a further aspect, after etching the electrically conductive material layer to expose the isolation material layer 300, the method further includes: the isolation material layer 300 is etched to a predetermined depth to form an isolation layer. By further etching the isolation material layer between the adjacent electrically conductive layers, the conductive material between the adjacent electrically conductive layers can be effectively removed to ensure the isolation between the adjacent electrically conductive layers.

In this embodiment, the first contact portion 410 is located between the first bit line 210 and the second bit line 220, and the top of the first contact portion 410 further laterally covers a portion of the isolation material layer 300 directly above the first bit line 210, so that when the isolation material layer 300 is etched, the isolation material layer directly above the first bit line 210 and covered by the first contact portion 410 is not consumed, and the isolation material layer directly above the first bit line 210 and exposed to the first contact portion 410 is partially etched, thereby forming the first isolation portion 310 above the first bit line 210. And the second contact portion 420 is located between the adjacent second bit lines 220, and when the isolation material layer is etched, the height of the isolation material layer above the second bit lines 220 is reduced, thereby forming a second isolation portion 320 above the second bit lines 220.

Further, after forming the first isolation portion 310 and the second isolation portion 320 having a lower height, forming an isolation insulating layer is further included. The spacer insulating layer is formed on the isolation layer, wherein a portion of the spacer insulating layer formed on the first isolation portion 310 forms a spacer sidewall 910, and a portion of the spacer insulating layer formed on the second isolation portion 320 forms a spacer filling portion 920.

In this embodiment, the method for forming the spacer insulating layer includes, for example: first, an insulating material layer is deposited, which fills the gaps between adjacent second contacts 420 to cover the second isolation portions 320 and also covers the first and third isolation portions of the isolation layer; and then, performing an etching-back process to remove a part of the insulating material layer, which is higher than the node contact part, and to remove a part of the insulating material layer, which covers the third isolation part, so as to form an interval side wall and the interval filling part respectively. In addition, after performing an etch-back process on the insulating material layer to expose the third isolation portion, the third isolation portion may be further etched to partially consume the third isolation portion such that a top surface of the third isolation portion is lower than a top surface of the second isolation portion.

Example two

The difference from the first embodiment is that in this embodiment, a third contact portion and a fourth contact portion are further provided in the peripheral region. Fig. 5 is a cross-sectional view of a memory according to a second embodiment of the invention, as shown in fig. 5, the third contact 430 includes an insulating pillar 430a and a third electrically conductive layer 430b, and the third electrically conductive layer 430b covers a top surface of the insulating pillar 430 a. And, the fourth contact portion 440 includes only an insulating pillar.

Further, the fourth contact portions 440 and the third contact portions 430 are alternately arranged in sequence, and an isolation material is filled between the insulating columns 430a of the third contact portions 430 and the insulating columns of the fourth contact portions 440. In this embodiment, a fourth contact 440 is spaced between the third contact 430 closest to the memory region 100A and the first contact 410, so as to prevent the first electrically conductive layer 410b in the first contact 410 and the third electrically conductive layer 430b in the third contact 430 from being connected to each other. The width of the third electrically conductive layer 430b of the third contact 430 may be the same as or similar to the width of the first electrically conductive layer 410b of the first contact 410.

In a more specific embodiment, the third electrically conductive layer 430b of the third contact 430 covers the top surface of the insulating pillar 430a and also extends to cover the adjacent isolation material in a direction away from the memory region.

With continued reference to fig. 5, the third electrically conductive layer 430b in the third contact 430 is flush with the top surface of the first electrically conductive layer 410b in the first contact 410, and the insulating column 430a of the third contact 430 is higher than the insulating column of the fourth contact 440. In other words, the insulating columns and the isolation material covered by the third electrically conductive layer 430b are higher than the insulating columns and the isolation material not covered by the third electrically conductive layer 430 b.

Further, the memory further includes a spacer 910 ', the space 910' is filled between the first contact portion 410 and the third contact portion 430, and the space 910 'is also filled between the adjacent third contact portions 430, such that the spacer 910' covers the fourth contact portion 440 and the adjacent isolation material.

It should be noted that the insulating pillar 430a of the third contact 430, the insulating pillar of the fourth contact 440, and the insulating contact pillar 410a of the first contact 410 may be simultaneously prepared, and the third electrically conductive layer 430b of the third contact 430 and the first electrically conductive layer 410b of the first contact 410 may be simultaneously prepared. Specifically, the third electrically conductive layer 430b of the third contact 430 and the first electrically conductive layer 410b of the first contact 410 can be formed simultaneously by patterning the same conductive material layer.

In summary, in the memory described above, the width of the first bit line at the edge position in the bit line group is greater than the width of the second bit lines arranged therein, so that when the bit line group is prepared, even if the first bit line at the edge position is easily eroded by a large amount, the morphology of the first bit line can be ensured, and under the blocking protection of the first bit line with a larger width, the second bit line arranged therein can be prevented from being eroded by a large amount, so as to improve the morphology accuracy of the second bit line, thereby facilitating the improvement of the device performance of the formed memory. Similarly, since the width of the first contact portion at the edge position in the node contact portion array is larger than that of the second contact portion, the appearance of the first contact portion can be correspondingly ensured, and the graphic accuracy of the second contact portion can be improved.

In a further embodiment, the active region at the edge position may be defined as a non-functional active region, and the first bit line at the edge position in the bit line group may be defined as a non-functional bit line. Therefore, on one hand, the width size of the first bit line can be adjusted more flexibly; on the other hand, when the functional memory cell is formed based on the active region at the edge position, the performance abnormity of the memory cell is easy to occur, and further the device performance of the formed memory is influenced. Likewise, it is also possible to electrically insulate the first contact at the edge position in the node contact array from the active region below it, so that the first contact is correspondingly a non-functional contact.

It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.

It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.

It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims (12)

1. A memory, comprising:

the semiconductor device comprises a substrate, a plurality of first transistors and a plurality of second transistors, wherein a memory area and a peripheral area are defined on the substrate, the peripheral area is located on the outer side of the memory area, and a plurality of active areas are formed in the memory area of the substrate;

a bit line group formed in the memory region of the substrate, the bit line group including a plurality of bit lines extending in a predetermined direction, the bit lines intersecting corresponding ones of the plurality of active regions, and bit lines arranged at edge positions in the bit line group constituting first bit lines, and bit lines on a side of the first bit lines away from a peripheral region in the bit line group constituting second bit lines; and the number of the first and second groups,

a plurality of node contacts, each of which is at least partially located on one side of the bit line and is formed on the corresponding active region, and of which the node contacts arranged at edge positions constitute first contacts and the node contacts located on one side of the first contacts away from the peripheral region constitute second contacts; the first contact part comprises an insulating contact column which is formed on the substrate and is electrically insulated from the contacted active area, and the second contact part comprises a conductive contact layer which is formed on the substrate and is electrically connected with the contacted active area.

2. The memory of claim 1, further comprising an isolation layer covering a top surface of the bit line, and a portion of the isolation layer covering the first bit line constitutes a first isolation portion;

and the insulated contact column of the first contact portion is positioned at one side of the first bit line, and the first contact portion further comprises a first electrically conductive layer which covers the top surface of the insulated contact column and extends transversely to the first isolation portion, so that the maximum width dimension of the first contact portion is larger than that of the second contact portion.

3. The memory of claim 2, wherein the insulated contact stud of the first contact is located on a side of the first bit line adjacent to the second bit line such that the insulated contact stud is located between the first bit line and an immediately adjacent second bit line, and the first electrically conductive layer of the first contact further extends onto the first isolation in a direction away from the second bit line.

4. The memory of claim 2, wherein a top surface of the conductive contact layer of the second contact is lower than a top surface of the bit line;

and the second contact part also comprises a second electric conduction layer which is formed on the electric conduction contact layer and extends upwards along the height direction so as to enable the top surface of the second electric conduction layer to be flush with the top surface of the first electric conduction layer.

5. The memory of claim 2, wherein a maximum width dimension of the first contact is greater than 1 times and equal to or less than 2 times a maximum width dimension of the second contact.

6. The memory of claim 2, wherein a portion of the isolation layer overlying the second bit line constitutes a second isolation portion, and a top surface of the second contact is higher than a top surface of the second isolation portion;

and the memory further comprises an interval insulating layer, wherein the interval insulating layer is formed on the isolation layer, the part of the interval insulating layer formed on the first isolation part forms an interval side wall, the part of the interval insulating layer formed on the second isolation part forms an interval filling part, and the interval filling part is formed between the adjacent node contact parts.

7. The memory of claim 6, wherein a first portion of the first isolation portion covered by the first electrically conductive layer is higher than a second portion of the first isolation portion uncovered by the first electrically conductive layer so that a sidewall of the first portion and a top surface of the second portion are connected to assume a step-like structure, and the spacer sidewall is formed on the top surface of the second portion and covers the sidewall of the first portion.

8. The memory of claim 1, wherein a width dimension of the first bit line is greater than a width dimension of the second bit line.

9. The memory of claim 8, wherein a width dimension of the first bit line is greater than 1 times and equal to or less than 2 times a width dimension of the second bit line.

10. A method for forming a memory, comprising:

providing a substrate, wherein a memory area and a peripheral area are defined on the substrate, the peripheral area is positioned outside the memory area, and a plurality of active areas are formed in the memory area of the substrate;

forming a bit line group in the memory region of the substrate, wherein the bit line group comprises a plurality of bit lines extending along a predetermined direction, the bit lines intersect with corresponding active regions in the plurality of active regions, and a plurality of node contact windows are defined by the bit lines, the node contact windows arranged at edge positions in the plurality of node contact windows form first contact windows, and the node contact windows positioned at one side of the first contact windows far away from the peripheral region form second contact windows; and the number of the first and second groups,

the first contact window is filled with an insulating contact column which is electrically insulated from an active region below the insulating contact column, and the second contact window is filled with a conductive contact layer which is electrically connected with an active region below the conductive contact layer.

11. The method of forming a memory of claim 10, further comprising:

forming a layer of electrically conductive material overlying the insulated contact stud and the conductive contact layer; and the number of the first and second groups,

and patterning the electric conduction material layer to form an electric conduction layer, wherein the electric conduction layer corresponding to the second contact window forms a second electric conduction layer, the second electric conduction layer is formed above the conductive contact layer, the electric conduction layer corresponding to the first contact window forms a first electric conduction layer, the first electric conduction layer covers the insulated contact column and transversely extends to be positioned right above the first bit line, so that the width dimension of the first electric conduction layer is larger than that of the second electric conduction layer.

12. The method of claim 11, wherein patterning the layer of electrically conductive material to form an electrically conductive layer comprises:

forming a patterned mask layer on the electrically conductive material layer, the patterned mask layer including a first pattern and a second pattern, the first pattern covering the first contact and extending laterally to the first bit line for defining a pattern of the first electrically conductive layer, and the second pattern covering the second contact for defining a pattern of the second electrically conductive layer; and the number of the first and second groups,

and etching the electric conduction material layer by taking the patterned mask layer as a mask to form the first electric conduction layer and the second electric conduction layer, wherein the width dimension of the first electric conduction layer is larger than that of the second electric conduction layer.

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