CN108010919B - TFT array substrate, manufacturing method thereof and display device - Google Patents
TFT array substrate, manufacturing method thereof and display device Download PDFInfo
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- CN108010919B CN108010919B CN201711218906.0A CN201711218906A CN108010919B CN 108010919 B CN108010919 B CN 108010919B CN 201711218906 A CN201711218906 A CN 201711218906A CN 108010919 B CN108010919 B CN 108010919B
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- 239000000758 substrate Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 230000002093 peripheral effect Effects 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 27
- 229910052760 oxygen Inorganic materials 0.000 abstract description 27
- 239000001301 oxygen Substances 0.000 abstract description 27
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 238000009832 plasma treatment Methods 0.000 abstract description 5
- 230000008021 deposition Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000000926 separation method Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses a TFT array substrate, comprising: a substrate; the buffer layer and the active layer are sequentially arranged on the substrate; the insulating layer of setting on the initiative layer, the width of insulating layer is less than the width of initiative layer, and the insulating layer corresponds the middle zone that sets up at the initiative layer, wherein: the peripheral region of the active layer is recessed near the insulating layer. The invention also discloses a manufacturing method of the TFT array substrate and a display device. By implementing the TFT array substrate, the manufacturing method thereof and the display device, oxygen vacancies on the surface of the active layer after plasma treatment can be prevented from diffusing to the channel region, the influence of the diffusion of the oxygen vacancies in the conductive active layer on the TFT leakage current is reduced, and the yield of the display panel is improved.
Description
Technical Field
The invention relates to the field of display panel manufacturing, in particular to a TFT array substrate, a manufacturing method thereof and a display device.
Background
In the conventional fabrication of top gate IGZO TFT substrate, after the GE metal layer electrode is fabricated, the GE metal layer is used as a photomask to perform self-aligned plasma treatment, so that the IGZO surface region of SD contact is made into a conductor, the contact resistance between the IGZO and the SD can be reduced, and the effect similar to ohmic contact is formed.
The problems of the manufacturing method are as follows: the oxygen vacancies in the conductive IGZO will increase, and during the subsequent processing, the oxygen vacancies will diffuse along the surface towards the channel, so that the oxygen vacancies on the upper surface of the IGZO channel region will increase, which will increase the leakage current under the TFT off condition, and the TFT will not be effectively turned off, thereby affecting the TFT characteristics.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a TFT array substrate, a method for manufacturing the same, and a display device, which can prevent oxygen vacancies on the surface of an active layer after plasma treatment from diffusing to a channel region, reduce the influence of oxygen vacancy diffusion in a conductive active layer on TFT leakage current, and improve the yield of a display panel.
In order to solve the above technical problem, an embodiment of the present invention provides a TFT array substrate, including: a substrate; the buffer layer and the active layer are sequentially arranged on the substrate; the insulating layer of setting on the initiative layer, the width of insulating layer is less than the width on initiative layer, and the insulating layer corresponds the middle zone that sets up at the initiative layer, and the peripheral zone that is close to the insulating layer on the initiative layer is equipped with the recess, and the insulating layer coats and is stamped the metal level, and the metal level is filled in the recess on initiative layer simultaneously.
Wherein, the edge of the opening at one side of the groove is close to the position of the area corresponding to the insulating layer on the active layer.
The two grooves are respectively arranged on two opposite sides of the peripheral area, close to the insulating layer, on the active layer.
Wherein the depth of the groove in the active layer is less than the thickness of the active layer.
Wherein, a dielectric layer is arranged on the active layer and the insulating layer and covers the active layer and the insulating layer, and a source drain metal layer is arranged on the dielectric layer.
In order to solve the technical problem, the invention also discloses a manufacturing method of the TFT array substrate, which comprises the following steps: sequentially manufacturing a buffer layer and an active layer on a substrate; depositing an insulating layer on the active layer; coating a photoresist on the insulating layer, and exposing and developing the photoresist; after etching and photoresistance removing, forming a groove in the peripheral area, close to the insulating layer, of the active layer, wherein the width of the insulating layer is smaller than that of the active layer, and the insulating layer is correspondingly arranged in the middle area of the active layer; further comprising: and manufacturing a metal layer on the insulating layer, and filling the metal layer in the groove of the active layer.
Wherein, the edge of the opening at one side of the groove is close to the position of the area corresponding to the insulating layer on the active layer; the two grooves are respectively arranged on two opposite sides of the peripheral area, close to the insulating layer, on the active layer; the depth of the groove in the active layer is smaller than the thickness of the active layer.
Wherein, still include: and manufacturing a dielectric layer covering the active layer and the insulating layer on the active layer and the insulating layer, and manufacturing a source drain metal layer on the dielectric layer.
The invention also discloses a display device with the TFT array substrate.
The TFT array substrate, the manufacturing method thereof and the display device have the following beneficial effects:
firstly, a buffer layer and an active layer are sequentially arranged on a substrate; set up the insulating layer on the initiative layer, the width of insulating layer is less than the width on initiative layer, and the insulating layer corresponds the middle zone that sets up at the initiative layer, and the peripheral zone that is close to the insulating layer on the initiative layer is equipped with the recess, is equipped with the metal level in the recess, and the oxygen vacancy on the initiative layer surface after handling is by the metal level separation, makes the oxygen vacancy can't enter into the recess on initiative layer.
And secondly, the influence of oxygen vacancy diffusion in the conductive active layer on TFT leakage current is reduced, and the yield of the display device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of exposing and developing a photoresist by a method for manufacturing a TFT array substrate according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a groove obtained after etching and photoresist removal by using a TFT array substrate manufacturing method according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a metal layer deposited on a groove by a method for manufacturing a TFT array substrate according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a TFT array substrate according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 4, it is a first embodiment of the TFT array substrate of the present invention.
The TFT array substrate in this embodiment includes: a substrate 101; a buffer layer 102 and an active layer 103 sequentially disposed on the substrate 101; an insulating layer 104 disposed on the active layer 103, wherein: the active layer 103 has a groove T around the periphery of the region corresponding to the insulating layer 104.
In specific implementation, the grooves T are formed as follows: the buffer layer 102 and the active layer 103 are sequentially formed on the substrate 101, and after patterning the buffer layer 102 and the active layer 103, an insulating layer 104 is deposited on the active layer 103, a resist is applied, and the resist is exposed and developed using a semi-transparent mask blank 105. Wherein: the groove T is formed at the following positions: the peripheral region of the active layer 103 near the insulating layer 104 has a structure in which the width of the insulating layer 104 is smaller than the width of the active layer 103, and the insulating layer 104 is correspondingly disposed in the middle region of the active layer 103.
The function of the groove T is: in the subsequent plasma treatment and anneal treatment processes, the oxygen vacancy on the surface of the active layer 103 is blocked by the groove T, so that the oxygen vacancy cannot enter the channel region of the active layer 103.
Preferably, one side opening edge T1 of the groove T is adjacent to the region of the active layer 103 corresponding to the insulating layer 104. Therefore, the manufacturing process flows such as subsequent deposition and the like are simplified.
Preferably, two grooves T are provided, and the two grooves T are respectively disposed on two opposite sides of the peripheral region of the active layer 103 near the insulating layer 104, and meanwhile, the depth of the groove T in the active layer 103 is smaller than the thickness of the active layer 103. Therefore, the manufacturing process flows such as subsequent deposition and the like are simplified.
Further, in the present embodiment, the insulating layer 104 is covered with a metal layer 106, and the metal layer 106 is filled in the groove T of the active layer 103 to form a metal layer 106a as shown in the figure. Thus, after the processing, in the embodiment of plasma processing, and in the subsequent annealing process, the oxygen vacancy on the surface of the active layer 103 is blocked by the metal layer 106a, so that the oxygen vacancy cannot enter the channel region of the active layer 103. That is, the oxygen vacancy on the surface of the conductive active layer 103 is blocked by the metal layer 106a embedded on both sides of the channel region of the active layer 103 when diffusing, so that the oxygen vacancy on the surface of the active layer 103 after plasma processing can be prevented from diffusing into the channel region, and the influence of the oxygen vacancy diffusion in the conductive active layer on the TFT leakage current can be reduced.
Further, a dielectric layer 201 is formed on the active layer 103 and the insulating layer 104 to cover the active layer 103 and the insulating layer 104, and a source/drain metal layer 202 is formed in the dielectric layer 201.
Referring to fig. 1 to fig. 3 in combination, the invention also discloses a manufacturing method of the TFT array substrate, which includes the following steps: sequentially manufacturing a buffer layer 102 and an active layer 103 on a substrate 101; depositing an insulating layer 104 on the active layer 103; a resist 107 is applied on the insulating layer 104, and the resist 107 is exposed and developed. After etching and photoresist removal, a groove T is formed in the peripheral region of the active layer 103 close to the insulating layer 104. In the process, the width of the insulating layer 104 is smaller than the width of the active layer 103, and the insulating layer 104 is correspondingly disposed in the middle region of the active layer 103.
The function of the groove T is: in the subsequent plasma treatment and anneal treatment processes, the oxygen vacancy on the surface of the active layer 103 is blocked by the groove T, so that the oxygen vacancy cannot enter the channel region of the active layer 103.
Preferably, one side opening edge T1 of the groove T is adjacent to the region of the active layer 103 corresponding to the insulating layer 104. Therefore, the manufacturing process flows such as subsequent deposition and the like are simplified.
Preferably, two grooves T are provided, and the two grooves T are respectively disposed on two opposite sides of the peripheral region of the active layer 103 near the insulating layer 104, and meanwhile, the depth of the groove T in the active layer 103 is smaller than the thickness of the active layer 103. Therefore, the manufacturing process flows such as subsequent deposition and the like are simplified.
Further, a metal layer 106 is covered on the insulating layer 104, and the metal layer 106 is filled in the groove T of the active layer to form a metal layer 106a as shown in the figure. Thus, after the processing, in the embodiment of plasma processing, and in the subsequent annealing process, the oxygen vacancy on the surface of the active layer 103 is blocked by the metal layer 106a, so that the oxygen vacancy cannot enter the channel region of the active layer 103. That is, the oxygen vacancy on the surface of the conductive active layer 103 is blocked by the metal layer 106a embedded on both sides of the channel region of the active layer 103 when diffusing, so that the oxygen vacancy on the surface of the active layer 103 after plasma processing can be prevented from diffusing into the channel region, and the influence of the oxygen vacancy diffusion in the conductive active layer on the TFT leakage current can be reduced.
Further, the method also comprises the following steps: and manufacturing a dielectric layer 201 covering the active layer 103 and the insulating layer 104 on the active layer 103 and the insulating layer 104, and manufacturing a source drain metal layer 202 in the dielectric layer 201.
The invention also discloses a display device comprising the TFT array substrate, wherein the manufacturing process of the display device further comprises the steps of covering the flat layer 203 on the dielectric layer 201 and the source drain metal layer 202, covering the anode layer 204 on the flat layer 203, and manufacturing the pixel separation layer 205 and the light-emitting layer 206 on the anode layer 204 so as to form an O L ED driving device.
The TFT array substrate, the manufacturing method thereof and the display device have the following beneficial effects:
firstly, a buffer layer and an active layer are sequentially arranged on a substrate; set up the insulating layer on the initiative layer, the width of insulating layer is less than the width on initiative layer, and the insulating layer corresponds the middle zone that sets up at the initiative layer, and the peripheral zone that is close to the insulating layer on the initiative layer is equipped with the recess, is equipped with the metal level in the recess, and the oxygen vacancy on the initiative layer surface after handling is by the metal level separation, makes the oxygen vacancy can't enter into the recess on initiative layer.
And secondly, the influence of oxygen vacancy diffusion in the conductive active layer on TFT leakage current is reduced, and the yield of the display device is improved.
Claims (9)
1. A TFT array substrate, comprising:
a substrate;
the buffer layer and the active layer are sequentially arranged on the substrate;
the insulating layer is arranged on the active layer, the width of the insulating layer is smaller than that of the active layer, and the insulating layer is correspondingly arranged in the middle area of the active layer;
a groove is formed in the peripheral area, close to the insulating layer, of the active layer, a metal layer covers the insulating layer, and meanwhile the metal layer is filled in the groove of the active layer.
2. The TFT array substrate of claim 1, wherein an opening edge of one side of the groove is located adjacent to a region of the active layer corresponding to the insulating layer.
3. The TFT array substrate of claim 2, wherein the two grooves are disposed on opposite sides of the peripheral region of the active layer adjacent to the insulating layer.
4. The TFT array substrate of claim 1, wherein the recess has a depth within the active layer that is less than a thickness of the active layer.
5. The TFT array substrate of any of claims 1-4, wherein a dielectric layer is disposed over the active layer and the insulating layer, the dielectric layer having a source drain metal layer disposed thereon.
6. A manufacturing method of a TFT array substrate is characterized by comprising the following steps:
sequentially manufacturing a buffer layer and an active layer on a substrate;
depositing an insulating layer on the active layer in a whole layer;
coating a photoresist on the insulating layer, and exposing and developing the photoresist;
after etching and photoresistance are removed, a groove is formed in the peripheral area, close to the insulating layer, on the active layer, the width of the insulating layer is smaller than that of the active layer, and the insulating layer is correspondingly arranged in the middle area of the active layer, and the method further comprises the following steps: and manufacturing a metal layer on the insulating layer, and filling the metal layer in the groove of the active layer.
7. The method of manufacturing the TFT array substrate of claim 6, wherein an opening edge of one side of the groove is adjacent to a region of the active layer corresponding to the insulating layer;
the two grooves are respectively arranged on two opposite sides of the peripheral area, close to the insulating layer, on the active layer; the depth of the groove in the active layer is smaller than the thickness of the active layer.
8. The method of manufacturing the TFT array substrate of claim 6 or 7, further comprising: and covering the active layer and the dielectric layer of the insulating layer on the active layer and the insulating layer, and manufacturing a source drain metal layer on the dielectric layer.
9. A display device comprising the TFT array substrate according to any one of claims 1 to 5.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711218906.0A CN108010919B (en) | 2017-11-28 | 2017-11-28 | TFT array substrate, manufacturing method thereof and display device |
| PCT/CN2018/071557 WO2019104834A1 (en) | 2017-11-28 | 2018-01-05 | Tft array substrate and manufacturing method therefor and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711218906.0A CN108010919B (en) | 2017-11-28 | 2017-11-28 | TFT array substrate, manufacturing method thereof and display device |
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| CN108010919A CN108010919A (en) | 2018-05-08 |
| CN108010919B true CN108010919B (en) | 2020-07-31 |
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| CN115663032A (en) * | 2019-01-10 | 2023-01-31 | 合肥鑫晟光电科技有限公司 | Thin film transistor, preparation method thereof, array substrate and display device |
| CN110752219B (en) * | 2019-10-29 | 2022-07-26 | 昆山国显光电有限公司 | Thin film transistor and display panel |
| CN114784113A (en) * | 2022-04-02 | 2022-07-22 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103295962A (en) * | 2013-05-29 | 2013-09-11 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
| CN104979380A (en) * | 2015-05-26 | 2015-10-14 | 合肥鑫晟光电科技有限公司 | Thin film transistor and manufacturing method therefor |
| CN106876280A (en) * | 2017-04-24 | 2017-06-20 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof |
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| US8987808B2 (en) * | 2006-03-29 | 2015-03-24 | Cambridge Enterprise Limited | Thin film transistor with accurately aligned electrode patterns and electronic device(s) that include same |
| KR101949861B1 (en) * | 2012-10-10 | 2019-02-20 | 삼성디스플레이 주식회사 | Organic light emitting diode display and method for manufacturing organic light emitting diode display |
| CN105097824B (en) * | 2014-05-22 | 2019-12-10 | 群创光电股份有限公司 | Thin film transistor substrate, manufacturing method thereof and display |
| CN104037090B (en) * | 2014-06-19 | 2016-10-19 | 深圳市华星光电技术有限公司 | Oxide thin film transistor construction manufacturing method and oxide thin film transistor structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103295962A (en) * | 2013-05-29 | 2013-09-11 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
| CN104979380A (en) * | 2015-05-26 | 2015-10-14 | 合肥鑫晟光电科技有限公司 | Thin film transistor and manufacturing method therefor |
| CN106876280A (en) * | 2017-04-24 | 2017-06-20 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof |
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| WO2019104834A1 (en) | 2019-06-06 |
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