CN216213426U - QFN (quad Flat No lead) design packaging structure of SoC (System on chip) - Google Patents

QFN (quad Flat No lead) design packaging structure of SoC (System on chip) Download PDF

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Publication number
CN216213426U
CN216213426U CN202122697673.5U CN202122697673U CN216213426U CN 216213426 U CN216213426 U CN 216213426U CN 202122697673 U CN202122697673 U CN 202122697673U CN 216213426 U CN216213426 U CN 216213426U
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qfn
soc
frame
pads
package structure
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CN202122697673.5U
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Chinese (zh)
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丁海松
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Hefei Ingenic Technology Co ltd
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Hefei Ingenic Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body

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Abstract

The utility model provides a QFN design packaging structure of SoC, which comprises: SoC wafer d ie and QFN frame; the SoC wafer d ie is positioned on the QFN packaging frame and is electrically connected through a routing; functional interface bonding pads, power bonding pads and ground bonding pads are distributed around the SoC wafer d i e; the central area of the QFN frame comprises a large bonding pad, and frame conductive welding pins for realizing electric connection are arranged around the periphery of the package of the large bonding pad; and a bridge is arranged between two of the QFN frame conductive welding pins, and the power supply welding pads of the SoC wafer d ie are connected to the bridge one by one through routing according to the routing direction.

Description

QFN (quad Flat No lead) design packaging structure of SoC (System on chip)
Technical Field
The utility model relates to the technical field of chip packaging, in particular to a QFN (quad Flat No lead) design packaging structure of an SoC (System on chip).
Background
In the prior art, generally, the periphery of an SoC wafer contains abundant functional interface pads, and power pads are uniformly distributed on the periphery of the SoC in order to stably operate.
QFN is a quad or rectangular package with a large area of exposed bonding pad at the center of the metal frame at the bottom of the package for heat conduction, and frame conductive pins surrounding the large bonding pad for electrical connection. Because the QFN package has only one metal frame and no package substrate, the QFN package has low production cost and excellent heat dissipation performance and is widely applied to the field of integrated circuit chip package.
In the prior art, the electrical connection between the die of the SoC wafer and the conductive solder pins of the QFN frame is realized by package and wire bonding. However, only one row of conductive welding pins are arranged around the QFN package, the number of the conductive welding pins of the whole package is limited, and the power supply pads uniformly distributed around the SoC wafer need to be wired out to form the power supply welding pins on the QFN package so as to supply power at board level, so that a plurality of conductive welding pins of the QFN frame are occupied, which is not beneficial to the enrichment and expansion of chip functional interfaces. If the functional interface is added, the number of the frame conductive welding feet is increased, and the chip packaging size is increased, so that the chip packaging cost is increased.
Further, terms commonly used in the art include:
QFN: quad Flat No-leads Package, one of Quad Flat non-leaded packages, surface mount packages.
SoC: system on Chip, a System-on-Chip, is an integrated circuit with a dedicated target that contains the complete System and has the full contents of embedded software.
SUMMERY OF THE UTILITY MODEL
In order to solve the above problems, the present method is directed to: the application provides a QFN of SoC designs packaging structure, couple together the electrically conductive leg internal connection of QFN frame through setting up the bridging, power pad routing on the SoC wafer die to the bridging on to avoid SoC wafer power pad routing and function interface routing cross phenomenon, reduce the encapsulation routing degree of difficulty, also can reduce the power leg quantity of QFN frame, the function interface of being convenient for expands, thereby promote SoC chip competitiveness.
Specifically, the present invention provides a QFN design package structure of SoC, which includes:
SoC wafer die and QFN frame;
the SoC wafer die is positioned on the QFN packaging frame and is electrically connected through a routing;
functional interface bonding pads, power bonding pads and ground bonding pads are distributed around the SoC wafer die;
the central area of the QFN frame comprises a large bonding pad, and frame conductive welding pins for realizing electric connection are arranged around the periphery of the package of the large bonding pad;
and a bridge is arranged between two of the QFN frame conductive welding pins, and a power supply welding pad of the SoC wafer die is electrically connected to the bridge through a routing according to the routing direction.
The bridging is to select a first conductive welding foot and a second conductive welding foot of the QFN frame from at least one side of the periphery of the QFN frame according to the distribution condition of the SoC power supply welding pads, and connect the two conductive welding feet into a whole to form the bridging.
The four sides of the periphery of the QFN frame can connect two conductive welding feet on one side into a whole through bridging according to actual conditions, namely at least one bridging is arranged.
And the power supply bonding pad of the SoC wafer die is connected to the bridge of the QFN power supply welding pin through a routing according to the routing direction.
And the ground pads uniformly distributed on the periphery of the SoC wafer die are electrically connected to the central large pad of the QFN frame through bonding wires.
The functional interface of the SoC wafer die is electrically connected to the remaining unconnected conductive pins of the QFN frame by wire bonding.
And power supply pads required by the operation of the SoC are uniformly distributed around the wafer die so as to meet the requirement that a power supply channel for the operation of the system is sufficient.
Thus, the present application has the advantages that: through above-mentioned packaging structure, the power routing on the SoC wafer is to the bridging to avoid SoC wafer power pad routing and function interface routing cross phenomenon, reduce the encapsulation routing degree of difficulty, also can reduce the power leg quantity of QFN frame, the function interface of being convenient for expands, thereby promotes SoC chip competitiveness.
Drawings
The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the utility model and together with the description serve to explain the principles of the utility model.
Fig. 1 is a schematic diagram of a package structure according to an embodiment of the utility model.
Fig. 2 is a schematic diagram of a package structure according to another embodiment of the utility model.
Detailed Description
In order that the technical contents and advantages of the present invention can be more clearly understood, the present invention will now be described in further detail with reference to the accompanying drawings.
As shown in fig. 1, the present invention relates to a QFN package structure of SoC:
icon: 100-QFN package frame; 101-the central large pad of the QFN frame; 102-SoC wafer die; 103-ground pads on SoC wafer die; 104-power pads on the SoC wafer die; 105-functional interface pads on SoC wafer die; 106-routing; 107-bridging; 108-conductive leg of QFN frame.
The following detailed description of the embodiments of the present invention will be made with reference to the accompanying drawings, which are provided for more clearly illustrating the mechanism of the present invention and are therefore only taken as examples and not intended to limit the scope of the patent of the present invention.
As shown in fig. 1 and fig. 2, an embodiment of the present invention provides a QFN design package structure of SoC, including: SoC wafer die102 and QFN package frame 100.
The SoC die102 is located on the QFN package frame 100 and electrically connected by a wire bonding 106.
Functional interface pads 105, power pads 104 and ground pads 103 are distributed around the SoC wafer die102, and as shown in fig. 1, the functional interface pads 105, the power pads 104 and the ground pads 103 are distributed on one side of the periphery and are bridged into one; as shown in fig. 2, two functional interface pads 105, a power pad 104 and a ground pad 103 are distributed on two sides of the periphery and are bridged into two.
The central area of the QFN frame comprises a large pad 101, and frame conductive pins 108 for electrical connection are arranged around the periphery of the package surrounding the large pad.
Further, in order to meet the functions and performance of the SoC, the power pads 104 required for the SoC operation are generally uniformly distributed around the wafer die102, so as to meet the requirement of sufficient power supply channels for the system operation.
Further, taking a certain side around the QFN frame, according to the distribution of the SoC power pads 104, a first conductive leg 1081 and a second conductive leg 1082 of the QFN frame are selected, and the two conductive legs are connected into a whole through a bridge 107, and the other three sides can be treated similarly according to the actual situation.
Further, according to the routing direction, the power pads 104 of the SoC wafer die102 may be routed to the bridges 107 of the QFN frame one by one, that is, the power pads 104 are connected to the bridges 107 of the QFN frame through routing.
Further, the landing pads 103 are uniformly distributed around the SoC die102 to provide adequate signal return path and heat dissipation path for SoC operation.
Further, the uniformly distributed ground pads 103 around the SoC wafer die102 are electrically connected to the central large pad 101 of the QFN frame by a wire bonding 106.
Further, the functional interface 105 of the SoC die102 is electrically connected to the remaining conductive pads of the QFN frame through wire bonds 106.
Through the mode, the power supply bonding pad 104 on the SoC wafer die102 is wire-bonded to the bridge 107, so that the phenomenon of crossing the wire bonding of the SoC wafer power supply bonding pad 104 and the wire bonding of the functional interface 105 is avoided, the packaging wire bonding difficulty is reduced, the number of power supply welding pins of the QFN frame can be reduced, the functional interface is convenient to expand, and the competitiveness of the SoC chip is improved.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes may be made to the embodiment of the present invention by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (7)

1. A QFN design package structure of a SoC, the package structure comprising:
SoC wafer die and QFN frame;
the SoC wafer die is positioned on the QFN packaging frame and is electrically connected through a routing;
functional interface bonding pads, power bonding pads and ground bonding pads are distributed around the SoC wafer die;
the central area of the QFN frame comprises a large bonding pad, and frame conductive welding pins for realizing electric connection are arranged around the periphery of the package of the large bonding pad;
it is characterized in that the preparation method is characterized in that,
and a bridge is arranged between two of the QFN frame conductive welding pins, and a power supply welding pad of the SoC wafer die is electrically connected to the bridge through a routing according to the routing direction.
2. The QFN design package structure of an SoC of claim 1, wherein the bridging is implemented by selecting a first conductive pad and a second conductive pad of the QFN frame from at least one side of the QFN frame according to the distribution of the power pads of the SoC, and integrally connecting the two conductive pads.
3. The QFN design package structure of an SoC as claimed in claim 2, wherein four sides of the QFN frame are connected together by at least one bridge, wherein the two conductive pads are connected together by the bridge.
4. The QFN design package structure of SoC of claim 1, wherein the power pads of the SoC wafer die are connected to the bridge of the QFN power pins by wire bonding according to the wire bonding direction.
5. The QFN design package structure of SoC of claim 1, wherein the ground pads uniformly distributed around die of SoC are electrically connected to the central large pad of QFN frame by bonding wires.
6. The QFN design package structure of SoC of claim 1, wherein the functional interface of the SoC die is electrically connected to the remaining unconnected conductive pads of the QFN frame by wire bonding.
7. The QFN design package structure of SoC of claim 1, wherein the power pads required for the operation of SoC are uniformly distributed around the die to satisfy the requirement of sufficient power supply channels for the operation of the system.
CN202122697673.5U 2021-11-05 2021-11-05 QFN (quad Flat No lead) design packaging structure of SoC (System on chip) Active CN216213426U (en)

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Application Number Priority Date Filing Date Title
CN202122697673.5U CN216213426U (en) 2021-11-05 2021-11-05 QFN (quad Flat No lead) design packaging structure of SoC (System on chip)

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Application Number Priority Date Filing Date Title
CN202122697673.5U CN216213426U (en) 2021-11-05 2021-11-05 QFN (quad Flat No lead) design packaging structure of SoC (System on chip)

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CN216213426U true CN216213426U (en) 2022-04-05

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