CN216213374U

CN216213374U - Semiconductor device stacking and packaging structure

Info

Publication number: CN216213374U
Application number: CN202122694060.6U
Authority: CN
Inventors: 王悦聪; 徐艺凌
Original assignee: Sichuan Heentai Semiconductor Co ltd
Current assignee: Sichuan Heentai Semiconductor Co ltd
Priority date: 2021-11-05
Filing date: 2021-11-05
Publication date: 2022-04-05
Anticipated expiration: 2031-11-05

Abstract

The utility model discloses a semiconductor device stacking and packaging structure, and relates to the technical field of semiconductors. The packaging structure comprises a circuit board and a packaging body, wherein the packaging body is arranged on the upper surface of the circuit board, the bottom surface of the packaging body is provided with a mounting groove, the upper surface of the mounting groove is provided with a bottom heat dissipation plate, the upper surface of the bottom heat dissipation plate is provided with a mounting seat, the upper surface of the mounting seat is provided with a wafer, a buffer plate is arranged between the wafer and the mounting seat, the upper surface of the packaging body is sealed by glue, a cover plate is arranged on one surface of the cover plate, and a plurality of heat conduction columns are connected between the bottom heat dissipation plate and the top heat dissipation plate. According to the utility model, through arranging the buffer plate, the multiple groups of heat dissipation plates and the heat conduction columns, double-sided heat dissipation is realized, the heat dissipation efficiency is high, the stability and the weather resistance of the structure during operation are improved, and a good buffer protection effect is achieved.

Description

Semiconductor device stacking and packaging structure

Technical Field

The utility model belongs to the technical field of semiconductors, and particularly relates to a semiconductor device stacking and packaging structure.

Background

The semiconductor packaging refers to a process of processing a wafer passing a test according to a product model and a functional requirement to obtain an independent chip. The packaging process comprises the following steps: the wafer from the previous process of the wafer is cut into small chips after scribing process, then the cut chips are pasted on the corresponding small island of the substrate (lead frame) frame by glue, and then the bonding pads of the chips are connected to the corresponding pins of the substrate by utilizing superfine metal (gold tin copper aluminum) wires or conductive resin to form the required circuit; the individual chips are then encapsulated and protected by a plastic housing.

The existing semiconductor packaging structure usually radiates the wafer at the bottom of the packaging body, the heat is not easy to pour out, the anti-seismic protection effect of the wafer is achieved, and the wafer is easy to damage due to the vibration of a circuit board in the transportation process; accordingly, a semiconductor device stack package junction is provided.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a semiconductor device stacking and packaging structure, which solves the problems that the wafer is generally radiated at the bottom of a packaging body, heat is not easy to pour out, the wafer is easy to damage due to vibration of a circuit board during transportation and the vibration of the wafer is easy to protect the wafer when the wafer is carried.

In order to solve the technical problems, the utility model is realized by the following technical scheme:

the utility model relates to a semiconductor device stacking and packaging structure, which comprises a circuit board and a packaging body, wherein the packaging body is arranged on the upper surface of the circuit board, the bottom surface of the packaging body is provided with a mounting groove, the upper surface of the mounting groove is provided with a bottom heat dissipation plate, the upper surface of the bottom heat dissipation plate is provided with a mounting seat, the upper surface of the mounting seat is provided with a wafer, a buffer plate is arranged between the wafer and the mounting seat, the upper surface of the packaging body is sealed by glue and provided with a cover plate, one surface of the cover plate is provided with a top heat dissipation plate, a plurality of heat conduction columns are connected between the bottom heat dissipation plate and the top heat dissipation plate, the wafer is supported by the mounting seat, the wafer is effectively buffered and protected by the buffer plate, the heat generated inside the packaging body is effectively absorbed by the bottom heat dissipation plate, the heat generated by the bottom heat dissipation plate is conducted to the top heat dissipation plate by the heat conduction columns, and the heat in the packaging body is rapidly led out by the two plates, realize two-sided heat dissipation, the radiating efficiency is high, has promoted stability and weatherability when this structure moves.

A plurality of pins are arranged on two opposite side walls of the packaging body, and gold wires are connected between the pins and the wafer.

Be provided with a plurality of blotters between pin and the packaging body, the blotter is protected the pin effectively, promotes the antidetonation effect of pin, avoids the pin rupture.

The edge groove has been seted up to the buffer pad upper surface, the pin bottom surface is provided with spacing arris, spacing arris clamps the cooperation with the edge groove, and spacing arris cooperation edge groove promotes the stability after the pin assembly, avoids pin and packaging body disconnection.

The bottom radiating plate is provided with a plurality of radiating fins in a bottom array, and the radiating effect of the bottom radiating plate is improved through the radiating fins because the heat at the bottom of the packaging body is not easy to dissipate.

A plurality of heat dissipation through grooves are formed between the bottom heat dissipation plate and the circuit board, and the heat dissipation through grooves improve the bottom heat dissipation effect.

The two opposite side walls of the packaging body are respectively provided with a plurality of side radiating grooves in an array mode, the side radiating grooves can lead out heat inside the packaging body from the sides, and the radiating effect of the packaging body is further improved.

The utility model has the following beneficial effects:

according to the utility model, the buffer plate is arranged, so that the wafer is effectively protected in a buffering manner, and the phenomenon that the wafer is easily damaged due to vibration of the circuit board in the transportation process is avoided; the bottom heat dissipation plate is arranged to effectively absorb heat generated inside the packaging body, the heat conduction column conducts the heat generated by the bottom heat dissipation plate to the top heat dissipation plate, the two plates quickly conduct the heat inside the packaging body out, double-sided heat dissipation is achieved, heat dissipation efficiency is high, and stability and weather resistance of the structure during operation are improved; the buffering cushion is arranged, so that the pins are effectively protected, the anti-seismic effect of the pins is improved, and the pins are prevented from being broken; through setting up fin, heat dissipation logical groove and side radiating groove, further promote the radiating effect of this packaging body.

Of course, it is not necessary for any product in which the utility model is practiced to achieve all of the above-described advantages at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic isometric view of a semiconductor device package on package structure;

FIG. 2 is a top view of a stacked package structure of semiconductor devices;

FIG. 3 is a schematic view of the cross-sectional structure A-A of FIG. 2;

FIG. 4 is a partial enlarged view of portion B of FIG. 3;

fig. 5 is a front view of a stacked package structure of semiconductor devices.

In the drawings, the components represented by the respective reference numerals are listed below: 1. a circuit board; 2. a package body; 3. mounting grooves; 4. a heat sink; 5. a bottom heat dissipation plate; 6. a mounting seat; 7. a buffer plate; 8. a wafer; 9. a heat dissipation through groove; 10. gold thread; 11. a pin; 12. a limiting edge; 13. a cushion pad; 14. a ridge groove; 15. a cover plate; 16. a top heat sink plate; 17. a heat-conducting column; 18. side radiating grooves.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it is to be understood that the terms "upper", "middle", "outer", "inner", and the like, indicate orientations or positional relationships, are used for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referenced components or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.

Referring to fig. 1-5, the present invention is a semiconductor device stacked package structure, including a circuit board 1 and a package 2, the package 2 is mounted on the upper surface of the circuit board 1, the bottom surface of the package 2 is provided with a mounting groove 3, the upper surface of the mounting groove 3 is provided with a bottom heat sink 5, the upper surface of the bottom heat sink 5 is provided with a mounting seat 6, the upper surface of the mounting seat 6 is provided with a chip 8, a buffer plate 7 is arranged between the chip 8 and the mounting seat 6, the upper surface of the package 2 is encapsulated with a cover plate 15, one surface of the cover plate 15 is provided with a top heat sink 16, a plurality of heat conduction posts 17 are connected between the bottom heat sink 5 and the top heat sink 16, the mounting seat 6 supports the chip 8, the chip 8 is effectively protected by the buffer plate 7, the bottom heat sink 5 effectively absorbs heat generated inside the package 2, the heat generated by the bottom heat sink 5 is conducted to the top heat sink 16 by the heat conduction posts 17, two boards are quick to derive the heat inside the packaging body 2, double-sided heat dissipation is realized, the heat dissipation efficiency is high, and the stability and the weather resistance during the operation of the structure are improved.

A plurality of pins 11 are arranged on two opposite side walls of the packaging body 2, and gold wires 10 are connected between the pins 11 and the wafer 8; a plurality of cushion pads 13 are arranged between the pins 11 and the package body 2, the cushion pads 13 effectively protect the pins 11, the shock-resistant effect of the pins 11 is improved, and the pins 11 are prevented from being broken; arris groove 14 has been seted up to blotter 13 upper surface, and 11 bottoms surfaces of pin are provided with spacing arris 12, and spacing arris 12 clamps the cooperation with arris groove 14, and spacing arris 12 cooperation arris groove 14 promotes the stability after 11 pins assemble, avoids pin 11 and packaging body 2 disconnection.

The bottom surface of the bottom heat dissipation plate 5 is provided with a plurality of heat dissipation fins 4 in an array mode, and the heat at the bottom of the packaging body 2 is not easy to dissipate, so that the heat dissipation effect of the bottom heat dissipation plate 5 is improved through the heat dissipation fins 4.

A plurality of heat dissipation through grooves 9 are formed between the bottom heat dissipation plate 5 and the circuit board 1, and the heat dissipation through grooves 9 improve the heat dissipation effect of the bottom; the two opposite side walls of the package body 2 are all arrayed with a plurality of side radiating grooves 18, the side radiating grooves 18 can lead out the heat inside the package body 2 from the side edges, and the radiating effect of the package body 2 is further improved.

The embodiment is a method for using a semiconductor device stack package structure as shown in fig. 1-5: mount pad 6 supports wafer 8, through buffer board 7, cushion protection is carried out to wafer 8 effectively, the inside heat that produces of packaging body 2 is absorbed effectively to bottom heating panel 5, heat conduction post 17 conducts the heat that bottom heating panel 5 produced to top heating panel 16, two quick exporting the inside heat of packaging body 2, realize two-sided heat dissipation, the radiating efficiency is high, stability and weatherability when having promoted this structure operation, blotter 13 protects pin 11 effectively, promote the antidetonation effect of pin 11, avoid pin 11 to break, spacing arris 12 cooperation arris groove 14 promotes the stability after the pin 11 assembles, avoid pin 11 and packaging body 2 disconnection, fin 4 and radiating through groove 9 promote the radiating effect of bottom heating panel 5, side radiating groove 18 can be derived the inside heat of packaging body 2 from the side, further promote the radiating effect of this packaging body 2.

In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The preferred embodiments of the utility model disclosed above are intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the utility model to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the utility model and the practical application, to thereby enable others skilled in the art to best utilize the utility model. The utility model is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor device stack package structure includes a wiring board (1) and a package body (2), characterized in that: packaging body (2) is installed in circuit board (1) upper surface, packaging body (2) bottom surface is provided with mounting groove (3), mounting groove (3) upper surface mounting has bottom heating panel (5), bottom heating panel (5) upper surface mounting has mount pad (6), mount pad (6) upper surface mounting has wafer (8), be provided with buffer board (7) between wafer (8) and mount pad (6), packaging body (2) upper surface glue has apron (15), apron (15) surface is provided with top heating panel (16), be connected with a plurality of heat conduction posts (17) between bottom heating panel (5) and top heating panel (16).

2. The stacked package structure of semiconductor devices according to claim 1, wherein a plurality of leads (11) are mounted on two opposite sidewalls of the package body (2), and gold wires (10) are connected between the leads (11) and the die (8).

3. The stacked package structure of semiconductor devices according to claim 2, wherein a plurality of cushions (13) are disposed between the leads (11) and the package body (2).

4. The stacked package structure of claim 3, wherein the buffer pad (13) has a groove (14) on the top surface thereof, the lead (11) has a limiting rib (12) on the bottom surface thereof, and the limiting rib (12) is snap-fitted into the groove (14).

5. The stacked package structure of semiconductor devices as claimed in claim 1, wherein the bottom surface of the bottom heat spreader (5) is arrayed with a plurality of heat sinks (4).

6. The stacked package structure of semiconductor devices as claimed in claim 5, wherein a plurality of heat dissipating through grooves (9) are formed between the bottom heat dissipating plate (5) and the circuit board (1).

7. The stacked package structure of claim 1, wherein the package body (2) has a plurality of side heat sinks (18) arrayed on two opposite sidewalls.