CN216210991U - Wireless transmission multi-path RISC-V chip debugger based on WIFI - Google Patents
Wireless transmission multi-path RISC-V chip debugger based on WIFI Download PDFInfo
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- CN216210991U CN216210991U CN202122603431.5U CN202122603431U CN216210991U CN 216210991 U CN216210991 U CN 216210991U CN 202122603431 U CN202122603431 U CN 202122603431U CN 216210991 U CN216210991 U CN 216210991U
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 46
- 230000002093 peripheral effect Effects 0.000 claims abstract description 8
- 230000009286 beneficial effect Effects 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
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Abstract
The utility model discloses a wireless transmission multi-channel RISC-V chip debugger based on WIFI, belonging to the field of RISC-V development; the wireless transmission multi-path RISC-V chip debugger based on WIFI is characterized in that the debugger specifically comprises a multi-path debugger module and a wireless transmission controller module; the multi-path debugger module comprises a multi-path multiplexing transmission chip and a microcontroller chip A; the wireless transmission controller module comprises a WIFI transmission chip, a microcontroller chip and a peripheral circuit; a user remotely connects a wireless transmission controller module of the debugger through wireless WIFI, selects a RISC-V chip to be debugged, wirelessly transmits a program and data to be downloaded to the debugger, and can remotely read the state and register information of the debugged chip; the multi-path debugger module can be simultaneously connected with a plurality of paths of debugged RISC-V chips through a plurality of JTAG interfaces, and the multiplexing transmission chip gates a certain path of RISC-V chip for debugging according to the gating instruction sent by the wireless transmission controller module.
Description
Technical Field
The utility model discloses a wireless transmission multichannel RISC-V chip debugging based on WIFI relates to RISC-V development technical field.
Background
When the RISC-V embedded system is developed, in order to configure the RISC-V chip and carry out kernel on-line debugging, a JTAG debugging downloader is needed to be used for programming programs and data, namely ELF files, into the chip from a host. In many debugging processes, one host is often required to be used for simultaneously debugging a plurality of RISC-V chips, the RISC-V chips and the host cannot be powered off, and a plurality of boards may need to be debugged in the same way. Because the hot plug of the RISC-V chip may cause the burning of JTAG pins, a plurality of JTAG debugging downloaders are needed, and the hot plug of usb download lines is frequently needed, on one hand, the resource waste is caused, on the other hand, the burning of host usb ports is possibly caused, and the debugging environment needs to be set beside the debugged RISC-V chip.
Aiming at the defects in the prior art, the utility model provides a wireless transmission multi-path RISC-V chip debugger based on WIFI (wireless fidelity), which aims to solve the problems.
SUMMERY OF THE UTILITY MODEL
Aiming at the problems in the prior art, the utility model provides a wireless transmission multi-path RISC-V chip debugger based on WIFI, which adopts the technical scheme that: a wireless transmission multi-path RISC-V chip debugger based on WIFI (wireless fidelity), which specifically comprises a multi-path debugger module and a wireless transmission controller module;
the multi-path debugger module comprises a multi-path multiplexing transmission chip and a microcontroller chip A;
the wireless transmission controller module comprises a WIFI transmission chip, a microcontroller chip and a peripheral circuit;
the WIFI transmission chip circuit is connected with a RISC-V microcontroller chip, and the RISC-V microcontroller chip is connected with JTAG interface signals of the multi-channel debugger module;
the multiplexing transmission chip gates a certain path of RISC-V microcontroller chip for debugging through a micro-control chip A signal according to a gating instruction issued by the wireless transmission controller module.
The microcontroller chip A is an STM32 microcontroller chip.
The STM32 microcontroller chip runs GDB debug software.
The peripheral circuit includes an SRAM memory chip.
The utility model has the beneficial effects that: a user remotely connects a wireless transmission controller module of the debugger through wireless WIFI, selects a RISC-V chip to be debugged, wirelessly transmits a program and data to be downloaded to the debugger, and can remotely read the state and register information of the debugged chip; the multi-path debugger module can be simultaneously connected with a plurality of paths of debugged RISC-V chips through a plurality of JTAG interfaces, and the multiplexing transmission chip gates a certain path of RISC-V chip for debugging according to the gating instruction sent by the wireless transmission controller module.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural view of the present invention.
Detailed Description
The present invention is further described below in conjunction with the following figures and specific examples so that those skilled in the art may better understand the present invention and practice it, but the examples are not intended to limit the present invention.
A wireless transmission multi-path RISC-V chip debugger based on WIFI (wireless fidelity), which specifically comprises a multi-path debugger module and a wireless transmission controller module;
the multi-path debugger module comprises a multi-path multiplexing transmission chip and a microcontroller chip A;
the wireless transmission controller module comprises a WIFI transmission chip, a microcontroller chip and a peripheral circuit;
the WIFI transmission chip circuit is connected with a RISC-V microcontroller chip, and the RISC-V microcontroller chip is connected with JTAG interface signals of the multi-channel debugger module;
the multiplexing transmission chip gates a certain path of RISC-V microcontroller chip for debugging through a signal A of the microcontroller chip according to a gating instruction issued by the wireless transmission controller module;
further, the microcontroller chip a is an STM32 microcontroller chip;
when the novel debugger works, a user remotely connects a wireless transmission controller module of the novel debugger through wireless WIFI, selects a RISC-V microcontroller chip to be debugged, wirelessly transmits a program and data to be downloaded to a multi-path debugger module, and can remotely read the state and register information of the debugged chip;
the multi-path debugger module can be simultaneously connected with a plurality of paths of debugged RISC-V microcontroller chips through a plurality of JTAG interfaces, and the multiplexing transmission chip gates a certain path of RISC-V microcontroller chip for debugging according to a gating instruction sent by the wireless transmission controller module; the debugger can be used for facilitating a user to remotely and wirelessly debug a target RISC-V microcontroller chip, and meanwhile, in large-scale board product debugging, frequent manual RISC-V debugging downloader hot plug is avoided, JTAT related GPIO pins of the RISC-V microcontroller chip are prevented from being burnt, and remote real-time flexible kernel downloading and debugging of a plurality of RISC-V microcontroller chips are realized;
furthermore, the STM32 microcontroller chip runs GDB debugging software and is responsible for downloading programs and data to the selected RISC-V microcontroller chip according to the instruction of the remote host, and simultaneously reads the register of the debugged chip according to the instruction of the remote host and sends the data to the wireless transmission controller module;
furthermore, the peripheral circuit comprises peripheral circuits such as an SRAM (static random access memory) storage chip and the like, and is responsible for providing a hardware environment for the work of the WIFI transmission chip.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (4)
1. A wireless transmission multi-path RISC-V chip debugger based on WIFI is characterized in that the debugger specifically comprises a multi-path debugger module and a wireless transmission controller module;
the multi-path debugger module comprises a multi-path multiplexing transmission chip and a microcontroller chip A;
the wireless transmission controller module comprises a WIFI transmission chip, a RISC-V microcontroller chip and a peripheral circuit;
the WIFI transmission chip circuit is connected with a RISC-V microcontroller chip, and the RISC-V microcontroller chip is connected with JTAG interface signals of the multi-channel debugger module;
the multiplexing transmission chip gates a certain path of RISC-V microcontroller chip for debugging through a micro-control chip A signal according to a gating instruction issued by the wireless transmission controller module.
2. A WIFI-based wireless transport multi-way RISC-V chip debugger according to claim 1 characterized by that the microcontroller chip a is STM32 microcontroller chip.
3. A WIFI-based wireless transport multi-way RISC-V chip debugger according to claim 2 characterized by the STM32 microcontroller chip running GDB debug software.
4. A WIFI-based wireless transport multi-way RISC-V chip debugger according to claim 3, characterized by that the peripheral circuit comprises SRAM memory chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202122603431.5U CN216210991U (en) | 2021-10-28 | 2021-10-28 | Wireless transmission multi-path RISC-V chip debugger based on WIFI |
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| CN202122603431.5U CN216210991U (en) | 2021-10-28 | 2021-10-28 | Wireless transmission multi-path RISC-V chip debugger based on WIFI |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115454881A (en) * | 2022-11-10 | 2022-12-09 | 北京红山微电子技术有限公司 | Debugging system and debugging method of RISC-V architecture |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115454881A (en) * | 2022-11-10 | 2022-12-09 | 北京红山微电子技术有限公司 | Debugging system and debugging method of RISC-V architecture |
| CN115454881B (en) * | 2022-11-10 | 2023-03-03 | 北京红山微电子技术有限公司 | Debugging system and debugging method of RISC-V architecture |
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