CN204270060U - STM32F103R8T6 single-chip minimum system plate - Google Patents
STM32F103R8T6 single-chip minimum system plate Download PDFInfo
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- CN204270060U CN204270060U CN201420656197.XU CN201420656197U CN204270060U CN 204270060 U CN204270060 U CN 204270060U CN 201420656197 U CN201420656197 U CN 201420656197U CN 204270060 U CN204270060 U CN 204270060U
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- minimum system
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- learning board
- rom
- system learning
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Abstract
A kind of STM32F103R8T6 minimum system learning board, solve and around how reducing beginner learn in STM32F103R8T6 process, usually to need program emulator to be burnt in ROM, due to the needs of debugging, keep away and unavoidably ROM is repeatedly wiped, ROM loss problem.This product has done to improve and Starting mode can have been arranged by the selection of jumper cap the erasable number of times that three kinds of modes greatly can alleviate ROM in sheet when jumper cap selection starts from RAM in Starting mode, to reduce the loss to ROM, make to download easier with on-line debugging.STM32F103R8T6 minimum system learning board comprises MCU main control chip, CAN interface, JTAG downloads in-circuit emulation interface, USB power supply interface, DC-2.0 power supply interface, 3.3V, 5V power expansion interface, RTC Real Time Clock battery power supply, power light, program run indicator, reset key, user can expand according to demand voluntarily.Adopt rational layout that volume is reached to minimize simultaneously, make user easy to carry.The design is a practical STM32F103R8T6 minimum system learning board, and specific functional modules distribution as shown in drawings.
Description
Technical field
The utility model patent belongs to one block of single-chip minimum system plate involved by embedded system development lowermost layer field, is specially STM32F103R8T6 single-chip minimum system.
Background technology
In recent years, singlechip technology develop rapidly.At production and Technical Development Area, become an important developing instrument in electronic technology, automatic technology, computer technology, detection technique and the communication technology, market is very urgent to the demand being engaged in microcomputer development, this also has higher requirement to single chip computer teaching and practice, single-chip minimum system plate, to single-chip microcomputer beginner or microcomputer development personnel all tool be of great significance, utilize minimum system plate can carry out the expansion of peripheral circuit, programming thus realize SCM Based various application.Usually in single-chip microcomputer product development process, first must add that the peripheral circuit that user designs carries out mode in early stage with minimum system plate as mode object, need program emulator to be burnt in ROM, due to the needs of mode, keep away and unavoidably ROM is repeatedly wiped, cause ROM loss.
Utility model content
In order to solve the problem, Starting mode is set to three kinds of optional manner by the selection of jumper cap by this minimum system plate in Starting mode, when selecting the erasable number of times that greatly can alleviate ROM in sheet when starting from RAM, extends the minimum system learning board life-span.STM32F103R8T6 single-chip minimum system plate comprises, reset circuit, clock circuit, RTC feed circuit, power circuit, CAN communication circuit module.Form element reasonable layout each position at circuit board of these circuit.Its integrated level is high, compact conformation, facilitates user to carry.The all pins of STM32F103R8T6 single-chip microcomputer are all drawn to arrange pin, and provide 5V, 3.3V power extension, support SWD and JTAG two kinds of downloading modes simultaneously, facilitate user's regarded as output controlling.
Accompanying drawing explanation
Fig. 1 is 3.3V and 5V power supply the principle figure
Fig. 2 is MCU master control schematic diagram
Fig. 3 is Starting mode choosing principles figure
Fig. 4 is external connection row pin and the catenation principle figure of the corresponding pin position of corresponding MCU
Fig. 5 is CAN schematic diagram
Fig. 6 is that JTAG downloads mode interface
Fig. 7 is that PCB plate-making is drawn
Embodiment
STM32F103R8T6 single-chip minimum system plate it comprise PCB, feature PCB is installed with the double socket of STM32F103R8T6 single-chip microcomputer, VP230 CAN transceiving chip, Chip-R (R1, R2, R4, R3), patch capacitor (C1, C2, C3, C4, C5, C6, C7, C8, C9), 16 pin, the double socket of 6 pin, self-lock switch, USB female power interface, DC2.0 power interface, reset key, patch light-emitting diode, crystal oscillator, RTC powered battery base, 20pinJTAG download interface.
STM32F103R8T6 single-chip minimum system plate comprises:
Two kinds of power supply modes: USB power supply mode, DC-2.0 power supply mode, provide 5v to power, adopt ASM1117-3.3v step-down to become 3.3v to power (power supply mode connects anti-defencive function) to stm32.
Reset mode: electrification reset, button reset.
Starting mode: select three kinds of Starting mode BOOT1=x (arbitrary value) by jumping cap, BOOT0=0 starts from user's flash memory, and this is normal mode of operation.BOOT1=0 BOOT0=1 starts from system storage, and the program function that this pattern starts is arranged by producer.BOOT1=1 BOOT0=1 starts from built-in SRAM, and this pattern may be used for debugging.
Debud mode: 2 kinds of debud modes supported by minimum system plate, 20 pin JTAG artificial debuggings of standard and serial single line debugging (SWD).When chip real work not necessarily, native system adopts SWD interface to JTAG debugging interface.The jtag interface of standard needs 5 signal wires (TDO, TDI, TCK, NRST, TMS) and hardware reset RST signal.And serial line interface SWD only needs 1 clock cable (SWCLK) and 1 single data signal wire (SEDIO), not only increase debugging speed, decrease the use of GPIO, and save space and the wiring difficulty of PCB.The TCK of JTAG and tms signal share pin with SWCLK and SEDIO respectively, and one on TMS pin special burst is used for switching between JTAG and SWD.Native system adopts Keil μ Vi-sion4IDE development environment, after being set to SWD, can use SWD interface, without the need to exporting the burst of specifying on TMS when debugging is downloaded.
Communication mode: CAN communication, real-time, transmission range is comparatively far away, Anti-amyloid-β antibody ability is strong, low cost and other advantages to adopt CAN transceiver VP230 to have; Adopt two wire serial communication mode, error detecing capability is strong, can work in strong noise interference environment; Have right of priority and arbitration function, multiple control module is suspended on CAN-bus by CAN controller, forms many main frames localized network; Can determine receive or shield this message according to the ID of message; Reliable error handle and error-detection mechanism; The information sent can be retransmitted after being destroyed automatically; Node has the function automatically exiting bus when mistake is serious; Message does not comprise source address or destination address, only comes deixis information, precedence information by identifier.
RTC adopts independently button cell electric power system to power, and important information can be made not lose when system power supply accident power-off.
Break-make between self-lock switch is used for controlling being powered by USB female and DC-2.0 power supply interface and single-chip microcomputer, and re-power reset when single-chip microcomputer carries out download program.
Reset key is arranged on the edge of single-chip core core and is connected to the reset pin of single-chip microcomputer.
A PLC technology LED light lamp is connected to the PB0 pin of STM32F103R8T6, for completing program deixis when use STM32F103R8T6 minimum system plate.
The strong anti-interference performance of this minimum system plate has all added electric capacity at 3.3V power supply and 5V power supply and has carried out filtering.
The all GPIO mouths of this minimum system have external connection row pin, facilitate user to expand.
Claims (4)
1. a STM32F103R8T6 minimum system learning board, it comprises PCB, it is characterized in that described pcb board is installed with a slice STM32F103R8T6 singlechip chip, a slice VP230CAN transceiving chip, a slice ASM1117-3.3V power supply chip, four Chip-R (R1, R2, R4, R3), ten patch capacitor (C1, C2, C3, C4, C5, C6, C7, C8, C9), the double socket of four 16 pin, the double socket of four 6 pin, a self-lock switch, a USB female power interface, a DC2.0 power interface, a reset key, a patch light-emitting diode, a 8M crystal oscillator, a 32.768kHZ crystal oscillator, R TC powered battery base, a 20pinJTAG download interface, a CAN interface.
2. the STM32F103R8T6 minimum system learning board according to claims 1, it is characterized in that it is provided with Starting mode and selects, Starting mode can be set to three kinds of modes by the selection of jumper cap: user's flash memory starts, system storage starts, starts from built-in SRAM.
3. the STM32F103R8T6 minimum system learning board according to claims 1, is characterized in that it is provided with the function of CAN communication, is provided with CAN interface, supports SWD and JTAG two kinds of downloading modes, facilitates user's mode to extend the minimum system learning board life-span.
4. the STM32F103R8T6 minimum system learning board according to claims 1, it is characterized in that its volume is little, convenience is strong, the all of the port of STM32F103R8T6 can be drawn by Du Pont's line simultaneously, user can arbitrarily expand, it is provided with program and runs deixis, can be tested the quality of minimum system plate by light emitting diode D2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN201420656197.XU CN204270060U (en) | 2014-11-06 | 2014-11-06 | STM32F103R8T6 single-chip minimum system plate |
Applications Claiming Priority (1)
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CN201420656197.XU CN204270060U (en) | 2014-11-06 | 2014-11-06 | STM32F103R8T6 single-chip minimum system plate |
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CN204270060U true CN204270060U (en) | 2015-04-15 |
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CN201420656197.XU Expired - Fee Related CN204270060U (en) | 2014-11-06 | 2014-11-06 | STM32F103R8T6 single-chip minimum system plate |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104914767A (en) * | 2015-06-17 | 2015-09-16 | 北京微控工业网关技术有限公司 | Electronic smart jumper device |
-
2014
- 2014-11-06 CN CN201420656197.XU patent/CN204270060U/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104914767A (en) * | 2015-06-17 | 2015-09-16 | 北京微控工业网关技术有限公司 | Electronic smart jumper device |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150415 Termination date: 20151106 |
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EXPY | Termination of patent right or utility model |