CN216210581U

CN216210581U - DP interface awakens receiving equipment's circuit up

Info

Publication number: CN216210581U
Application number: CN202122547627.7U
Authority: CN
Inventors: 王颜飞; 丁敏杰; 吴子明
Original assignee: Shenzhen Weishiteng Technology Co ltd
Current assignee: Shenzhen Weishiteng Technology Co ltd
Priority date: 2021-10-21
Filing date: 2021-10-21
Publication date: 2022-04-05
Anticipated expiration: 2031-10-21

Abstract

The utility model relates to a circuit for awakening receiving equipment by a DP interface, which comprises the DP interface, a detection judgment feedback module and a CPU, wherein the detection judgment feedback module is arranged between the DP interface and the CPU, an audio signal of the DP interface is input into the detection judgment feedback module, the detection judgment feedback module outputs a voltage signal which can be identified by the CPU, the detection judgment feedback module comprises a signal input end, a signal output end, a first switch tube, a second switch tube, a power supply and two divider resistors, the signal input end is connected with and controls the on-off of the first switch tube, the first switch tube is connected with the second switch tube and the power supply and controls the on-off of the second switch tube, and when the second switch tube is connected, the signal output end outputs the voltage signal to the CPU, so that the receiving equipment is awakened or a signal channel is switched. The utility model can execute the function of awakening or signal source jumping when the DP interface has signal access under the standby condition of the receiving equipment without additional remote control operation.

Description

DP interface awakens receiving equipment's circuit up

Technical Field

The utility model relates to the field of circuits, in particular to a circuit for waking up a receiving device by a DP interface.

Background

At present, receiving devices supporting a DP interface in the market, such as an extended display, a television, an advertisement machine, an education machine, or a conference machine, mostly need to be wakened up by a remote controller under a standby condition, or switch signal channels by using modes such as an intelligent remote control, and the like, and the starting mode is not fast and convenient enough.

The above problems are worth solving.

Disclosure of Invention

To overcome the problems of the prior art, the present invention provides a circuit for waking up a receiving device by a DP interface.

The technical scheme of the utility model is as follows:

a circuit for awakening receiving equipment by a DP interface is characterized by comprising the DP interface, a detection judgment feedback module and a CPU, wherein the detection judgment feedback module is arranged between the DP interface and the CPU, an audio signal of the DP interface is input into the detection judgment feedback module, the detection judgment feedback module outputs a voltage signal which can be identified by the CPU,

the detection judgment feedback module comprises a signal input end, a signal output end, a first switch tube, a second switch tube, a power supply and two divider resistors, wherein the signal input end is connected with the first switch tube and controls the on-off of the first switch tube, the first switch tube is connected with the second switch tube and the power supply and controls the on-off of the second switch tube, the second switch tube is connected with the signal output end through the divider resistors, and when the second switch tube is switched on, the CPU obtains a voltage signal and outputs a wake-up signal or a channel switching signal.

The utility model according to the above scheme is characterized in that the second switching tube is a second MOS tube, a source of the second MOS tube is connected to the power supply, a gate of the second MOS tube is connected to the first switching tube, a resistor is connected between the source and the gate, and a drain of the second MOS tube is connected to the voltage dividing resistor.

Furthermore, the first switch tube is a triode, the base of the triode is connected with the signal input end, the collector of the triode is connected with the grid of the second MOS tube, and the emitter of the triode is grounded.

Furthermore, a current limiting resistor is connected between the base electrode of the triode and the signal input end.

Furthermore, the first switch tube is a first MOS tube, a gate of the first MOS tube is connected to the signal input end, a source of the first MOS tube is connected to a gate of the second MOS tube, and a drain of the first MOS tube is grounded.

Furthermore, a current-limiting resistor is connected between the grid of the first MOS tube and the signal input end.

The utility model according to the above scheme is characterized in that the input end of the first switching tube is connected with a pull-down resistor, and the other end of the pull-down resistor is grounded.

The utility model according to the above scheme is characterized in that the voltage dividing resistor includes a first voltage dividing resistor and a second voltage dividing resistor, one end of the first voltage dividing resistor is connected to the second switching tube, the other end of the first voltage dividing resistor is connected to the signal output end, one end of the second voltage dividing resistor is connected to the signal output end, and the other end of the second voltage dividing resistor is grounded.

The utility model according to the scheme has the advantages that:

the utility model can analyze and judge the AUX channel signal in the DP interface, and convert the change of the AUX signal into a voltage signal which can be picked up by a CPU and changes from low to high, thereby realizing the function of awakening or signal source jumping when the DP interface has signal access under the standby condition of receiving equipment, and needing no additional hardware switch, wireless remote control or other intelligent remote control and other modes of operation; the hardware circuit module of the utility model is simple, easy to transplant and beneficial to popularization and use.

Drawings

FIG. 1 is a block diagram of the present invention;

FIG. 2 is a circuit diagram of a detection and judgment feedback module according to the first embodiment;

fig. 3 is a circuit diagram of a detection and judgment feedback module in the second embodiment.

Detailed Description

For better understanding of the objects, technical solutions and effects of the present invention, the present invention will be further explained with reference to the accompanying drawings and examples. Meanwhile, the following described examples are only for explaining the present invention, and are not intended to limit the present invention.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or intervening elements may also be present, and when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

The terms "first", "second" and "first" are used merely for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features.

As shown in fig. 1 and 2, a DP interface wakens up circuit of a receiving device, including a DP interface, a detection and judgment feedback module and a CPU, the detection and judgment feedback module is disposed between the DP interface and the CPU, an audio signal of the DP interface is input into the detection and judgment feedback module, the detection and judgment feedback module outputs a voltage signal recognizable to the CPU, the detection and judgment feedback module includes a signal input end, a signal output end, a first switch tube, a second switch tube, a power supply VCC _ STB and two voltage dividing resistors R4 and R5, the signal input end is connected to the first switch tube and controls the on-off of the first switch tube, the first switch tube is connected to the second switch tube and the power supply and controls the on-off of the second switch tube, the second switch tube is connected to the signal output end through the voltage dividing resistor, when the second switch tube is turned on, the CPU obtains the voltage signal and outputs a wakening up signal or a channel switching signal.

In the utility model, a signal input end of a detection judgment feedback module is connected with a DP interface to obtain an AUX audio signal of the DP interface; the signal output end is connected with a CPU in the receiving equipment, the CPU comprises a power supply management module, the CPU can output a wake-up signal to start the power supply management module, an IO port of the power supply management module is controllable when the receiving equipment is in standby, and when the CPU outputs the wake-up signal, the receiving equipment is started; or the CPU outputs a channel switching signal, and the receiving equipment executes signal source jumping.

In the utility model, the input end of the first switch tube is connected with a pull-down resistor R1, the other end of the pull-down resistor R1 is grounded, the second switch tube is a second MOS tube Q2, the source electrode of the second MOS tube Q2 is connected with a power supply VCC _ STB, the grid electrode of the second MOS tube Q2 is connected with the first switch tube, a resistor R3 is connected between the source electrode and the grid electrode, and the drain electrode of the second MOS tube Q2 is connected with a divider resistor.

IN this embodiment, the voltage dividing resistor includes a first voltage dividing resistor R4 and a second voltage dividing resistor R5, one end of the first voltage dividing resistor R4 is connected to the second switching tube, specifically, one end of the first voltage dividing resistor R4 is connected to the drain of the second MOS transistor Q2, the other end is connected to the signal output terminal (DP _ IN _ DETECT), one end of the second voltage dividing resistor R5 is connected to the signal output terminal (DP _ IN _ DETECT), and the other end is grounded.

In an alternative embodiment, as shown in fig. 2, the first switch transistor is a transistor Q1, the base of the transistor Q1 is connected to the signal input terminal (DP _ AUX _ P/N), the collector of the transistor Q1 is connected to the gate of the second MOS transistor Q2, and the emitter of the transistor Q1 is grounded. And a current-limiting resistor R2 is connected between the base of the triode Q1 and the signal input end (DP _ AUX _ P/N).

When signal source equipment accessed by the DP interface works, a control signal is sent, and an audio channel signal in the DP interface has direct-current bias voltage. If the DP interface signal source equipment does not work or the DP interface is not connected to the working signal source equipment, the level of an audio channel signal in the DP interface is 0; the logic of the signal input end (DP _ AUX _ P/N) is low, the voltage on the pull-down resistor R1 is 0, the triode Q1 is in an off state, and the second MOS transistor Q2 is in an off state; the divided voltage across the voltage dividing resistors R4 and R5 is 0, i.e., logic low.

When signal source equipment connected with a DP interface is started up and works, after a voltage larger than 0.7V appears at a signal input end (DP _ AUX _ P/N), a current limiting resistor R2 performs a current limiting function, a triode Q1 is conducted, due to the action of a resistor R3, the driving voltage of a second MOS tube Q2 reaches an on threshold, the second MOS tube Q2 is conducted, the voltage at the upper end of a voltage dividing resistor R4 is equal to a power supply VCC _ STB, the voltage of a signal output end (DP _ IN _ DETECT) is obtained through voltage division of two voltage dividing resistors R4 and R5, the voltage of the signal output end (DP _ IN _ DETECT) is 3.3V, the signal output end (DP _ IN _ DET) changes from 0 to 3.3V, and the CPU receives a jump level and feeds back the jump level to an IO port of a power management module of the CPU, so that the receiving equipment starts up or executes the jump signal source.

As shown in fig. 3, in an alternative embodiment, the first switch transistor is a first MOS transistor Q3, the gate of the first MOS transistor Q3 is connected to the signal input terminal (DP _ AUX _ P/N), the source of the first MOS transistor Q3 is connected to the gate of the second MOS transistor Q2, and the drain of the first MOS transistor Q3 is grounded. The current limiting resistor R2 is connected between the gate of the first MOS transistor Q3 and the signal input end (DP _ AUX _ P/N).

Therefore, the utility model converts the bias voltage of the AUX in the DP interface during working into a level change, and feeds back the level change to the CPU, so that the utility model can be used for judging whether the signal source equipment connected to the DP interface is in a working state.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the utility model. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A circuit for awakening receiving equipment by a DP interface is characterized by comprising the DP interface, a detection judgment feedback module and a CPU, wherein the detection judgment feedback module is arranged between the DP interface and the CPU, an audio signal of the DP interface is input into the detection judgment feedback module, the detection judgment feedback module outputs a voltage signal which can be identified by the CPU,

2. The circuit according to claim 1, wherein the second switching transistor is a second MOS transistor, a source of the second MOS transistor is connected to the power supply, a gate of the second MOS transistor is connected to the first switching transistor, a resistor is connected between the source and the gate of the second MOS transistor, and a drain of the second MOS transistor is connected to the voltage divider resistor.

3. The circuit of claim 2, wherein the first switch tube is a triode, a base of the triode is connected to the signal input end, a collector of the triode is connected to a gate of the second MOS tube, and an emitter of the triode is grounded.

4. The DP interface wake-up receiving device circuit of claim 3, wherein a current-limiting resistor is connected between the base of the triode and the signal input terminal.

5. The circuit of claim 2, wherein the first switch transistor is a first MOS transistor, a gate of the first MOS transistor is connected to the signal input terminal, a source of the first MOS transistor is connected to a gate of the second MOS transistor, and a drain of the first MOS transistor is grounded.

6. The circuit according to claim 5, wherein a current limiting resistor is connected between the gate of the first MOS transistor and the signal input terminal.

7. The circuit according to claim 1, wherein an input terminal of the first switch tube is connected to a pull-down resistor, and another terminal of the pull-down resistor is grounded.

8. The circuit for waking up a receiving device by a DP interface according to claim 1 or 2, wherein said voltage dividing resistor comprises a first voltage dividing resistor and a second voltage dividing resistor, one end of said first voltage dividing resistor is connected to said second switch tube, the other end of said first voltage dividing resistor is connected to said signal output end, one end of said second voltage dividing resistor is connected to said signal output end, and the other end of said second voltage dividing resistor is connected to ground.