CN216086468U

CN216086468U - Grid circuit applied to NMOS (N-channel metal oxide semiconductor) tube, switching power supply circuit and charger

Info

Publication number: CN216086468U
Application number: CN202121919200.9U
Authority: CN
Inventors: 方洪福
Original assignee: Shenzhen Sirius Semiconductor Co ltd
Current assignee: Shenzhen Sirius Semiconductor Co ltd
Priority date: 2021-08-16
Filing date: 2021-08-16
Publication date: 2022-03-18
Anticipated expiration: 2031-08-16

Abstract

The application belongs to the technical field of power supplies, and provides a grid circuit, a switching power supply circuit and a charger applied to an NMOS (N-channel metal oxide semiconductor) tube, wherein the grid circuit comprises a buffer module and a PNP (plug and play) triode module. The emitting electrode of the PNP triode module and the first end of the buffer module are connected to the grid electrode of the NMOS tube in common; the base of PNP triode module and the second end of buffering module connect altogether for receive drive signal, the collecting electrode ground connection of PNP triode module, thereby LC oscillation reduces the loss of opening of NMOS pipe when reducing the NMOS pipe through buffering module and opening, opens through the PNP triode when the NMOS pipe is closed and can discharge the voltage of NMOS pipe fast, reduces the loss of closing of NMOS pipe.

Description

Grid circuit applied to NMOS (N-channel metal oxide semiconductor) tube, switching power supply circuit and charger

Technical Field

The application belongs to the technical field of power supplies, and particularly relates to a grid circuit, a switching power supply circuit and a charger applied to an NMOS (N-channel metal oxide semiconductor) tube.

Background

At present, in the 3C digital field, a flyback switching power supply topology structure is generally adopted as a circuit structure of a charger with power less than or equal to 150W, the principle of the flyback switching power supply topology structure in the charger is that a primary high-voltage side of a transformer is connected with an NMOS tube, a drive circuit outputs a high level to enable a gate voltage of the NMOS tube to be increased to be greater than a critical starting voltage and then the NMOS tube is switched on, energy storage of the transformer is realized, a low level is output to enable the gate voltage of the NMOS tube to be released to be lower than the critical starting voltage and then the NMOS tube is switched off, and energy release of the transformer is realized.

However, since the primary coil voltage in the transformer circuit is high, the NMOS transistor connected thereto has a problem of large loss during the turn-on and turn-off processes.

SUMMERY OF THE UTILITY MODEL

The application aims to provide a grid circuit, a switching power supply circuit and a charger applied to an NMOS (N-channel metal oxide semiconductor) tube, and aims to solve the problem that the loss of an MOS tube connected with the transformer circuit is large in the process of starting and shutting down due to the high voltage of a primary coil in the transformer circuit.

In a first aspect, an embodiment of the present application provides a gate circuit applied to an NMOS transistor, where the gate circuit includes: the buffer module and the PNP triode module;

the emitting electrode of the PNP triode module and the first end of the buffer module are connected to the grid electrode of the NMOS tube in a sharing mode;

the base of the PNP triode module is connected with the second end of the buffer module in common and used for receiving a driving signal, and the collector of the PNP triode module is grounded.

In one embodiment, the NMOS transistor is a gallium nitride field effect transistor.

In one embodiment, the buffer module comprises at least one buffer resistor, wherein a first end of the at least one buffer resistor is connected with an emitter of the PNP transistor module, and a second end of the at least one buffer resistor is connected with a base of the PNP transistor module.

The second aspect of the present application also provides a switching power supply circuit, including: transformer circuit, NMOS pipe, current-limiting circuit and aforementioned any one the grid circuit, wherein:

the drain electrode of the NMOS tube is connected with the primary coil of the transformer circuit, the source electrode of the NMOS tube is connected with the first end of the current limiting circuit, and the grid electrode of the NMOS tube is connected with the grid electrode circuit;

the second end of the current limiting circuit is grounded.

In one embodiment, the switching power supply circuit further includes: the first rectifying and filtering circuit is connected with the primary coil of the transformer circuit;

the first rectifying and filtering circuit is used for accessing alternating current and rectifying and filtering the alternating current to generate direct current which is output to the transformer circuit

In one embodiment, the switching power supply circuit further includes: the second rectifying and filtering circuit is connected with the secondary coil of the transformer circuit;

and the second rectifying and filtering circuit is used for rectifying and filtering the direct current output by the transformer circuit.

In one embodiment, the switching power supply circuit further includes: and the driving circuit is connected with the grid circuit and used for sending a driving signal to the grid circuit.

In one embodiment, the transformer circuit comprises: the circuit comprises a first resistor, a first diode, a transformer and a first capacitor;

the first end of the first resistor and the first end of the first capacitor are connected to the first end of a primary coil of a transformer in a shared mode;

the second end of the first resistor and the second end of the first capacitor are connected to the cathode of a first diode in common;

the anode of the first diode and the second end of the primary coil of the transformer are connected to the drain of the NMOS tube in a shared mode.

In one embodiment, the current limiting circuit includes: and the first end of the second resistor is connected with the source electrode of the NMOS tube, and the second end of the second resistor is grounded.

The third aspect of the embodiments of the present application also provides a charger including the switching power supply circuit according to any one of the above embodiments.

The embodiment of the application provides a grid circuit, a switching power supply circuit and a charger applied to an NMOS (N-channel metal oxide semiconductor) tube, wherein the grid circuit comprises a buffer module and a PNP (plug and play) triode module. The emitting electrode of the PNP triode module and the first end of the buffer module are connected to the grid electrode of the NMOS tube in common; the base of PNP triode module and the second end of buffering module connect altogether for receive drive signal, the collecting electrode ground connection of PNP triode module, thereby LC oscillation reduces the loss of opening of NMOS pipe when reducing the NMOS pipe through buffering module and opening, opens through the PNP triode when the NMOS pipe is closed and can discharge the voltage of NMOS pipe fast, reduces the loss of closing of NMOS pipe.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a functional block diagram of a gate circuit applied to an NMOS transistor according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram illustrating a schematic circuit of a connection circuit between a buffer module and a PNP transistor according to an embodiment of the present disclosure;

fig. 3 is a functional block diagram of a switching power supply circuit according to an embodiment of the present application;

fig. 4 is a schematic connection diagram of a first rectifying and filtering circuit and a switching power supply circuit according to an embodiment of the present disclosure;

fig. 5 is a schematic connection diagram of a second rectifying and filtering circuit and a switching power supply circuit according to an embodiment of the present disclosure;

fig. 6 is a schematic connection diagram of a driving circuit and a switching power supply circuit according to an embodiment of the present disclosure;

fig. 7 is a schematic circuit diagram of a charger according to an embodiment of the present disclosure.

Reference numerals:

101: a buffer module; 102: a PNP triode module; 103: an NMOS tube; 104: a transformer circuit; 105: a current limiting resistor; 106: a first rectifying and filtering circuit; 107: a second rectifying and filtering circuit; 108: a drive circuit;

r1: a first resistor; c1: a first capacitor; d1: a first diode; r2: a second resistor; q: a PNP triode; re: a buffer resistor; BD: a rectifier bridge circuit; c2: a second capacitor; c3: a third capacitor; d2: a second diode.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the NMOS starting process, if the output of the driving circuit is directly connected with the grid electrode of the NMOS tube, the drain voltage can generate overhigh dv/dt when the NMOS tube is conducted, namely, under high frequency, because the junction capacitance between the drain electrode and the grid electrode is influenced by the Miller capacitance, the grid voltage is instantly pulled down to turn off the NMOS tube again, LC oscillation of the junction capacitance of the MOS tube and the parasitic inductance of the circuit board can be formed, the heating is caused to increase the loss in the starting process, and the output of the driving circuit can not be directly connected with the grid electrode of the NMOS tube.

In order to solve the above technical problem, an embodiment of the present application provides a gate circuit applied to an NMOS transistor, and fig. 1 is a functional block diagram of the gate circuit applied to the NMOS transistor provided in the embodiment of the present application, and with reference to fig. 1, the gate circuit in the embodiment includes a buffer module 101, a PNP triode module 102, and an NMOS transistor 103.

An emitter of the PNP triode module 102 and a first end of the buffer module 101 are connected to a gate of the NMOS transistor 103; the base of the PNP transistor module 102 is connected to the second end of the buffer module 101, and is configured to receive the driving signal, and the collector of the PNP transistor module 102 is grounded.

Specifically, in this embodiment, the PNP transistor module 102 includes at least one PNP transistor, and the PNP transistor is used to form a bleeding channel, and the buffer module 101 can properly reduce the turn-on speed of the NMOS transistor 103 to avoid generating oscillation and increasing loss.

Buffer module 101 and NMOS pipe 103 inherent input capacitance constitute RC charge-discharge circuit, and its discharge time can increase MOS pipe shutoff process time, and after buffer module 101 parallelly connected PNP triode module 102, the NMOS pipe 103 was turn-offed in the twinkling of an eye, and buffer module 101's first end and second end can form pressure differential, make PNP triode module 102's emitting electrode and collecting electrode switch on to accelerate NMOS pipe 103's voltage to bleed, loss when reducing NMOS pipe 103 and turn-offeing.

In the turn-off process of the NMOS transistor 103, the faster the gate voltage is discharged, the smaller the turn-off process loss is. The fastest way to turn off the NMOS 103 is to short its gate to source (e.g., by shorting the gate to common ground). However, as described above, the driving circuit 108 outputs a low level (e.g., a level of common ground) to control the NMOS transistor 103 to turn off, and the output cannot be directly connected to the gate of the NMOS transistor 103.

Because of the characteristics of high power of the gallium nitride fast charger and low turn-on voltage of the gallium nitride MOS transistor, a higher requirement is put forward for reducing the loss of the high-voltage NMOS transistor 103, in this embodiment, the buffer module 101 and the PNP triode module 102 are combined to form a passive control gate circuit, so that the problem that when an NPN triode Q is adopted, the base of the NPN triode Q needs to be connected with a high level to conduct the NPN triode Q, thereby causing the need of additionally increasing a circuit for outputting the high level.

In one embodiment, the PNP transistor module 102 is at least composed of a PNP transistor Q, and the rated current of the PNP transistor Q may be greater than 1A.

In one embodiment, the current flowing through the PNP transistor module 102 can be limited by connecting one or more current limiting resistors in series with the collector.

For example, referring to fig. 2, the PNP transistor module 102 may include a PNP transistor Q, a base of the PNP transistor Q and a first end of the buffer resistor Re are connected to the driving circuit 108 in common, an emitter of the PNP transistor Q and a second end of the buffer resistor Re are connected to a gate of the NMOS transistor 103, and a collector of the PNP transistor Q is grounded.

In one embodiment, the NMOS transistor 103 may be a gallium nitride field effect transistor.

The gallium nitride NMOS tube has low on-resistance and high switching speed under high withstand voltage, can be used as a high-voltage NMOS tube to be applied to an AC charger, can realize the miniaturization of the volume of the charger and the higher power, and is becoming the mainstream of the market. In the present embodiment, by providing the gate circuit in the above embodiment on the gate of the gan field effect transistor, the gan field effect transistor can be turned off quickly in a passive control manner, and the turn-off loss can be reduced as much as possible.

In one embodiment, the NMOS transistor 103 may have an on resistance of 160 milliohms, a breakdown voltage of 650 volts, and a threshold turn-on/turn-off voltage of 1 volt.

In one embodiment, the buffer module 101 includes at least one buffer resistor Re, a first terminal of the at least one buffer resistor Re is connected to the emitter of the PNP transistor module 102, and a second terminal of the at least one buffer resistor Re is connected to the base of the PNP transistor module 102.

In this embodiment, the buffer resistor Re in the buffer module 101 may be one or more, and if there are more, the buffer modules 101 may be formed by a plurality of buffer resistors in series, in parallel, or in a combination of series and parallel.

For example, a buffer resistor Re in the buffer module 101 is connected in parallel between the emitter and the base of a PNP transistor Q, the resistance of the buffer resistor Re is greater than 100 ohms, and the existence of the buffer resistor Re weakens the oscillation of the NMOS transistor 103 during the turn-on process, thereby reducing the loss of the NMOS transistor 103.

Fig. 3 is a functional block diagram of a switching power supply circuit according to an embodiment of the present disclosure, and shown in fig. 3, the switching power supply circuit includes a transformer circuit 104, an NMOS transistor 103, a current limiting circuit 105, a buffer module 101, and a PNP triode module 102.

The drain electrode of the NMOS tube 103 is connected with the third end of the transformer circuit 104, the source electrode of the NMOS tube 103 is connected with the first end of the current limiting circuit 105, and the grid electrode of the NMOS tube 103 is connected with the emitter electrode of the PNP triode module 102 and the second end of the buffer module 101; a first end of the transformer circuit 104 inputs high-voltage direct current, and a second end of the transformer circuit 104 outputs low-voltage direct current; a second terminal of the current limiting circuit 105 is connected to ground.

In one embodiment, referring to fig. 4, the switching power supply circuit further includes: the first rectifying and filtering circuit 106, the first filtering circuit 106 is used for accessing the alternating current, and rectifying and filtering the alternating current to generate direct current, and outputting the direct current to the transformer circuit 104.

In this embodiment, AC mains may be input to a first end of the first rectifying and filtering circuit 106, and the AC mains is rectified and filtered to be a direct current, and then the direct current is output from a second end of the first rectifying and filtering circuit 106.

For example, as shown in fig. 4 and fig. 7, a first terminal of the first filter circuit 106 inputs ac power, and a second terminal of the first filter circuit 106 is connected to a first terminal of the transformer circuit 104; the first filter circuit 106 includes a rectifier bridge circuit BD having a first side receiving a high-voltage ac power and a second side connected to the transformer circuit 104 together with the second capacitor C2, and a second capacitor C2.

In one embodiment, referring to fig. 5, the switching power supply circuit further includes: and the second rectifying and filtering circuit 107, the second rectifying and filtering circuit 107 is used for rectifying and filtering the direct current output by the transformer circuit 104.

In this embodiment, the first end of the second rectifying and filtering circuit 107 receives the low-voltage dc power transmitted from the transformer circuit 104, and outputs the dc power required by the load after rectification and filtering.

For example, referring to fig. 5 and 7, a first terminal of the second filter circuit 107 is connected to a second terminal of the transformer circuit, and a second terminal of the second rectifier filter circuit 107 outputs low-voltage direct current; the second rectifying and smoothing circuit 107 includes a second diode D2, a third capacitor C3, wherein an anode of the second diode D2 is connected to a first end of the secondary winding of the transformer T, and the third capacitor C3 is connected in parallel with the second diode D2 and a second end of the secondary winding of the transformer T.

In one embodiment, referring to fig. 6, the switching power supply circuit further includes a driving circuit 108, and the driving circuit 108 is connected to the gate circuit for sending a driving signal to the gate circuit.

In the embodiment, the driving chip in the driving circuit 108 is configured to receive the current signals from the first rectifying and filtering circuit 106, the transformer circuit 104, the second rectifying and filtering circuit 107 and the current limiting circuit 105, process the current signals, and then output a driving signal to control the NMOS transistor 103 to be turned on and off.

In this embodiment, the driving circuit 108 may output a driving signal to control the NMOS transistor 103 to turn on or off in a quasi-resonant control mode.

The quasi-resonance control mode refers to that after the energy of the primary coil of the transformer T is released, the primary inductor of the transformer T resonates with the junction capacitance of the NMOS tube 103, so that the voltage or current at the gate and drain ends of the NMOS tube 103 is in a sine wave change rule, and when the junction capacitance of the NMOS tube 103 discharges to the lowest, the NMOS tube 103 is turned on and conducted, thereby reducing the loss when the NMOS tube 103 is turned on and improving the efficiency of the NMOS tube 103.

In one embodiment, referring to fig. 7, the transformer circuit 104 includes a first resistor R1, a first diode D1, a transformer T, and a first capacitor C1.

A first end of the first resistor R1 and a first end of the first capacitor C1 are connected to a first end of a primary coil of the transformer T in a common mode; a second end of the first resistor R1 and a second end of the first capacitor C1 are connected in common to a cathode of a first diode D1; the anode of the first diode D1 and the second end of the primary winding of the transformer T are connected to the drain of the NMOS transistor 103.

In the embodiment, the transformer circuit 104 and the NMOS transistor 103 form a flyback topology, when the NMOS transistor 103 is turned on, the primary coil of the transformer T stores energy, and when the NMOS transistor 103 is turned off, the primary coil of the transformer T releases energy to the secondary coil of the transformer T.

In one embodiment, the current limiting circuit includes a second resistor R2, a first end of the second resistor R2 is connected to the source of the NMOS transistor 103, and a second end of the second resistor R2 is grounded.

In this embodiment, the resistance of the second resistor R2 may be determined according to the rated current of the NMOS transistor 103, and the second resistor R2 connected to the source of the NMOS transistor 103 can reduce the current passing through the NMOS transistor 103, thereby achieving the purpose of preventing the short circuit of the NMOS transistor 103.

Fig. 7 is a schematic circuit diagram of a charger according to an embodiment of the present application.

In this embodiment, the high-voltage ac is converted into a high-voltage dc by the first rectifying and filtering circuit 106, and when the driving circuit 108 outputs a high level, the voltage of the gate terminal of the NMOS transistor 103 rises to be greater than the critical turn-on voltage, and then the NMOS transistor 103 is turned on, so as to store energy in the primary coil of the transformer T; when the driving circuit 108 outputs a low level, the voltage at the gate terminal of the NMOS transistor 103 is discharged to a voltage lower than the critical turn-on voltage, and then the NMOS transistor 103 is turned off, so that the transformer T releases energy to the secondary coil of the transformer T, the secondary coil outputs a low-voltage direct current, and the low-voltage direct current passes through the second rectifying and filtering circuit 107 and then outputs a direct current required by a load.

In one embodiment, the power of the charger is less than or equal to 150 watts.

The buffer resistor Re in the buffer module 101 is connected with the gate terminal of the NMOS tube 103, so that the turn-on speed of the NMOS tube can be reduced, LC oscillation generated by junction capacitance of the NMOS tube 103 and parasitic inductance of a charger circuit can be avoided, and therefore, the buffer module 101 is added to reduce the turn-on speed of the NMOS tube 103, and accordingly loss of the NMOS tube 103 is reduced.

When the driving circuit 108 outputs a low voltage, the NMOS tube 103 is turned off, the faster the gate terminal voltage of the NMOS tube 103 is released, the smaller the loss in the turn-off process, and when the NMOS tube 103 is turned off, the capacitors in the buffer module 101 and the NMOS tube 103 form an RC discharge circuit and form a voltage difference with the low level of the driving circuit 108, and the PNP triode module 102 and the PNP triode module 101 are connected in parallel, so that the PNP triode module 102 can be turned on under the passive control condition, and the gate terminal voltage of the NMOS tube 103 can be released quickly.

Therefore, the switching power supply circuit optimizes the topological structure of the flyback switching power supply, reduces the oscillation of the NMOS tube 103 by adding the buffer module 101, reduces the loss of the NMOS tube when the NMOS tube is started, reduces the loss of the NMOS tube 103 when the NMOS tube is turned off by accelerating the turn-off time of the NMOS tube 103, and reduces the cost of the switching power supply circuit by adopting a mode of passively controlling the conduction of the PNP triode Q.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. A gate circuit applied to an NMOS transistor, the gate circuit comprising: the buffer module and the PNP triode module;

2. The gate circuit of claim 1, wherein the NMOS transistor is a gallium nitride field effect transistor.

3. The gate circuit of claim 1, wherein the snubber module comprises at least one snubber resistor, a first end of the at least one snubber resistor connected to the emitter of the PNP triode module and a second end of the at least one snubber resistor connected to the base of the PNP triode module.

4. A switching power supply circuit characterized by comprising: a transformer circuit, an NMOS transistor, a current limiting circuit, and a gate circuit of any one of claims 1-3, wherein:

the second end of the current limiting circuit is grounded.

5. The switching power supply circuit according to claim 4, wherein the switching power supply circuit further comprises: the first rectifying and filtering circuit is connected with the primary coil of the transformer circuit;

the first rectifying and filtering circuit is used for accessing alternating current and rectifying and filtering the alternating current to generate direct current and output the direct current to the transformer circuit.

6. The switching power supply circuit according to claim 4, wherein the switching power supply circuit further comprises: the second rectifying and filtering circuit is connected with the secondary coil of the transformer circuit;

7. The switching power supply circuit according to claim 4, wherein the switching power supply circuit further comprises: and the driving circuit is connected with the grid circuit and used for sending a driving signal to the grid circuit.

8. The switching power supply circuit according to any one of claims 4 to 6, wherein the transformer circuit includes: the circuit comprises a first resistor, a first diode, a transformer and a first capacitor;

the first end of the first resistor and the first end of the first capacitor are connected to the first end of the primary coil of the transformer in a shared mode;

the second end of the first resistor and the second end of the first capacitor are connected to the cathode of the first diode in a sharing mode;

9. The switching power supply circuit according to any one of claims 4 to 6, wherein the current limiting circuit includes: and the first end of the second resistor is connected with the source electrode of the NMOS tube, and the second end of the second resistor is grounded.

10. A charger, characterized in that it comprises a switching power supply circuit according to any one of claims 4-9.