CN215990261U

CN215990261U - Reduce precharge circuit that surge strikes

Info

Publication number: CN215990261U
Application number: CN202122014921.1U
Authority: CN
Inventors: 施海謇; 刘瑜; 龚士权; 陈功义
Original assignee: New Focus Lighting and Power Technology Shanghai Co Ltd
Current assignee: New Focus Lighting and Power Technology Shanghai Co Ltd
Priority date: 2021-08-25
Filing date: 2021-08-25
Publication date: 2022-03-08
Anticipated expiration: 2031-08-25

Abstract

The utility model relates to the technical field of inverters, in particular to a pre-charging circuit for reducing surge impact. A reduce precharge circuit that surge strikeed, includes the power, its characterized in that: the power supply positive electrode is respectively connected with one end of a resistor and one emitter of the triode, the other end of the resistor is respectively connected with a base electrode of the triode and one end of a resistor, a collector electrode of the triode is respectively connected with one-hundred-and-zero three anodes of the diode and one end of an eight resistor, one-hundred-and-zero three cathodes of the diode are respectively connected with one thirty end of the resistor and one twenty-eight end of the resistor, and the thirty end of the resistor and the twenty-eight end of the resistor are respectively connected with one eighty-five end of the resistor and one triodes collector electrode of the triode after being combined. Compared with the prior art, the problem of large current surge at the input end of the high-power inverter is solved, the impact and loss of the battery end are reduced, the charging stability is improved, the service life of the battery is prolonged, and the overcurrent protection of the lithium battery protection plate is avoided being triggered.

Description

Reduce precharge circuit that surge strikes

Technical Field

The utility model relates to the technical field of inverters, in particular to a pre-charging circuit for reducing surge impact.

Background

The high-frequency sine wave inverter organically combines a high-frequency switching power supply technology and an embedded microcomputer control technology, and realizes the high-frequency boosting conversion of direct-current input voltage of 12V/24V/48V/80V and the like into 110V/220V alternating-current sine output. Due to the need to reduce ripple at the input of the inverter, multiple electrolytic capacitors are typically wired in parallel across the input clamp. In the actual use process at present, the larger the output power of the product is, the larger the generated current of the input end is, the more electrolytic capacitors connected in parallel with the input end are generally selected, and the larger the capacitance value is. However, due to the inherent characteristics of the electrolytic capacitor, the product of the capacitance value C and the equivalent resistance R is generally a fixed value, so that the larger the capacitance value of the input electrolytic capacitor is, the smaller the equivalent resistance is. The problem of small equivalent resistance can cause that when the clamp line at the input end of the inverter is electrified, larger current surge can be generated when the clamp line is directly connected; the higher the input voltage, the more severe the input surge. The battery, especially the lithium battery, may be damaged to some extent, and sometimes even the overcurrent protection function of protecting the lithium battery protection board may be triggered.

At present, the common practice for solving the input surge is to connect a plurality of electrolytic capacitors in parallel at the input end of the battery, but when a higher voltage is directly injected into the electrolytic capacitor with a lower voltage, the current is limited by the equivalent resistance ESR of the electrolytic capacitors. However, as the output power increases, the more input capacitance is increased, resulting in a smaller equivalent resistance ESR and a weaker surge limiting capability.

Disclosure of Invention

The utility model provides a pre-charging circuit for reducing surge impact, which overcomes the defects of the prior art, solves the problem of large current surge at the input end of a high-power inverter, reduces impact and loss on a battery end, improves charging stability, prolongs the service life of the battery, and avoids triggering over-current protection of a lithium battery protection board.

In order to achieve the above object, a pre-charging circuit for reducing surge impact is provided, which includes a power supply, and is characterized in that: the power supply positive electrode is respectively connected with one end of a resistor and one emitter of a triode, the other end of the resistor is respectively connected with a base electrode of the triode and one end of a resistor, a collector electrode of the triode is respectively connected with a one-hundred-three anode of a diode and one end of an eight-resistor, a one-hundred-three cathode of the diode is respectively connected with one end of a resistor thirty and one end of a resistor twenty-eight, the other ends of the resistor thirty-eight and the resistor twenty-eight are respectively connected with one end of a resistor eighty-five and a collector electrode of the triode after being combined, the other end of the resistor eighty-five is respectively connected with a three base electrode of the triode and a three cathode of the diode, a three emitter electrode of the triode is connected with one end of a capacitor two, the other end of the capacitor is grounded, the anode of the diode is grounded, the other end of the resistor eight is connected with one end of a resistor twelve, the other end of the resistor twelve is respectively connected with one end of a twenty-seven gate electrode of a field effect tube, the eighteen source electrode of the field effect tube is respectively connected with the other end of the resistor twenty-seven, the resistor, A field effect tube three source electrode, a field effect tube four source electrode, a field effect tube seven source electrode, a field effect tube one source electrode, a resistor two end, a test point and a power ground, wherein an eighteen drain electrode of the field effect tube is connected with a resistor twenty six end, the other twenty six end is merged with the three drain electrode of the field effect tube, the four drain electrode of the field effect tube, the seven drain electrode of the field effect tube and the one drain electrode of the field effect tube and then grounded, a field effect tube three gate electrode is connected with the resistor six end, a field effect tube four gate electrode is connected with the resistor four end, a field effect tube seven gate electrode is connected with the resistor seven end, the one gate electrode of the field effect tube is connected with a resistor fifteen end, the other end of the resistor seven end, the other end of the resistor four end and the other end of the resistor six end are merged and then connected with an emitter electrode of an optical coupling eight receiving end, a collector electrode of the optical coupling end is connected with a +12V power supply, a cathode of the optical coupling eight transmitting end is grounded, an anode of the optical coupling end is connected with a resistor thirty two, the other end of the resistor five is connected with one end of a resistor three, the other end of the resistor three is connected with a collector of a triode two, an emitter of the triode two is respectively connected with one end of a resistor eleven and a power ground, the other end of the resistor eleven is respectively connected with a base of the triode two and one end of a resistor twenty nine, the other end of the resistor twenty nine is connected with a collector of a seven-receiving end of the optocoupler, an emitter of the seven-receiving end of the optocoupler is connected with the power ground, a cathode of the seven-emitting end of the optocoupler is connected with one-hundred-eight end of the resistor, the other end of the one-hundred-eight resistor is connected with a +15V power supply, and an anode of the seven-emitting end of the optocoupler is connected with a ground wire.

The model of the triode I is A92.

The type of the diode is ES1G one hundred and three.

The model of the triode II is A42.

The type of the triode III is KSC 2881.

The eighteen type field effect transistors are FQD10N 20.

The types of the optocouplers eight and seven are EL 817.

The eighteen field effect transistors are replaced by darlington transistors.

And the optical coupler eight and the optical coupler seven are replaced by a relay.

Compared with the prior art, the utility model solves the problem of large current surge at the input end of the high-power inverter, reduces the impact and loss on the battery end, improves the charging stability, prolongs the service life of the battery and avoids triggering the overcurrent protection of the lithium battery protection board.

Drawings

FIG. 1 is a circuit diagram of the present invention.

FIG. 2 is a block diagram of a circuit used in an embodiment of the present invention.

Referring to fig. 1 to 2, 1 is an external direct current power supply, 2 is a precharge circuit, 3 is an inverter control circuit, 4 is an inverter operation circuit, and 5 is an alternating current.

Detailed Description

The utility model is further illustrated below with reference to the accompanying drawings.

The first embodiment is as follows:

as shown in fig. 1, the positive +80V of the power supply is connected to one end of a resistor-R1 and an emitter of a transistor-P1, the other end of the resistor-R1 is connected to a base of a transistor-P1 and one end of a resistor-five R5, a collector of a transistor-P1 is connected to an anode of a diode-one-hundred-three D103 and one end of a resistor-eight R8, a cathode of the diode-one-hundred-three D103 is connected to one end of a resistor-thirty R30 and one end of a resistor-twenty-eight R28, a resistor-thirty-R30 and the other end of the resistor-twenty-eight R28 are combined and then connected to one end of a resistor-eighty-five R85 and a collector of a transistor-three N3, the other end of the resistor-fifteen R85 is connected to a base of a transistor-three N3 and a cathode of a diode-Z3, an emitter of the transistor-three-N3 is connected to one end of a capacitor-two-C2, the other end of a capacitor-C2 is grounded, an anode of a diode-Z3 is grounded, the other end of the resistor-eight-R8 is connected to one end of a resistor-twelve R12, and the other end of a resistor-twelve-R12 is connected to one end of a resistor-seven-R27, An eighteen Q18 gate of the field effect transistor, an eighteen Q18 source of the field effect transistor is respectively connected with the other end of the twenty-seven R27 resistor, a three Q3 source of the field effect transistor, a four Q4 source of the field effect transistor, a seven Q7 source of the field effect transistor, a one Q1 source of the field effect transistor, one end of the two R2 resistor, the SIP1 test point, the 80VGND power supply, an eighteen Q18 drain of the field effect transistor is connected with one end of the twenty-six R26 resistor, the other end of the twenty-six R26 resistor, a three Q3 drain of the field effect transistor, a four Q4 drain of the field effect transistor, a seven Q7 drain of the field effect transistor, and a one Q1 drain of the field effect transistor are merged and then grounded, a three Q1 gate of the field effect transistor is connected with one end of the six R1 resistor, a four Q1 gate of the field effect transistor is connected with one end of the four R1 gate of the resistor, a seventy Q1 resistor, a fifteen Q1 gate of the other end of the field effect transistor is connected with one Q1 resistor, a fifteen R1 gate of the other end of the field effect transistor is connected with one Q1 resistor, and a gate of the other end of the one Q1 resistor, The other end of the resistor six R6 is connected with an emitter of an opto-coupler eight O8 receiving end after being combined, a collector of an opto-coupler eight O8 receiving end is connected with a +12V power supply, a cathode of an emitting end of the opto-coupler eight O8 is grounded, an anode of the emitting end of the opto-coupler eight O8 is connected with a resistor thirty-two R32, the other end of the resistor five R5 is connected with one end of a resistor three R3, the other end of the resistor three R3 is connected with a collector of a triode two N1, an emitter of a triode two N1 is respectively connected with one end of a resistor ten R10 and a power ground 80VGND, the other end of the resistor ten R10 is respectively connected with a base of a triode two N1, one end of a resistor twenty-nine R29, the other end of the resistor twenty-nine R29 is connected with a collector of a receiving end of an optocoupler seven O7, an emitter of the receiving end of the optocoupler seven O7 is connected with a power ground 80VGND, a cathode of an emitting end of the optocoupler seven O7 is connected with one end of a resistor one-hundred-eight R108, the other end of the resistor one-hundred-eight R108 is connected with a +15V power supply, and an anode of the emitting end of the optocoupler seven O7 is connected with a ground wire LGND.

The model of the transistor I P1 is A92.

The diode one hundred three D103 is model ES 1G.

The model of the transistor II N1 is A42.

The model of the triode three N3 is KSC 2881.

The model of the field effect transistor eighteen Q18 is FOD10N 20.

The types of the optocoupler eight O8 and the optocoupler seven O7 are EL 817.

In the use of the present embodiment, as shown in fig. 2, the output terminal of the external dc power supply 1 is connected to the input terminal of the precharge circuit 2 of the present embodiment, the output terminal of the precharge circuit 2 is connected to the input terminal of the inverter control circuit 3 and the input terminal of the inverter operating circuit 4, respectively, the output terminal of the inverter control circuit 3 is connected to the input terminal of the inverter operating circuit 4, and the output terminal of the inverter operating circuit 4 outputs the ac power 5.

The inverter control circuit 3 and the inverter operating circuit 4 are circuits of the inverter itself.

When the POWER-on signal generating device is used, one end of the resistor thirty-two R32 is connected with the POWER pin of the single chip microcomputer, one end of the resistor twenty-nine R29 is connected with the EN pin of the single chip microcomputer, and the emitting electrode of the triode three N3 is connected with the PA6 pin of the single chip microcomputer to serve as a POWER-on signal. The model of the singlechip connected with the embodiment is ES7P 169C.

The pre-charging circuit 2 of the embodiment controls the on and off of the triode i P1 through an external +80V power supply and an EN pin of a single chip microcomputer, and finally controls the on and off of the field-effect transistor eighteen Q18, so that the resistor twenty-six R26 serving as a current-limiting resistor is smoothly connected in series into the inverter control circuit 3 and the inverter working circuit 4. At this time, the input power ground 80VGND and the internal ground GND are not directly connected, but a resistor twenty-six R26 is connected in series between the ground of the inverter control circuit 3, the inverter operating circuit 4, and the negative electrode of the external power source. Due to the presence of the resistor twenty-six R26, the maximum value of the current is limited within a controllable range even if the voltage difference between the capacitor and the input end of the inverter is large. For example, when the capacitor is powered on for the first time, the voltage of the capacitor is 0, the input voltage is 80V, and at this time, the resistance twenty-six R26 serving as the current limiting resistor is 120 Ω, the maximum current at the moment of power-on does not exceed (80-0)/120 = 0.75A. The charging curve of the electrolytic capacitor at the moment can be directly detected through an oscilloscope, and whether the charging time constant RC is proper or not is checked. And selecting a resistor twenty-six R26 with proper resistance and power as required. After the pre-charging is finished, the optocoupler seven O7 and the optocoupler eight O8 are conducted through a POWER pin of the single chip microcomputer, so that a POWER supply ground 80VGND of an external POWER supply and an internal GND are connected together, the short-circuit resistor twenty-six R026 enables the pre-charging circuit to be invalid, the inverter can work normally, and the phenomenon that the inverter is too large in loss and low in efficiency when working normally is avoided.

Example two:

this embodiment is only different from the first embodiment, and the description of the same parts will not be repeated.

The difference between this embodiment and the first embodiment is that, in this embodiment, the field effect transistor eighteen Q18 is replaced by a darlington transistor.

Example three:

The difference between this embodiment and the first embodiment is that in this embodiment, the optical coupler eight O8 and the optical coupler seven O7 are replaced by a relay.

Claims

1. A reduce precharge circuit that surge strikeed, includes the power, its characterized in that: the anode (+ 80V) of the power supply is respectively connected with one end of a first resistor (R1) and the emitter of a first triode (P1), the other end of the first resistor (R1) is respectively connected with the base of the first triode (P1) and one end of a fifth resistor (R5), the collector of the first triode (P1) is respectively connected with the anode of a diode one-hundred-three (D103) and one end of a resistor eight (R8), the cathode of the diode one-hundred-three (D103) is respectively connected with one end of a resistor thirty (R30) and one end of a resistor twenty-eight (R28), the other ends of the resistor thirty (R30) and the resistor twenty-eight (R28) are respectively connected with one end of a resistor eighty-five (R85) and the collector of a triode three (N3) after being combined, the other end of the resistor eighty-five (R85) is respectively connected with the base of the triode three (N3) and the cathode of a diode three (Z3), the emitter of the triode (N3) is connected with one end of a second capacitor (C2), the anode of the other end of the second capacitor (C2) is grounded, and the other end of the anode of the diode 3), the other end of the resistor eight (R8) is connected with one end of a resistor twelve (R12), the other end of the resistor twelve (R12) is respectively connected with one end of a resistor twenty-seven (R27) and a gate of a field-effect tube eighteen (Q18), the source of the field-effect tube eighteen (Q18) is respectively connected with the other end of the resistor twenty-seven (R27), the source of a field-effect tube three (Q3), the source of a field-effect tube four (Q4), the source of a field-effect tube seven (Q7), the source of a field-effect tube one (Q1), one end of a resistor two (R2), a test point (SIP 1) and a power ground (80 VGND), the drain of the field-effect tube eighteen (Q18) is connected with one end of a resistor twenty-six (R26), the other end of the resistor twenty-six (R26) is connected with the drain of the field-effect tube three (Q3), the drain of the field-effect tube four (Q4), the drain of the field-effect tube, the field-effect tube seven (Q7), the drain of the field-effect tube one (Q1) is grounded after being combined, the drain of the field-effect tube three (Q3) is connected with one end of the resistor six (R6), a gate of a field effect transistor IV (Q4) is connected with one end of a resistor IV (R4), a gate of a field effect transistor IV (Q7) is connected with one end of a resistor VII (R7), a gate of a field effect transistor I (Q1) is connected with one end of a resistor fifteen (R15), the other end of a resistor II (R2), the other end of a resistor fifteen (R15), the other end of a resistor VII (R7), the other end of a resistor IV (R4) and the other end of a resistor VI (R6) are combined and then connected with an emitter of a receiving end of an opto-coupler eight (O8), a collector of a receiving end of the opto-coupler eight (O8) is connected with a +12V power supply, a cathode of an emitting end of the opto-coupler eight (O8) is grounded, an anode of the transmitting end of the opto-coupler eight (O8) is connected with a resistor thirty-two (R32), the other end of a resistor V (R5) is connected with one end of a resistor III (R3), the other end of the resistor III (R3) is connected with a collector of a triode II (N1), and an emitter of a triode II (N1) is respectively connected with one end of a resistor VI (R10) and an ND 80) and an electric source ND 80, the other end of the resistor ten (R10) is connected with the base of the triode two (N1) and one end of the resistor twenty-nine (R29), the other end of the resistor twenty-nine (R29) is connected with the collector of the receiving end of the optocoupler seven (O7), the emitter of the receiving end of the optocoupler seven (O7) is connected with a power ground (80 VGND), the cathode of the emitting end of the optocoupler seven (O7) is connected with one end of the resistor one-hundred-eight (R108), the other end of the resistor one-hundred-eight (R108) is connected with a +15V power supply, and the anode of the emitting end of the optocoupler seven (O7) is connected with a ground wire (LGND).

2. A precharge circuit for reducing surge according to claim 1, wherein: the type of the triode I (P1) is A92.

3. A precharge circuit for reducing surge according to claim 1, wherein: the type of the diode one hundred and zero three (D103) is ES 1G.

4. A precharge circuit for reducing surge according to claim 1, wherein: the model of the triode II (N1) is A42.

5. A precharge circuit for reducing surge according to claim 1, wherein: the type of the triode III (N3) is KSC 2881.

6. A precharge circuit for reducing surge according to claim 1, wherein: the model of the field effect transistor eighteen (Q18) is FQD10N 20.

7. A precharge circuit for reducing surge according to claim 1, wherein: the types of the optocouplers eight (O8) and seven (O7) are EL 817.

8. A precharge circuit for reducing surge according to claim 1, wherein: eighteen (Q18) FETs are replaced by Darlington transistors.

9. A precharge circuit for reducing surge according to claim 1, wherein: the optical coupler eight (O8) and the optical coupler seven (O7) are replaced by a relay.