CN215988739U

CN215988739U - Conducting circuit structure for semiconductor chip package

Info

Publication number: CN215988739U
Application number: CN202122155581.4U
Authority: CN
Inventors: 林功艺
Original assignee: Wanhong Enterprise Co ltd
Current assignee: Wanhong Enterprise Co ltd
Priority date: 2021-09-07
Filing date: 2021-09-07
Publication date: 2022-03-08
Anticipated expiration: 2031-09-07

Abstract

A conductive circuit structure of semiconductor chip package is prepared as setting multiple seed crystal layers on a surface of a semiconductor chip and covering each corresponding pad, setting part of each seed crystal layer in each corresponding first groove to form at least one conductive circuit, controlling size, shape or thickness of conductive circuit structure more accurately by forming mode of seed crystal layer.

Description

Conducting circuit structure for semiconductor chip package

Technical Field

The present invention relates to a conductive circuit structure, and more particularly, to a conductive circuit structure for semiconductor chip package.

Background

In the field of semiconductor chip package structure technology, there are several prior arts such as taiwan patent No. 434848, "semiconductor chip device and its packaging method", and four additional patents including: disclosed in patents such as publication No. 466715 (addition one), publication No. 495933 (addition two), publication No. 466716 (addition three), publication No. 503534 (addition four), or I381503, and U.S. patent nos. US6,239,488, US5,990,546, US6,143,991, US6,075,712, US6,114,754, or US 2004/0232543. Recently developed and used semiconductor chip package structure belongs to a chip scale package type (chip scale package type), and various processes and structures have been derived, which can solve the problem of larger package size caused by TAB technology.

However, the method of forming the conductive trace structure in the technical features of patent I381503 still needs to be improved, in the technical features of patent I381503, the dielectric layer is formed first, then the groove structure is formed on the dielectric layer, and then the conductive trace is formed in the groove by chemical plating or electroplating. In addition, in the technical feature of patent I381503, a protection layer is provided on the surface of the pad structure, but the protection layer has the disadvantage of oxidation damage, and the problem of poor contact is easily generated after long-term use.

Therefore, a conductive trace structure of a semiconductor chip package, which can solve the problem that the size, shape or thickness of the conductive trace structure is easy to be controlled, and can avoid the problem of poor contact of the bonding pad due to the oxidation damage of the surface protection layer of the bonding pad in the prior art, is desired by the related industries.

SUMMERY OF THE UTILITY MODEL

The present invention provides a conductive circuit structure for semiconductor chip package, wherein the conductive circuit structure has a plurality of seed layers, each of the seed layers is correspondingly covered on a surface of a semiconductor chip and covers a corresponding pad, and a portion of each of the seed layers is disposed in a corresponding first groove to form at least one conductive circuit.

In order to achieve the above object, the present invention provides a conductive circuit structure of a semiconductor chip package, the semiconductor chip package is mounted on a substrate through the conductive circuit structure to be electrically connected to a plurality of pads disposed on the substrate, the conductive circuit structure includes a semiconductor chip, a plurality of first dielectric layers, a plurality of seed layers (seed layers), a plurality of conductive circuits and a plurality of second dielectric layers; wherein the semiconductor chip has a surface on which a plurality of bonding pads are disposed; wherein each first dielectric layer covers the surface of the semiconductor chip, and at least one first groove is formed on each first dielectric layer, and each first groove is used for exposing each welding pad of the semiconductor chip outwards; wherein each seed layer is correspondingly covered on the surface of the semiconductor wafer and covers each welding pad, and part of each seed layer is arranged in each first groove, wherein each seed layer is electrically connected with each welding pad of the semiconductor wafer; wherein each conductive line is correspondingly covered on each seed layer and covers each bonding pad of the semiconductor chip, and each conductive line fills each seed layer but the thickness of each conductive line does not exceed the coverage range of each seed layer on the semiconductor chip; wherein each conductive line is electrically connected with each seed layer, so that each conductive line can be electrically connected with each bonding pad of the semiconductor chip through each seed layer; the second dielectric layers are respectively and correspondingly arranged on the surfaces of the first dielectric layers and the conducting circuits in a covering manner, at least one second groove is formed on each second dielectric layer, and each second groove is used for exposing each conducting circuit outwards so that each conducting circuit can be electrically connected outwards, each crystal pad can be electrically connected outwards, the yield of products is improved, and the cost of manufacturing ends is reduced.

In another preferred embodiment of the present invention, each of the first dielectric layers and each of the second dielectric layers are formed by a spin coating (spin coating) process.

The present invention further provides a conductive circuit structure of a semiconductor chip package, the semiconductor chip package is mounted on a substrate through the conductive circuit structure to electrically connect to a plurality of pads disposed on the substrate, the conductive circuit structure includes a semiconductor chip, a plurality of first dielectric layers, a plurality of second dielectric layers, a plurality of seed layers (seed layers), a plurality of conductive circuits and a plurality of third dielectric layers; wherein the semiconductor chip has a surface on which a plurality of bonding pads are disposed; wherein each first dielectric layer covers the surface of the semiconductor chip, and at least one first groove is formed on each first dielectric layer, and each first groove is used for exposing each welding pad of the semiconductor chip outwards; wherein each second dielectric layer is covered on the surface of each first dielectric layer, at least one second groove is formed on each second dielectric layer, and each second groove is communicated with each first groove; wherein each seed layer is correspondingly arranged on the surface of the semiconductor wafer in a covering manner and covers each welding pad, and each seed layer is arranged in each first groove and each second groove, wherein each seed layer is electrically connected with each welding pad of the semiconductor wafer; wherein each conductive line is correspondingly covered on each seed layer and covers each bonding pad of the semiconductor chip, and each conductive line fills each seed layer but the thickness of each conductive line does not exceed the coverage range of each seed layer on the semiconductor chip; wherein each conductive line is electrically connected with each seed layer, so that each conductive line can be electrically connected with each bonding pad of the semiconductor chip through each seed layer; the third dielectric layers are respectively and correspondingly arranged on the surfaces of the second dielectric layers and the conducting circuits in a covering manner, at least one third groove is formed on each third dielectric layer, and each third groove is used for exposing each conducting circuit outwards so that each conducting circuit can be electrically connected outwards, and each conducting circuit can be electrically connected outwards, thereby being beneficial to improving the yield of products and reducing the cost of manufacturing ends.

In another preferred embodiment of the present invention, each of the first dielectric layers, each of the second dielectric layers and each of the third dielectric layers are formed by a spin coating (spin coating) process.

The present invention further provides a conductive circuit structure of a semiconductor chip package, the semiconductor chip package is mounted on a substrate through the conductive circuit structure to electrically connect to a plurality of pads disposed on the substrate, the conductive circuit structure includes a semiconductor chip, a plurality of first dielectric layers, a plurality of seed layers, a plurality of conductive circuits, a plurality of die pads, and a plurality of second dielectric layers; wherein the semiconductor chip has a surface on which a plurality of bonding pads are disposed; wherein each first dielectric layer covers the surface of the semiconductor chip, and at least one first groove is formed on each first dielectric layer, and each first groove is used for exposing each welding pad of the semiconductor chip outwards; wherein each seed layer is correspondingly covered on the surface of the semiconductor wafer and covers each welding pad, and each seed layer is arranged in each first groove, wherein each seed layer is electrically connected with each welding pad of the semiconductor wafer; wherein each conductive line is correspondingly covered on each seed layer, and each conductive line fills each seed layer but the thickness of each conductive line does not exceed the coverage range of each seed layer on the semiconductor wafer, wherein each conductive line is electrically connected with each seed layer, so that each conductive line can be electrically connected with each bonding pad of the semiconductor wafer through each seed layer; wherein each die pad is correspondingly arranged on the surface of each seed layer and each connecting line in a covering manner, each die pad covers each bonding pad, each seed layer and each connecting line of the semiconductor chip, and each die pad is electrically connected with each seed layer and each connecting line so that each connecting line can be electrically connected with each bonding pad of the semiconductor chip through each seed layer and each connecting line; the second dielectric layers are respectively and correspondingly arranged on the surfaces of the first dielectric layers and the crystal pads in a covering manner, at least one second groove is formed on each second dielectric layer, and each crystal pad is exposed outwards through each second groove, so that each crystal pad can be electrically connected outwards, the crystal pads can be electrically connected outwards, the yield of products is improved, and the cost of manufacturing ends is reduced.

Another objective of the present invention is to provide a conductive trace structure of a semiconductor chip package, wherein the semiconductor chip package is mounted on a substrate through the conductive trace structure to electrically connect to a plurality of pads disposed on the substrate, the conductive trace structure comprises a semiconductor chip, a plurality of first dielectric layers, a plurality of second dielectric layers, a plurality of seed layers (seed layers), a plurality of conductive traces, a plurality of die pads, and a plurality of third dielectric layers: wherein the semiconductor chip has a surface on which a plurality of bonding pads are disposed; wherein each first dielectric layer covers the surface of the semiconductor chip, and at least one first groove is formed on each first dielectric layer, and each first groove is used for exposing each welding pad of the semiconductor chip outwards; wherein each second dielectric layer covers the surface of each first dielectric layer, at least one second groove is formed on each second dielectric layer, and each second groove is communicated with each first groove; wherein each seed layer is correspondingly arranged on the surface of the semiconductor wafer in a covering manner and covers each welding pad, and each seed layer is arranged in each first groove and each second groove, wherein each seed layer is electrically connected with each welding pad of the semiconductor wafer; wherein each conductive line is correspondingly covered on each seed layer, and each conductive line fills each seed layer but the thickness of each conductive line does not exceed the coverage range of each seed layer on the semiconductor wafer, wherein each conductive line is electrically connected with each seed layer, so that each conductive line can be electrically connected with each bonding pad of the semiconductor wafer through each seed layer; wherein each die pad is correspondingly arranged on the surface of each seed layer and each connecting line in a covering manner, each die pad covers each bonding pad, each seed layer and each connecting line of the semiconductor chip, and each die pad is electrically connected with each seed layer and each connecting line, so that each die pad can be electrically connected with each bonding pad of the semiconductor chip through each seed layer and each connecting line; the third dielectric layers are respectively and correspondingly arranged on the surfaces of the second dielectric layers and the crystal pads in a covering manner, at least one third groove is formed on each third dielectric layer, each crystal pad is exposed outwards by each third groove, and each crystal pad can be electrically connected outwards, so that each crystal pad can be electrically connected outwards, the yield of products is improved, and the cost of manufacturing ends is reduced.

Drawings

Fig. 1 is a cross-sectional view of a fourth embodiment of the present invention and step S8 of the fourth embodiment of the present invention.

Fig. 2 is a schematic cross-sectional view of step S1 of the fourth embodiment of the present invention.

Fig. 3 is a schematic cross-sectional view of step S2 of the fourth embodiment of the present invention.

Fig. 4 is a schematic cross-sectional view of step S3 of the fourth embodiment of the present invention.

Fig. 5 is a schematic cross-sectional view of step S4 of the fourth embodiment of the present invention.

Fig. 6 is a schematic cross-sectional view of step S5 of the fourth embodiment of the present invention.

Fig. 7 is a schematic cross-sectional view of step S6 of the fourth embodiment of the present invention.

Fig. 8 is a schematic cross-sectional view of step S7 of the fourth embodiment of the present invention.

Fig. 9 is a cross-sectional view of the third embodiment of the present invention and step S7 of the third embodiment of the present invention.

Fig. 10 is a schematic cross-sectional view of step S1 of the third embodiment of the present invention.

Fig. 11 is a schematic cross-sectional view of step S2 of the third embodiment of the present invention.

Fig. 12 is a schematic cross-sectional view of step S3 of the third embodiment of the present invention.

Fig. 13 is a schematic cross-sectional view of step S4 of the third embodiment of the present invention.

Fig. 14 is a schematic cross-sectional view of step S5 of the third embodiment of the present invention.

Fig. 15 is a schematic cross-sectional view of step S6 of the third embodiment of the present invention.

Fig. 16 is a cross-sectional view of the second embodiment of the present invention and step S7 of the second embodiment of the present invention.

Fig. 17 is a schematic cross-sectional view of step S1 of the second embodiment of the present invention.

Fig. 18 is a schematic cross-sectional view of step S2 of the second embodiment of the present invention.

Fig. 19 is a schematic cross-sectional view of step S3 of the second embodiment of the present invention.

Fig. 20 is a schematic cross-sectional view of step S4 of the second embodiment of the present invention.

Fig. 21 is a schematic cross-sectional view of step S5 of the second embodiment of the present invention.

Fig. 22 is a schematic cross-sectional view of step S6 of the second embodiment of the present invention.

Fig. 23 is a cross-sectional view of the first embodiment of the present invention and step S6 of the first embodiment of the present invention.

Fig. 24 is a schematic cross-sectional view of step S1 of the first embodiment of the present invention.

Fig. 25 is a schematic cross-sectional view of step S2 of the first embodiment of the present invention.

Fig. 26 is a schematic cross-sectional view of step S3 of the first embodiment of the present invention.

Fig. 27 is a schematic cross-sectional view of step S4 of the first embodiment of the present invention.

Fig. 28 is a schematic cross-sectional view of step S5 of the first embodiment of the present invention.

List of reference numerals: 1-a conductive connection line structure; 1 a-a conductive line structure; 1 b-a conductive line structure; 1 c-a conductive line structure; 1 d-a conductive line structure; 10-a semiconductor wafer; 11-surface; 12-a bond pad; 20-a first dielectric layer; 21-a first groove; 30-a second dielectric layer; 31-a second groove; 40-a seed layer; 50-a conductive connection line; 60-a wafer pad; 70-a third dielectric layer; 71-a third groove; 80-welding points.

Detailed Description

The present invention is described in detail with reference to the drawings, wherein the drawings are only for illustrating the structural relationship and the related functions of the present invention, and the sizes of the elements in the drawings are not to be drawn to scale and are not to be construed as limiting the present invention.

Referring to fig. 1, 9, 16 and 23, the present invention provides a

conductive trace structure

1, 1a, 1b and 1c for semiconductor chip package and a method for manufacturing the same, so as to control the size, shape or thickness of the conductive trace structure more accurately, effectively solve the disadvantage that the conductive trace structure in the prior art is easy to control the size, shape or thickness, and further avoid the problem of poor contact of the pad or wire trace due to the oxidation damage of the protective layer on the surface thereof in the prior art, thereby improving the yield of the product and reducing the cost of the manufacturing end. According to the differences between the

lead wiring structures

1, 1a, 1b, 1c of the semiconductor chip package and the steps in the manufacturing method thereof, the present invention provides the following first, second, third and fourth embodiments:

the embodiment shown in fig. 23 to 28 is a first embodiment of the present invention, the semiconductor chip package is mounted on a substrate through the bonding wire structure 1a to electrically connect with a plurality of pads disposed on the substrate, the bonding wire structure 1a includes a plurality of first dielectric layers 20, a plurality of seed layers 40, a plurality of bonding wires 50 and a plurality of second dielectric layers 30.

The semiconductor chip 10 has a surface 11, and a plurality of bonding pads 12 are disposed on the surface 11 as shown in fig. 23.

As shown in fig. 23, each first dielectric layer 20 is disposed on the surface 11 of the semiconductor chip 10, and at least one first groove 21 is formed on each first dielectric layer 20, and each first groove 21 is used for exposing each bonding pad 12 of the semiconductor chip 10.

Each seed layer 40 is correspondingly disposed on the surface 11 of the semiconductor wafer 10 and covers each bonding pad 12 as shown in fig. 23, and each seed layer 40 is disposed in each first groove 21; wherein each seed layer 40 is electrically connected to each bonding pad 12 of the semiconductor chip 10.

Each conductive line 50 is correspondingly disposed on each seed layer 40 and covers each bonding pad 12 of the semiconductor wafer 10 as shown in fig. 9, and each conductive line 50 fills each seed layer 40 but has a thickness not exceeding the coverage of each seed layer 40 on the semiconductor wafer 10; wherein each conductive line 50 is electrically connected to each seed layer 40, so that each conductive line 50 can be electrically connected to each bonding pad 12 of the semiconductor chip 10 through each seed layer 40.

As shown in fig. 23, each of the second dielectric layers 30 is correspondingly disposed on the surfaces of each of the first dielectric layers 20 and each of the conductive traces 50, and at least one second groove 31 is formed on each of the second dielectric layers 30, each of the second grooves 31 exposes each of the conductive traces 50 to the outside, so that each of the conductive traces 50 can be electrically connected to the outside.

In addition, each of the first dielectric layer 20 and each of the second dielectric layer 30 are formed by a spin coating (spin coating) process, but not limited thereto.

The manufacturing method of the conductive circuit structure 1a includes the following steps:

step S1: a semiconductor chip 10 is provided, the semiconductor chip 10 has a surface 11, and a plurality of bonding pads 12 are disposed on the surface 11 as shown in fig. 24.

Step S2: as shown in fig. 25, a plurality of first dielectric layers 20 are formed on the surface 11 of the semiconductor chip 10, and at least one first groove 21 is formed on each first dielectric layer 20, and each first groove 21 is used for exposing each bonding pad 12 of the semiconductor chip 10.

Step S3: as shown in fig. 26, a plurality of seed layers (seed layers) 40 are correspondingly disposed on the surface 11 of the semiconductor wafer 10, each seed layer 40 corresponds to and covers each bonding pad 12, and each seed layer 40 is disposed on the surface of each first dielectric layer 20 and in each first groove 21, unlike the prior art in which a passivation layer is disposed on a bonding pad, which effectively avoids the problem of poor contact of the bonding pad due to oxidation damage of the passivation layer on the surface; wherein each seed layer 40 is electrically connected to each bonding pad 12 of the semiconductor chip 10.

Step S4: the unwanted portions of each seed layer 40 are removed as shown in fig. 27, and each seed layer 40 is polished or micro-embossed, but not limited to, such that each seed layer 40 is only located in each first groove 21.

Step S5: as shown in fig. 28, each of the conductive traces 50 is correspondingly disposed on each of the seed layers 40, and each of the conductive traces 50 covers each of the bonding pads 12 and each of the seed layers 40 of the semiconductor chip 10, which is different from the prior art that a conductive trace layer is formed first and then a solder is formed on the conductive trace layer, the first embodiment of the present invention can directly use each of the conductive traces 50 to replace the solder in the prior art, which is beneficial to reducing the manufacturing cost and reducing the overall thickness of the conductive trace structure; wherein each conductive line 50 is electrically connected to each seed layer 40, so that each conductive line 50 can be electrically connected to each bonding pad 12 of the semiconductor chip 10 through each seed layer 40.

Step S6: the second dielectric layers 30 are respectively and correspondingly disposed on the surfaces of the first dielectric layers 20 and the conductive traces 50, at least one second groove 31 is formed on each second dielectric layer 30, and each second groove 31 is used for exposing each conductive trace 50 outwards, as shown in fig. 23, so that each conductive trace 50 can be electrically connected outwards.

As shown in fig. 23, each of the conductive traces 50 further includes a hemispherical solder joint 80 for external electrical connection, but not limited thereto.

The embodiment shown in fig. 16 to 22 is a second embodiment of the present invention, the semiconductor chip package is mounted on a substrate through the bonding wire structure 1b to electrically connect with a plurality of pads disposed on the substrate, the bonding wire structure 1b includes a semiconductor chip 10, a plurality of first dielectric layers 20, a plurality of second dielectric layers 30, a plurality of seed layers 40, a plurality of bonding wires 50 and a plurality of third dielectric layers 70.

The semiconductor chip 10 has a surface 11, and a plurality of bonding pads 12 are disposed on the surface 11 as shown in fig. 16.

As shown in fig. 16, each first dielectric layer 20 is disposed on the surface 11 of the semiconductor chip 10, and at least one first groove 21 is formed on each first dielectric layer 20, and each first groove 21 is used for exposing each bonding pad 12 of the semiconductor chip 10.

As shown in fig. 16, each of the second dielectric layers 30 is disposed on the surface of each of the first dielectric layers 20, and at least one second groove 31 is formed on each of the second dielectric layers 30, and each of the second grooves 31 is communicated with each of the first grooves 21.

Each seed layer 40 is correspondingly disposed on the surface 11 of the semiconductor wafer 10 and covers each bonding pad 12 as shown in fig. 16, and each seed layer 40 is disposed in each first groove 21 and each second groove 31; wherein each seed layer 40 is electrically connected to each bonding pad 12 of the semiconductor chip 10.

As shown in fig. 16, each of the third dielectric layers 70 is correspondingly disposed on the surfaces of each of the second dielectric layers 30 and each of the conductive traces 50, and at least one third groove 71 is formed on each of the third dielectric layers 70, each of the third grooves 71 exposes each of the conductive traces 50 to the outside, so that each of the conductive traces 50 can be electrically connected to the outside.

In addition, each of the first dielectric layer 20, each of the second dielectric layer 30 and each of the third dielectric layer 70 are formed by a spin coating (spin coating) process, but not limited thereto.

The manufacturing method of the conductive circuit structure 1b comprises the following steps:

step S1: providing a semiconductor chip 10 as shown in fig. 17, the semiconductor chip 10 has a surface 11, and a plurality of bonding pads 12 are disposed on the surface 11.

Step S2: as shown in fig. 18, a plurality of first dielectric layers 20 are formed on the surface 11 of the semiconductor chip 10, at least one first groove 21 is formed on each first dielectric layer 20, and at least one first groove 21 is formed thereon, and each first groove 21 is used for exposing each bonding pad 12 of the semiconductor chip 10.

Step S3: as shown in fig. 19, a plurality of second dielectric layers 30 are disposed on each first dielectric layer 20, at least one second groove 31 is formed on each second dielectric layer 30, and each second groove 31 is communicated with each first groove 21.

Step S4: as shown in fig. 20, a plurality of seed layers (seed layers) 40 are correspondingly disposed on the surface 11 of the semiconductor chip 10, each seed layer 40 corresponds to and covers each bonding pad 12, and each seed layer 40 is disposed on the surface of each first dielectric layer 20, on the surface of each second dielectric layer 30, in each first groove 21 and each second groove 31, unlike the prior art in which a passivation layer is disposed on a bonding pad, which effectively avoids the problem of poor contact of the bonding pad due to the oxidation damage of the passivation layer on the surface thereof; wherein each seed layer 40 is electrically connected to each bonding pad 12 of the semiconductor chip 10.

Step S5: the unwanted portions of each seed layer 40 are removed as shown in fig. 21, and each seed layer 40 is polished or micro-embossed, but not limited thereto, and each seed layer 40 is only located in each first groove 21 and each second groove 31.

Step S6: a plurality of conductive traces 50 are correspondingly formed on the surface of each seed layer 40 as shown in fig. 22, and each conductive trace 50 covers each bonding pad 12 of the semiconductor wafer 10 and each seed layer 40, which is different from the prior art that a conductive trace layer is formed first and then a solder is formed on the conductive trace layer, the second embodiment of the present invention can directly use each conductive trace 50 to replace the solder in the prior art, which is beneficial to reducing the manufacturing cost and reducing the overall thickness of the conductive trace structure; wherein each conductive line 50 is electrically connected to each seed layer 40, so that each conductive line 50 can be electrically connected to each bonding pad 12 of the semiconductor chip 10 through each seed layer 40.

Step S7: as shown in fig. 16, each of the third dielectric layers 70 is correspondingly disposed on the surfaces of each of the second dielectric layers 30 and each of the conductive traces 50, at least one third groove 71 is formed on each of the third dielectric layers 70, and each of the third grooves 71 exposes each of the conductive traces 50 to the outside, so that each of the conductive traces 50 can be electrically connected to the outside.

As shown in fig. 16, each of the conductive traces 50 further includes a hemispherical solder joint 80 for external electrical connection, but not limited thereto.

The embodiment shown in fig. 9 to 15 is a third embodiment of the present invention, the semiconductor chip package is mounted on a substrate through the bonding wire structure 1c to electrically connect with a plurality of pads disposed on the substrate, the bonding wire structure 1c includes a semiconductor chip 10, a plurality of first dielectric layers 20, a plurality of seed layers (seed layers) 40, a plurality of bonding wires 50, a plurality of die pads 60 and a plurality of second dielectric layers 30.

The semiconductor chip 10 has a surface 11, and a plurality of bonding pads 12 are disposed on the surface 11 as shown in fig. 9.

As shown in fig. 9, each first dielectric layer 20 is disposed on the surface 11 of the semiconductor chip 10, and at least one first groove 21 is formed on each first dielectric layer 20, and each first groove 21 is used for exposing each bonding pad 12 of the semiconductor chip 10.

Each seed layer 40 is correspondingly disposed on the surface 11 of the semiconductor wafer 10 and covers each bonding pad 12 as shown in fig. 9, and each seed layer 40 is disposed in each first groove 21; wherein each seed layer 40 is electrically connected to each bonding pad 12 of the semiconductor chip 10.

Each conductive line 50 is correspondingly disposed on each seed layer 40 in a covering manner as shown in fig. 9, and each conductive line 50 fills each seed layer 40 but has a thickness not exceeding the coverage of each seed layer 40 on the semiconductor wafer 10; wherein each conductive line 50 is electrically connected to each seed layer 40, so that each conductive line 50 can be electrically connected to each bonding pad 12 of the semiconductor chip 10 through each seed layer 40.

Each of the die pads 60 is correspondingly disposed on the surface of each of the seed layers 40 and each of the conductive traces 50 as shown in fig. 9, and each of the die pads 60 covers each of the bonding pads 12, each of the seed layers 40 and each of the conductive traces 50 of the semiconductor chip 10; wherein each of the die pads 60 is electrically connected to each of the seed layers 40 and each of the conductive traces 50, so that each of the conductive traces 50 can be electrically connected to each of the bonding pads 12 of the semiconductor chip 10 through each of the seed layers 40 and each of the conductive traces 50.

As shown in fig. 9, each of the second dielectric layers 30 is correspondingly disposed on the surfaces of each of the first dielectric layers 20 and each of the die pads 60, and at least one second groove 31 is formed on each of the second dielectric layers 30, each of the second grooves 31 exposes each of the die pads 60 to the outside, so that each of the die pads 60 can be electrically connected to the outside.

The manufacturing method of the conductive circuit structure 1c includes the following steps:

step S1: as shown in fig. 10, a semiconductor chip 10 is provided, the semiconductor chip 10 has a surface 11, and a plurality of bonding pads 12 are disposed on the surface 11.

Step S2: as shown in fig. 11, a plurality of first dielectric layers 20 are formed on the surface 11 of the semiconductor chip 10, each first dielectric layer 20 has at least one first groove 21 formed thereon, and each first groove 21 is used for exposing each bonding pad 12 of the semiconductor chip 10.

Step S3: correspondingly covering a plurality of seed layers (seed layers) 40 on the surface 11 of the semiconductor wafer 10 as shown in fig. 12, wherein each seed layer 40 corresponds to and covers each bonding pad 12, and each seed layer 40 is disposed on the surface of each first dielectric layer 20 and in each first groove 21; wherein each seed layer 40 is electrically connected to each bonding pad 12 of the semiconductor chip 10.

Step S4: as shown in fig. 13, a plurality of conductive traces 50 are correspondingly disposed on each seed layer 40 in a covering manner, and each seed layer 40 is ground flat or ground into a micro-protrusion without limitation, and each first groove 21 is filled with each conductive trace 50, which is different from the prior art that a passivation layer is disposed on a bonding pad, thereby effectively avoiding the problem of poor contact of the bonding pad due to oxidation damage of the passivation layer on the surface of the bonding pad; wherein each conductive line 50 is electrically connected to each seed layer 40, so that each conductive line 50 can be electrically connected to each bonding pad 12 of the semiconductor chip 10 through each seed layer 40.

Step S5: as shown in fig. 14, unnecessary portions of each seed layer 40 and each bonding wire 50 are removed, so that the thickness of each bonding wire 50 does not exceed the coverage of each seed layer 40 on the semiconductor wafer 10, and each seed layer 40 is only located in each first groove 21.

Step S6: a plurality of die pads 60 are correspondingly disposed on the surfaces of the seed layers 40 and the bonding wires 50, as shown in fig. 15, and each die pad 60 covers each bonding pad 12, each seed layer 40 and each bonding wire 50 of the semiconductor chip 10; wherein each of the die pads 60 is electrically connected to each of the seed layers 40 and each of the conductive traces 50, so that each of the die pads 60 can be electrically connected to each of the bonding pads 12 of the semiconductor chip 10 through each of the seed layers 40 and each of the conductive traces 50.

Step S7: as shown in fig. 9, a plurality of second dielectric layers 30 are correspondingly disposed on the surfaces of the first dielectric layers 20, each second dielectric layer 30 is formed with at least one second groove 31 and at least one second groove 31, and each second groove 31 exposes each die pad 60 to the outside, so that each die pad 60 can be electrically connected to the outside.

As shown in fig. 9, each die pad 60 further includes a hemispherical solder joint 80 for external electrical connection, but not limited thereto.

The embodiment shown in fig. 1 to 8 is a fourth embodiment of the present invention, the semiconductor chip package is mounted on a substrate through the bonding wire structure 1 to electrically connect with a plurality of pads disposed on the substrate, the bonding wire structure 1 includes a semiconductor chip 10, a plurality of first dielectric layers 20, a plurality of second dielectric layers 30, a plurality of seed layers (seed layers) 40, a plurality of bonding wires 50, a plurality of die pads 60 and a plurality of third dielectric layers 70.

The semiconductor chip 10 has a surface 11 as shown in fig. 1, and a plurality of bonding pads 12 are disposed on the surface 11.

As shown in fig. 1, each first dielectric layer 20 is disposed on the surface 11 of the semiconductor chip 10, and at least one first groove 21 is formed on each first dielectric layer 20, and each first groove 21 is used for exposing each bonding pad 12 of the semiconductor chip 10.

Each second dielectric layer 30 is disposed on the surface of each first dielectric layer 20 as shown in fig. 1, and at least one second groove 21 is formed on each second dielectric layer 30, and each second groove 21 is in communication with each first groove 21.

Each seed layer 40 is correspondingly disposed on the surface 11 of the semiconductor wafer 10 and covers each bonding pad 12 as shown in fig. 1, and each seed layer 40 is disposed in each first groove 21 and each second groove 21; wherein each seed layer 40 is electrically connected to each bonding pad 12 of the semiconductor chip 10.

Each conductive line 50 is correspondingly disposed on each seed layer 40 in a covering manner as shown in fig. 1, and each conductive line 50 fills each seed layer 40 but has a thickness not exceeding the coverage of each seed layer 40 on the semiconductor wafer 10; wherein each conductive line 50 is electrically connected to each seed layer 40, so that each conductive line 50 can be electrically connected to each bonding pad 12 of the semiconductor chip 10 through each seed layer 40.

Each of the die pads 60 is correspondingly disposed on the surface of each of the seed layers 40 and the conductive traces 50 as shown in fig. 1, and each of the die pads 60 covers each of the bonding pads 12, each of the seed layers 40 and each of the conductive traces 50 of the semiconductor chip 10; wherein each of the die pads 60 is electrically connected to each of the seed layers 40 and each of the conductive traces 50, so that each of the die pads 60 can be electrically connected to each of the bonding pads 12 of the semiconductor chip 10 through each of the seed layers 40 and each of the conductive traces 50.

Each of the third dielectric layers 70 is correspondingly disposed on the surfaces of each of the second dielectric layers 30 and each of the die pads 60 as shown in fig. 1, and at least one third groove 71 is formed on each of the third dielectric layers 70, each of the third grooves 71 exposes each of the die pads 60 to the outside, so that each of the die pads 60 can be electrically connected to the outside.

The manufacturing method of the conductive circuit structure 1 comprises the following steps:

step S1: as shown in fig. 2, a semiconductor chip 10 is provided, the semiconductor chip 10 has a surface 11, and a plurality of bonding pads 12 are disposed on the surface 11.

Step S2: as shown in fig. 3, a plurality of first dielectric layers 20 are formed on the surface 11 of the semiconductor chip 10, at least one first groove 21 is formed on each first dielectric layer 20, and each first groove 21 is used for exposing each bonding pad 12 of the semiconductor chip 10.

Step S3: as shown in fig. 4, a plurality of second dielectric layers 30 are disposed on each first dielectric layer 20, at least one second groove 31 is formed on each second dielectric layer 30, and each second groove 31 is communicated with each first groove 21.

Step S4: correspondingly covering a plurality of seed layers (seed layers) 40 on the surface 11 of the semiconductor wafer 10 as shown in fig. 5, wherein each seed layer 40 corresponds to and covers each bonding pad 12, and each seed layer 40 is disposed on the surface of each first dielectric layer 20, on the surface of each second dielectric layer 30, in each first groove 21 and in each second groove 31; wherein each seed layer 40 is electrically connected to each bonding pad 12 of the semiconductor chip 10.

Step S5: as shown in fig. 6, a plurality of conductive traces 50 are correspondingly disposed on each seed layer 40 in a covering manner, and each seed layer 40 is ground flat or ground into a micro-protrusion without limitation, and each conductive trace 50 fills each first groove 21 and each second groove 31, which is different from the prior art that a passivation layer is disposed on a bonding pad, thereby effectively avoiding the problem of poor contact of the bonding pad due to oxidation damage of the passivation layer on the surface of the bonding pad; wherein each conductive line 50 is electrically connected to each seed layer 40, so that each conductive line 50 can be electrically connected to each bonding pad 12 of the semiconductor chip 10 through each seed layer 40.

Step S6: as shown in fig. 7, unnecessary portions of each seed layer 40 and each conductive line 50 are removed, so that each conductive line 50 fills each seed layer 40 but has a thickness not exceeding the coverage of each seed layer 40 on the semiconductor wafer 10, and each seed layer 40 is only located in each first groove 21 and each second groove 31.

Step S7: a plurality of die pads 60 are correspondingly disposed on the surfaces of the seed layers 40 and the bonding wires 50, as shown in fig. 8, and each die pad 60 covers each bonding pad 12, each seed layer 40 and each bonding wire 50 of the semiconductor chip 10; wherein each of the die pads 60 is electrically connected to each of the seed layers 40 and each of the conductive traces 50, so that each of the die pads 60 can be electrically connected to each of the bonding pads 12 of the semiconductor chip 10 through each of the seed layers 40 and each of the conductive traces 50.

Step S8: as shown in fig. 1, each of the third dielectric layers 70 is disposed on the surfaces of each of the second dielectric layers 30 and each of the die pads 60 so as to cover the surface correspondingly, at least one third groove 71 is formed on each of the third dielectric layers 70, and each of the third grooves 71 exposes each of the die pads 60 to the outside, so that each of the die pads 60 can be electrically connected to the outside.

As shown in fig. 1, each die pad 60 further includes a hemispherical solder joint 80 for external electrical connection, but not limited thereto.

The foregoing is merely a preferred embodiment of this invention, which is intended to be illustrative, not limiting; those skilled in the art will appreciate that many variations, modifications, and even equivalent variations are possible within the spirit and scope of the utility model as defined in the appended claims.

Claims

1. A lead circuit structure of a semiconductor chip package, the semiconductor chip package is mounted on a substrate through the lead circuit structure to be electrically connected with a plurality of pads disposed on the substrate, the lead circuit structure comprises:

a semiconductor chip having a surface on which a plurality of bonding pads are formed;

a plurality of first dielectric layers, each of which covers the surface of the semiconductor chip and is formed with at least one first groove for exposing the bonding pad of the semiconductor chip;

a plurality of seed crystal layers, each seed crystal layer is correspondingly covered on the surface of the semiconductor wafer and covers each welding pad, and each seed crystal layer is arranged in each first groove; wherein each seed layer is electrically connected with each bonding pad of the semiconductor chip;

a plurality of conductive lines, each conductive line is correspondingly covered on each seed crystal layer and covers each bonding pad of the semiconductor chip, and each conductive line fills each seed crystal layer but the thickness of each conductive line does not exceed the coverage range of each seed crystal layer on the semiconductor chip; wherein each conductive line is electrically connected with each seed layer, so that each conductive line can be electrically connected with each bonding pad of the semiconductor chip through each seed layer; and

and the second dielectric layers are respectively correspondingly arranged on the surfaces of the first dielectric layers and the conducting circuits in a covering manner, at least one second groove is formed on each second dielectric layer, and each second groove is used for exposing the conducting circuits outwards so that the conducting circuits can be electrically connected outwards.

2. The structure of claim 1, wherein each of the first dielectric layers and the second dielectric layers is formed by a spin coating process.

3. A lead circuit structure of a semiconductor chip package, the semiconductor chip package is mounted on a substrate through the lead circuit structure to be electrically connected with a plurality of pads disposed on the substrate, the lead circuit structure comprises:

the second dielectric layers are arranged on the surfaces of the first dielectric layers in a covering mode, at least one second groove is formed in each second dielectric layer, and each second groove is communicated with each first groove;

a plurality of seed crystal layers, each seed crystal layer is correspondingly arranged on the surface of the semiconductor wafer in a covering manner and covers each welding pad, and each seed crystal layer is arranged in each first groove and each second groove; wherein each seed layer is electrically connected with each bonding pad of the semiconductor chip;

and each third dielectric layer is correspondingly arranged on the surfaces of the second dielectric layers and the third dielectric layers in a covering manner, at least one third groove is formed on each third dielectric layer, and each third groove is exposed outwards so as to enable the third dielectric layers to be electrically connected with the outside.

4. The structure of claim 3, wherein each of the first dielectric layer, the second dielectric layer and the third dielectric layer is formed by a spin coating process.

5. A lead circuit structure of a semiconductor chip package, the semiconductor chip package is mounted on a substrate through the lead circuit structure to be electrically connected with a plurality of welding points distributed on the substrate, the lead circuit structure comprises:

a plurality of seed crystal layers, each seed crystal layer is correspondingly arranged on the surface of the semiconductor wafer in a covering manner and covers each welding pad, and each seed crystal layer is arranged in each first groove; wherein each seed layer is electrically connected with each bonding pad of the semiconductor chip;

a plurality of conductive lines, each conductive line is correspondingly covered on each seed crystal layer, and each conductive line fills each seed crystal layer but the thickness of each conductive line does not exceed the coverage range of each seed crystal layer on the semiconductor wafer; wherein each conductive line is electrically connected with each seed layer, so that each conductive line can be electrically connected with each bonding pad of the semiconductor chip through each seed layer;

a plurality of die pads, each of which is correspondingly covered on the surface of each of the seed layers and the conductive lines, and covers each of the bonding pads, each of the seed layers and each of the conductive lines of the semiconductor chip; wherein each of the die pads is electrically connected to each of the seed layers and each of the conductive traces, so that each of the conductive traces can be electrically connected to each of the bonding pads of the semiconductor chip through each of the seed layers and each of the conductive traces; and

and the second dielectric layers are respectively correspondingly arranged on the surfaces of the first dielectric layers and the crystal pads in a covering manner, at least one second groove is formed on each second dielectric layer, and each crystal pad is exposed outwards by each second groove so as to enable each crystal pad to be electrically connected outwards.

6. The structure of claim 5, wherein each of the first dielectric layers and the second dielectric layers is formed by a spin coating process.

7. A lead circuit structure of a semiconductor chip package, the semiconductor chip package is mounted on a substrate through the lead circuit structure to be electrically connected with a plurality of welding points distributed on the substrate, the lead circuit structure comprises:

a plurality of seed crystal layers, each seed crystal layer is correspondingly arranged on the surface of the semiconductor wafer in a covering mode and covers each welding pad, and part of each seed crystal layer is arranged in each first groove and each second groove; wherein each seed layer is electrically connected with each bonding pad of the semiconductor chip;

a plurality of die pads, each of which is correspondingly covered on the surface of each of the seed layers and the conductive lines, and covers each of the bonding pads, each of the seed layers and each of the conductive lines of the semiconductor chip; wherein each of the die pads is electrically connected to each of the seed layers and each of the conductive traces, so that each of the die pads can be electrically connected to each of the bonding pads of the semiconductor chip through each of the seed layers and each of the conductive traces; and

and the third dielectric layers are respectively correspondingly arranged on the surfaces of the second dielectric layers and the crystal pads in a covering manner, at least one third groove is formed on each third dielectric layer, and each crystal pad is exposed outwards by each third groove so as to enable each crystal pad to be electrically connected outwards.

8. The structure of claim 7, wherein each of the first dielectric layer, the second dielectric layer and the third dielectric layer is formed by a spin coating process.