CN215986357U - Test system of super capacitor circuit - Google Patents
Test system of super capacitor circuit Download PDFInfo
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- CN215986357U CN215986357U CN202121192307.8U CN202121192307U CN215986357U CN 215986357 U CN215986357 U CN 215986357U CN 202121192307 U CN202121192307 U CN 202121192307U CN 215986357 U CN215986357 U CN 215986357U
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Abstract
The utility model relates to a test system of a super capacitor circuit, which comprises the super capacitor circuit and a test tool, wherein in the super capacitor circuit, a voltage input end and a voltage output end of a charging circuit are both provided with at least one test point, a voltage equalizing circuit is provided with the test point at a position where level change occurs after the voltage equalizing circuit acts, a voltage input end and a voltage output end of a boosting circuit are both provided with at least one test point, and a voltage input end and a voltage output end of a discharging circuit are both provided with at least one test point; the output voltage of the first test voltage output end of the test tool is higher than the sum of the nominal voltages of all the super capacitors in the charge and discharge circuit, and the output voltage of the second test voltage output end of the test tool is higher than the detection voltage of any power supply monitoring chip in the charge and discharge circuit and is lower than the target voltage output by the booster circuit. The test system can complete the test of the super capacitor circuit at the front end of the production of the product with the super capacitor circuit, and avoids the complex process of repairing the assembled product.
Description
Technical Field
The utility model relates to the field of super capacitor circuits, in particular to a test system of a super capacitor circuit.
Background
With the operation of various power terminal devices in the power grid, a new requirement is put on the operation standard of the power terminal devices, that is, in the case of power failure, a super capacitor circuit in the power terminal device is required to be capable of providing electric energy for more than 3 minutes for the operation of the power terminal device so as to ensure that the power terminal device completes necessary execution operation.
In order to meet the requirement of the power terminal equipment on the discharge time of a super capacitor circuit arranged in the power terminal equipment, the charging and discharging circuit of the super capacitor and the voltage boosting and reducing circuit part must be accurately tested so as to ensure that the problem can be exposed before the power terminal equipment is produced, the problem is solved in advance, and higher rear end maintenance cost is prevented from being generated after the power terminal equipment is produced.
The existing test aiming at the super capacitor circuit only achieves the aim of testing the charge and discharge performance of the super capacitor by calculating the power supply time of the super capacitor under the condition that the power failure of the power terminal equipment is determined. Therefore, the test efficiency is low, the performance of the boost and buck circuit of the super capacitor cannot be tested, the potential fault hazard is left for the normal operation of the power terminal equipment after leaving a factory, and the rear end maintenance cost of the power terminal equipment is increased.
SUMMERY OF THE UTILITY MODEL
The technical problem to be solved by the present invention is to provide a test system for a super capacitor circuit in view of the above prior art.
The technical scheme adopted by the utility model for solving the technical problems is as follows: a test system of a super capacitor circuit is characterized by comprising the super capacitor circuit and a test tool; wherein, super capacitor circuit includes:
the charging circuit is provided with a charging circuit voltage input end, at least two super capacitors connected in series, at least two power supply monitoring chips and a charging circuit voltage output end, wherein the charging circuit voltage input end is provided with at least one test point, and the charging circuit voltage output end is provided with at least one test point;
the voltage-sharing circuit is provided with a test point at the position where the level change occurs after the action;
the booster circuit is provided with a booster circuit voltage input end and a booster circuit voltage output end, and the booster circuit voltage input end and the booster circuit voltage output end are both provided with at least one test point;
the discharge circuit is provided with a discharge circuit voltage input end and a discharge circuit voltage output end, the discharge circuit voltage input end is provided with at least one test point, and the discharge circuit voltage output end is provided with at least one test point;
the test tool is provided with a test voltage output end group and a test voltage input end group, the test voltage output end group at least comprises a first test voltage output end and a second test voltage output end, and the test voltage input end group at least comprises a test voltage input end;
in the test tool, the output voltage of the first test voltage output end is higher than the sum of the nominal voltages of all the super capacitors in the charge and discharge circuit, and the output voltage of the second test voltage output end is higher than the detection voltage of any power supply monitoring chip in the charge and discharge circuit and is lower than the target voltage output by the booster circuit.
Further, in the test system of the super capacitor circuit, the test tool is provided with a display and a grounding end.
In an improvement, in the test system of the super capacitor circuit, the charging circuit includes:
a first end of the resistor R218 is connected with a first voltage output interface of the test tool;
a resistor R541, a first end of which is connected with a second end of the resistor R218;
the emitter of the triode V106 is connected to the second end of the resistor R218 and the first end of the resistor R541, respectively;
a diode VD332 whose positive electrode is connected to the collector of the transistor V106;
the emitter of the triode V109 is connected with the first voltage output interface of the test tool, the base of the triode V109 is connected with the second end of the resistor R541, and the collector of the triode V106 is connected with the base of the triode V;
a resistor R539, a first end of which is connected with a collector of the triode V109;
a collector of the triode V103 is connected with the second end of the resistor R539;
a resistor R214, the second end of which is connected with the base of the triode V103;
a resistor R236, a first end of which is connected to the second end of the resistor R214, and a second end of which and the emitter of the transistor V103 are connected to the ground GND, respectively;
a test point TP6 is arranged at the first end of the resistor R218, a test point TP1 is arranged at the cathode of the diode VD332, and a test point TP5 is arranged at the emitter of the transistor V103.
In a further improvement, in the test system of the super capacitor circuit, the voltage equalizing circuit includes:
a super capacitor C207;
the positive electrode of the super capacitor C225 is connected with the negative electrode of the super capacitor C207 through a short-circuit point S101, and the negative electrode of the super capacitor C is connected with the ground end GND through another short-circuit point S100;
one pin of the power supply monitoring chip N109 is connected with the anode of the super capacitor C207;
a resistor R294 having a first end connected to the positive electrode of the supercapacitor C207;
a resistor R306 having a first end connected to the power supply monitoring chip N109 and a second end connected to the second end of the resistor R294 through the MOS transistor M102;
a resistor R307, a first end of which is connected to a second end of the resistor R306, and a second end of which is connected to the ground GND and the short-circuit point S100 of the power supply monitoring chip N109, respectively;
the power supply monitoring chip N110 is provided with a grounding end, and one pin of the power supply monitoring chip N110 is respectively connected with the short-circuit point S100 and the grounding end GND of the power supply monitoring chip N109;
a resistor R316, a first end of which is connected to one end of the power monitoring chip N110, a second end of which is connected to a second end of a resistor R311 through the MOS transistor M101, and a first end of the resistor R311 is connected to a second end of the resistor R307;
a resistor R317, a first end of which is connected to the second end of the resistor R316, and a second end of which is connected to the ground GND of the power monitoring chip N110;
the test point TP1 is arranged between the positive electrode of the super capacitor C207 and the first end of the resistor R294, the test point TP2 is arranged between the second end of the resistor R294 and the MOS transistor M102, the test point TP3 is arranged between the second end of the resistor R307 and the ground terminal GND of the power supply monitoring chip N109, the test point TP4 is arranged between the second end of the resistor R311 and the MOS transistor M101, and the test point TP5 is arranged between the second end of the resistor R317 and the ground terminal GND of the power supply monitoring chip N110.
In a further improvement, in the test system of the super capacitor circuit, the boost circuit includes:
a voltage conversion chip N106;
the series resistor group comprises a resistor R301, a resistor R302 and a resistor R303 which are sequentially connected in series, the first end of the resistor R310 is grounded, the second end of the resistor R310 is connected with the resistor R302, and the feedback end FB of the voltage conversion chip N106 is connected between the resistor R301 and the resistor R302;
a resistor R304, a first end of which is connected to the anode of the super capacitor C207, a second end of which is connected to the collector of a transistor V104, an emitter of the transistor V104 is connected to the ground GND and one end of a resistor R257, respectively, and the other end of the resistor R257 is connected to the base of the transistor V104 and one end of a resistor R210, respectively; the second end of the resistor R304 is connected to the enable end EN of the voltage conversion chip N106, and the power supply end VDD of the voltage conversion chip N106 is connected to the ground end GND through a capacitor C243; an input voltage end VIN of the voltage conversion chip N106 is connected to a ground terminal GND through a capacitor C246, a SW end of the voltage conversion chip N106 is connected to the input voltage end VIN of the voltage conversion chip N106 through an inductor L107, and a BST end of the voltage conversion chip N106 is connected to the SW end of the voltage conversion chip N106 through a capacitor C244;
the parallel capacitor bank comprises a capacitor C247 and a capacitor C245 which are connected in parallel, a first parallel end of the parallel capacitor bank is connected with an output voltage end VOUT of the voltage conversion chip N106, and a second parallel end of the parallel capacitor bank is connected with a ground end GND;
the test point TP1 is disposed between the input voltage terminal VIN of the voltage conversion chip N106 and the capacitor C246, the test point TP5 is disposed at the second parallel end of the parallel capacitor bank, and the test point TP6 is disposed at the first parallel end of the parallel capacitor bank.
For example, in the present invention, the voltage conversion chip N106 herein is a DCDC voltage conversion chip.
Further, in the test system of the super capacitor circuit, the output voltage of the first test voltage output end in the test tool is 5.4V, the output voltage of the second test voltage output end in the test tool is 2.7V, and the detection voltage of the chip N109 is 2.6V.
Further, in the test system of the super capacitor circuit, the model of the power supply monitoring chip N109 and the model of the power supply monitoring chip N110 are both SGM 809B.
Still further, in the test system of the super capacitor circuit, the model of the chip N106 is MP3437 GJ.
Further, in the test system of the super capacitor circuit, the capacitance value of the capacitor C207 and the capacitance value of the capacitor C225 are both 150F.
Compared with the prior art, the utility model has the advantages that: in the utility model of the super capacitor circuit test system, the test tool can test the voltage equalizing circuit, the charging circuit and the booster circuit of the super capacitor circuit at the front end of the super capacitor circuit product, thereby avoiding the complex process of repairing the assembled product and reducing the time cost and the maintenance cost; secondly, the test system in this utility model can accomplish super capacitor circuit's capability test by simple and fast ground, realizes the synchronous test to super capacitor circuit in the many products.
Drawings
FIG. 1 is a schematic diagram of a test fixture in an embodiment of the utility model;
FIG. 2 is a schematic diagram of a charging circuit in a super capacitor circuit;
FIG. 3 is a schematic diagram of a voltage equalizing circuit in a super capacitor circuit;
FIG. 4 is a schematic diagram of a boost discharge circuit in a super capacitor circuit.
Detailed Description
The utility model is described in further detail below with reference to the accompanying examples.
The embodiment provides a test system of a super capacitor circuit. Specifically, referring to fig. 1 to 4, the test system of the super capacitor circuit of the embodiment includes:
the charging circuit is provided with a charging circuit voltage input end, at least two super capacitors connected in series, at least two power supply monitoring chips and a charging circuit voltage output end, wherein the charging circuit voltage input end is provided with at least one test point, and the charging circuit voltage output end is provided with at least one test point;
the voltage-sharing circuit is provided with a test point at the position where the level change occurs after the action;
the booster circuit is provided with a booster circuit voltage input end and a booster circuit voltage output end, and the booster circuit voltage input end and the booster circuit voltage output end are both provided with at least one test point;
the discharge circuit is provided with a discharge circuit voltage input end and a discharge circuit voltage output end, the discharge circuit voltage input end is provided with at least one test point, and the discharge circuit voltage output end is provided with at least one test point;
the test tool is provided with a test voltage output end group and a test voltage input end group, the test voltage output end group comprises a first test voltage output end, a second test voltage output end and a third test voltage output end, and the test voltage input end group at least comprises a test voltage input end; each voltage output end in the test voltage output end group is responsible for providing test voltage for the super capacitor circuit, and the voltage input end in the test voltage input end group is responsible for collecting the voltage of a corresponding test point in the super capacitor circuit; for example, test voltage input terminal T1, test voltage input terminal T2, test voltage input terminal T3, and test voltage input terminal T4 in fig. 1. The output voltage of the first test voltage output end in the test tool is 5.4V, and the output voltage of the second test voltage output end is 2.7V. The test fixture has a display and a ground GND. The arranged display can enable the test tool to display the voltage of the test point collected by the test voltage input end through the display interface.
In the test tool, the output voltage of the first test voltage output end is higher than the sum of the nominal voltages of all the super capacitors in the charge and discharge circuit, and the output voltage of the second test voltage output end is higher than the detection voltage of any power supply monitoring chip in the charge and discharge circuit and is lower than the target voltage output by the booster circuit.
Specifically, in this embodiment, referring to fig. 2, the charging circuit includes:
a first end of the resistor R218 is connected with a first voltage output interface of the test tool;
a resistor R541, a first end of which is connected with a second end of the resistor R218;
the emitter of the triode V106 is connected to the second end of the resistor R218 and the first end of the resistor R541, respectively;
a diode VD332 whose positive electrode is connected to the collector of the transistor V106;
the emitter of the triode V109 is connected with the first voltage output interface of the test tool, the base of the triode V109 is connected with the second end of the resistor R541, and the collector of the triode V106 is connected with the base of the triode V;
a resistor R539, a first end of which is connected with a collector of the triode V109;
a collector of the triode V103 is connected with the second end of the resistor R539;
a resistor R214, the second end of which is connected with the base of the triode V103;
a resistor R236, a first end of which is connected to the second end of the resistor R214, and a second end of which and the emitter of the transistor V103 are connected to the ground GND, respectively;
a test point TP6 is arranged at the first end of the resistor R218, a test point TP1 is arranged at the cathode of the diode VD332, and a test point TP5 is arranged at the emitter of the transistor V103.
Referring to fig. 3, the voltage equalizing circuit includes:
the capacitance value of the super capacitor C207 is 150F;
the positive electrode of the super capacitor C225 is connected with the negative electrode of the super capacitor C207 through a short-circuit point S101, the negative electrode of the super capacitor C225 is connected with the ground end GND through another short-circuit point S100, and the capacitance value of the super capacitor C225 is 150F;
one pin of the power supply monitoring chip N109 is connected with the anode of the super capacitor C207, the model of the power supply monitoring chip N109 adopts SGM809B, and the detection voltage of the power supply monitoring chip N109 is 2.6V;
a resistor R294 having a first end connected to the positive electrode of the supercapacitor C207;
a resistor R306 having a first end connected to the power supply monitoring chip N109 and a second end connected to the second end of the resistor R294 through the MOS transistor M102;
a resistor R307, a first end of which is connected to a second end of the resistor R306, and a second end of which is connected to the ground GND and the short-circuit point S100 of the power supply monitoring chip N109, respectively;
the power supply monitoring chip N110 is provided with a grounding end, and one pin of the power supply monitoring chip N110 is respectively connected with the short-circuit point S100 and the grounding end GND of the power supply monitoring chip N109; the model of the power supply monitoring chip N110 also adopts SGM 809B;
a resistor R316, a first end of which is connected to one end of the power monitoring chip N110, a second end of which is connected to a second end of a resistor R311 through the MOS transistor M101, and a first end of the resistor R311 is connected to a second end of the resistor R307;
a resistor R317, a first end of which is connected to the second end of the resistor R316, and a second end of which is connected to the ground GND of the power monitoring chip N110;
the test point TP1 is arranged between the positive electrode of the super capacitor C207 and the first end of the resistor R294, the test point TP2 is arranged between the second end of the resistor R294 and the MOS transistor M102, the test point TP3 is arranged between the second end of the resistor R307 and the ground terminal GND of the power supply monitoring chip N109, the test point TP4 is arranged between the second end of the resistor R311 and the MOS transistor M101, and the test point TP5 is arranged between the second end of the resistor R317 and the ground terminal GND of the power supply monitoring chip N110.
Referring to fig. 4, the booster circuit includes:
the voltage conversion chip N106 adopts a DCDC voltage conversion chip;
the series resistor group comprises a resistor R301, a resistor R302 and a resistor R303 which are sequentially connected in series, the first end of the resistor R310 is grounded, the second end of the resistor R310 is connected with the resistor R302, and the feedback end FB of the voltage conversion chip N106 is connected between the resistor R301 and the resistor R302;
a resistor R304, a first end of which is connected to the anode of the super capacitor C207, a second end of which is connected to the collector of a transistor V104, an emitter of the transistor V104 is connected to the ground GND and one end of a resistor R257, respectively, and the other end of the resistor R257 is connected to the base of the transistor V104 and one end of a resistor R210, respectively; the second end of the resistor R304 is connected to the enable end EN of the voltage conversion chip N106, and the power supply end VDD of the voltage conversion chip N106 is connected to the ground end GND through a capacitor C243; an input voltage end VIN of the voltage conversion chip N106 is connected to a ground terminal GND through a capacitor C246, a SW end of the voltage conversion chip N106 is connected to the input voltage end VIN of the voltage conversion chip N106 through an inductor L107, and a BST end of the voltage conversion chip N106 is connected to the SW end of the voltage conversion chip N106 through a capacitor C244;
the parallel capacitor bank comprises a capacitor C247 and a capacitor C245 which are connected in parallel, a first parallel end of the parallel capacitor bank is connected with an output voltage end VOUT of the voltage conversion chip N106, and a second parallel end of the parallel capacitor bank is connected with a ground end GND;
the test point TP1 is disposed between the input voltage terminal VIN of the voltage conversion chip N106 and the capacitor C246, the test point TP5 is disposed at the second parallel end of the parallel capacitor bank, and the test point TP6 is disposed at the first parallel end of the parallel capacitor bank.
The following describes the testing process of the testing system of the super capacitor circuit in this embodiment with reference to fig. 1 to 4:
charging circuit test scheme
The method comprises the steps of enabling a first test voltage output end of a test tool with the output voltage of +5.4V to be connected into a test point TP6, enabling a ground terminal GND of the test tool to be connected into a test point TP5, enabling a test voltage input interface T1 of the test tool to be connected into a test point TP1, enabling a test voltage input interface T2 to be connected into a test point TP5, enabling a short-circuit point S100 and a short-circuit point S101 to be in short circuit, and then enabling the test tool to be powered on. When a rising edge of the voltage between the test point TP1 and the test point TP5 is detected, it indicates that the test is performed, and the charging circuit is operating normally.
(II) voltage-equalizing circuit test scheme
Connecting 3 output interfaces (namely three test voltage output ends) of the test tool with a test point TP1, a test point TP3 and a test point TP5 in the figure 3 respectively, then connecting the input interfaces of the test tool into the test point TP1, the test point TP2, the test point TP3 and the test point TP4 respectively, disconnecting the short-circuit point S100 and the short-circuit point S101, and then electrifying the test tool.
When the voltage-sharing circuit works, square waves with the period of 280ms appear between the test point TP1 and the test point TP2 and between the test point TP3 and the test point TP4, so that the voltage-sharing circuit can be determined to work normally through testing, and the voltage-sharing work of the circuit can be ensured when the voltage difference occurs between the two super capacitors C207 and C225 under the actual operation condition.
After the test tool is powered on, the input voltage of the power supply monitoring chip N110 is 2.7V, the nrest pin of the power supply monitoring chip N110 outputs a high level, the MOS transistor M101 is turned on, and at this time, the voltage drop of the MOS transistor M101 is close to 0V, so that the voltage drop between the test point TP3 and the test point TP4 is close to 2.7V. When the input voltage of the power supply monitoring chip N110 fluctuates and drops to less than 2.6V due to the sudden connection of the resistor R308, the nrest pin of the power supply monitoring chip N110 immediately outputs a low level, the MOS transistor M101 is turned off and is not turned on, at this time, the voltage drop between the test point TP3 and the test point TP4 is close to 0V, the input voltage of the power supply monitoring chip N110 gradually rises due to the reduction of the load, and when the input voltage is greater than 2.6V, the nrest pin outputs a high level after 140ms due to the delay of the power supply monitoring chip N110, and the process is repeated. The working principle of the power supply monitoring chip N109 is the same as that of the power supply monitoring chip N110.
(III) booster circuit test scheme
Connecting a test voltage output end of the test tool with an output voltage of +2.7V to a test point TP1 in fig. 4 and connecting a ground end GND of the test tool to a test point TP5, disconnecting a short-circuit point S100 and a short-circuit point S101 in fig. 3, connecting a test voltage input interface T1 of the test tool to a test point TP6 in fig. 3, connecting a test voltage input interface T2 of the test tool to a test point TP5 in fig. 3, and then powering on the test tool.
When the voltage difference between the test point TP6 and the test point TP5 is detected to be 5.2V, it indicates that the boosting circuit is working normally. When the input voltage of the booster circuit is higher than the output of the rear end, the booster circuit does not work. The boost circuit is tested with an input voltage lower than the output voltage.
Although preferred embodiments of the present invention have been described in detail hereinabove, it should be clearly understood that modifications and variations of the present invention are possible to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A test system of a super capacitor circuit is characterized by comprising the super capacitor circuit and a test tool; wherein, super capacitor circuit includes:
the charging circuit is provided with a charging circuit voltage input end, at least two super capacitors connected in series, at least two power supply monitoring chips and a charging circuit voltage output end, wherein the charging circuit voltage input end is provided with at least one test point, and the charging circuit voltage output end is provided with at least one test point;
the voltage-sharing circuit is provided with a test point at the position where the level change occurs after the action;
the booster circuit is provided with a booster circuit voltage input end and a booster circuit voltage output end, and the booster circuit voltage input end and the booster circuit voltage output end are both provided with at least one test point;
the discharge circuit is provided with a discharge circuit voltage input end and a discharge circuit voltage output end, the discharge circuit voltage input end is provided with at least one test point, and the discharge circuit voltage output end is provided with at least one test point;
the test tool is provided with a test voltage output end group and a test voltage input end group, the test voltage output end group at least comprises a first test voltage output end and a second test voltage output end, and the test voltage input end group at least comprises a test voltage input end;
in the test tool, the output voltage of the first test voltage output end is higher than the sum of the nominal voltages of all the super capacitors in the charge and discharge circuit, and the output voltage of the second test voltage output end is higher than the detection voltage of any power supply monitoring chip in the charge and discharge circuit and is lower than the target voltage output by the booster circuit.
2. The system of claim 1, wherein the test fixture has a display and a ground.
3. The system for testing the supercapacitor circuit according to claim 1, wherein the charging circuit comprises:
a first end of the resistor R218 is connected with a first voltage output interface of the test tool;
a resistor R541, a first end of which is connected with a second end of the resistor R218;
the emitter of the triode V106 is connected to the second end of the resistor R218 and the first end of the resistor R541, respectively;
a diode VD332 whose positive electrode is connected to the collector of the transistor V106;
the emitter of the triode V109 is connected with the first voltage output interface of the test tool, the base of the triode V109 is connected with the second end of the resistor R541, and the collector of the triode V106 is connected with the base of the triode V;
a resistor R539, a first end of which is connected with a collector of the triode V109;
a collector of the triode V103 is connected with the second end of the resistor R539;
a resistor R214, the second end of which is connected with the base of the triode V103;
a resistor R236, a first end of which is connected to the second end of the resistor R214, and a second end of which and the emitter of the transistor V103 are connected to the ground GND, respectively;
a test point TP6 is arranged at the first end of the resistor R218, a test point TP1 is arranged at the cathode of the diode VD332, and a test point TP5 is arranged at the emitter of the transistor V103.
4. The test system of the supercapacitor circuit according to claim 3, wherein the voltage grading circuit comprises:
a super capacitor C207;
the positive electrode of the super capacitor C225 is connected with the negative electrode of the super capacitor C207 through a short-circuit point S101, and the negative electrode of the super capacitor C is connected with the ground end GND through another short-circuit point S100;
one pin of the power supply monitoring chip N109 is connected with the anode of the super capacitor C207;
a resistor R294 having a first end connected to the positive electrode of the supercapacitor C207;
a resistor R306 having a first end connected to the power supply monitoring chip N109 and a second end connected to the second end of the resistor R294 through the MOS transistor M102;
a resistor R307, a first end of which is connected to a second end of the resistor R306, and a second end of which is connected to the ground GND and the short-circuit point S100 of the power supply monitoring chip N109, respectively;
the power supply monitoring chip N110 is provided with a grounding end, and one pin of the power supply monitoring chip N110 is respectively connected with the short-circuit point S100 and the grounding end GND of the power supply monitoring chip N109;
a resistor R316, a first end of which is connected to one end of the power monitoring chip N110, a second end of which is connected to a second end of a resistor R311 through the MOS transistor M101, and a first end of the resistor R311 is connected to a second end of the resistor R307;
a resistor R317, a first end of which is connected to the second end of the resistor R316, and a second end of which is connected to the ground GND of the power monitoring chip N110;
the test point TP1 is arranged between the positive electrode of the super capacitor C207 and the first end of the resistor R294, the test point TP2 is arranged between the second end of the resistor R294 and the MOS transistor M102, the test point TP3 is arranged between the second end of the resistor R307 and the ground terminal GND of the power supply monitoring chip N109, the test point TP4 is arranged between the second end of the resistor R311 and the MOS transistor M101, and the test point TP5 is arranged between the second end of the resistor R317 and the ground terminal GND of the power supply monitoring chip N110.
5. The system for testing the supercapacitor circuit according to claim 4, wherein the boost circuit comprises:
a voltage conversion chip N106;
the series resistor group comprises a resistor R301, a resistor R302 and a resistor R303 which are sequentially connected in series, the first end of the resistor R310 is grounded, the second end of the resistor R310 is connected with the resistor R302, and the feedback end FB of the voltage conversion chip N106 is connected between the resistor R301 and the resistor R302;
a resistor R304, a first end of which is connected to the anode of the super capacitor C207, a second end of which is connected to the collector of a transistor V104, an emitter of the transistor V104 is connected to the ground GND and one end of a resistor R257, respectively, and the other end of the resistor R257 is connected to the base of the transistor V104 and one end of a resistor R210, respectively; the second end of the resistor R304 is connected to the enable end EN of the voltage conversion chip N106, and the power supply end VDD of the voltage conversion chip N106 is connected to the ground end GND through a capacitor C243; an input voltage end VIN of the voltage conversion chip N106 is connected to a ground terminal GND through a capacitor C246, a SW end of the voltage conversion chip N106 is connected to the input voltage end VIN of the voltage conversion chip N106 through an inductor L107, and a BST end of the voltage conversion chip N106 is connected to the SW end of the voltage conversion chip N106 through a capacitor C244;
the parallel capacitor bank comprises a capacitor C247 and a capacitor C245 which are connected in parallel, a first parallel end of the parallel capacitor bank is connected with an output voltage end VOUT of the voltage conversion chip N106, and a second parallel end of the parallel capacitor bank is connected with a ground end GND;
the test point TP1 is disposed between the input voltage terminal VIN of the voltage conversion chip N106 and the capacitor C246, the test point TP5 is disposed at the second parallel end of the parallel capacitor bank, and the test point TP6 is disposed at the first parallel end of the parallel capacitor bank.
6. The test system of the super capacitor circuit as claimed in claim 5, wherein the output voltage of the first test voltage output terminal in the test fixture is 5.4V, the output voltage of the second test voltage output terminal in the test fixture is 2.7V, and the detection voltage of the power supply monitoring chip N109 is 2.6V.
7. The test system of the super capacitor circuit as claimed in claim 6, wherein the model of the power supply monitoring chip N109 and the model of the power supply monitoring chip N110 are both SGM 809B.
8. The system for testing the super capacitor circuit as claimed in claim 7, wherein the model of the chip N106 is MP3437 GJ.
9. The system for testing the super capacitor circuit as claimed in claim 5, wherein the capacitance value of the super capacitor C207 and the capacitance value of the super capacitor C225 are both 150F.
10. The system for testing the super capacitor circuit as claimed in claim 5, wherein the voltage conversion chip N106 is a DCDC voltage conversion chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121192307.8U CN215986357U (en) | 2021-05-31 | 2021-05-31 | Test system of super capacitor circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121192307.8U CN215986357U (en) | 2021-05-31 | 2021-05-31 | Test system of super capacitor circuit |
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