CN215897375U

CN215897375U - Dual-power switching circuit

Info

Publication number: CN215897375U
Application number: CN202121683719.1U
Authority: CN
Inventors: 黄小刚; 殷旭东
Original assignee: Qingdao Ruiweishen Information Technology Co ltd
Current assignee: Qingdao Ruiweishen Information Technology Co ltd
Priority date: 2021-07-20
Filing date: 2021-07-20
Publication date: 2022-02-22
Anticipated expiration: 2031-07-20

Abstract

The utility model discloses a double-power-supply switching circuit, which mainly comprises the following components: the power supply detection circuit comprises a power supply A input port P1, a power supply B input port P2, a power supply output port P3, a PMOS tube Q1, a PMOS tube Q2, a PMOS tube Q4, a PMOS tube Q5, a PMOS tube Q6, an NMOS tube Q3, an NMOS tube Q7, a double diode SD1, a double diode SD2, a double diode SD3, a key switch K1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a ceramic chip capacitor C1 and a power supply detection chip U1, wherein the upper end of a pin 1 of the power supply A input port P1, the upper right end of the double diode SD1 and the upper end of the resistor R1 are all connected with a source electrode of the PMOS tube Q1. The utility model can realize that the input voltage and the output voltage have small voltage drop and small consumption, is very suitable for occasions powered by batteries and can realize seamless switching of two power supplies.

Description

Dual-power switching circuit

Technical Field

The utility model relates to the technical field of power supply switching, in particular to a dual-power supply switching circuit.

Background

With the development of the internet of things and portable equipment, more and more electronic devices need two power supplies, wherein one power supply is used as a normal power supply (hereinafter referred to as a power supply A) and the other power supply is used as a standby power supply (hereinafter referred to as a power supply B). When the power supply A is powered down, the power supply B can be in seamless connection to ensure normal operation of the equipment. Engineers typically implement this approach in a diode competitive manner when power a is slightly higher than power B, which has three disadvantages:

(1) the voltage drop of the diode can reduce the output voltage to a certain extent;

(2) the heat loss of the diode causes power to be wasted, which is unacceptable for battery powered devices;

(3) for equipment with larger power consumption, a heat dissipation device needs to be additionally arranged on the diode, otherwise, the reliability of the diode is influenced by heat generation.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that the defects in the prior art are overcome, and discloses a dual-power switching circuit which can realize that input and output voltages have small voltage drop and low consumption, is very suitable for occasions powered by batteries and can realize seamless switching of two power supplies.

The technical scheme adopted by the utility model for solving the technical problems is as follows: a double-power-supply switching circuit comprises a power supply A input port P, a power supply B input port P, a power supply output port P, a PMOS tube Q, an NMOS tube Q, a double diode SD, a key switch K, a resistor R, a ceramic capacitor C and a power supply detection chip U, wherein a pin 1 of the power supply A input port P, the upper right end of the double diode SD and the upper end of the resistor R are connected with a source electrode of the PMOS tube Q, a pin 2 of the power supply A input port P is grounded, the lower right end of the double diode SD and the pin 1 of the power supply B input port P are connected with a source electrode of the PMOS tube Q, the left end of the double diode SD is connected with the upper end of the key switch K, the lower end of the key switch K is connected with the upper left end of the double diode SD, the lower left end of the double diode SD is connected with an input output port I/O of a controller, pin 2 of an input port P2 of the power supply B is grounded, the right end of the double diode SD2 and the upper end of the resistor R5 are connected with the gate of the NMOS Q7, the lower end of the resistor R7 and the drain of the NMOS Q7 are grounded, the lower end of the resistor R7, the gate of the PMOS Q7, the lower end of the resistor R7 and the gate of the PMOS Q7 are connected with the source of the NMOS Q7, the drain of the PMOS Q7 and the upper end of the resistor R7 are connected with the source of the PMOS Q7, the drain of the PMOS Q7, the upper left end of the double diode SD 7 are connected with the drain of the PMOS Q7, the left ends of the gate of the PMOS Q7 and the resistor R7 are connected with the source of the NMOS Q7, the drain of the NMOS Q7 is grounded, the source of the PMOS Q7, the source of the resistor R7, the right end of the resistor R7 and the resistor R7 are connected with the right end of the power supply Q7, the P7 and the drain of the PMOS Q7 are connected with the power supply Q7, the power output end P3 pin 2 is grounded, the NMOS tube Q3 grid, the left end of the resistor R3 and the grid of the PMOS tube Q6 are all connected with a power detection chip U1 pin 1, the lower end of the double diode SD3 is connected with a power detection chip U1 pin 3, and the power detection chip U1 pin 2 is grounded.

In a preferred embodiment of the present invention, the voltage at pin 1 of the P1 input port of power supply a is higher than the voltage at pin 1 of the P2 input port of power supply B.

In a preferred embodiment of the present invention, the power detection chip U1 is a HX61Cxx chip.

In a preferred embodiment of the present invention, the lower left end of the double diode SD2 is connected to a microcontroller.

The utility model reduces the self power consumption of the whole circuit by utilizing the low loss and low voltage drop of the MOS tube conduction; the reliability and rapidity of power supply switching are ensured by using the hysteresis characteristic of the voltage detection chip; because of the parasitic capacitance of the MOS tube, the state of the MOS tube always passes through the amplification region during switching, which may cause short-time (generally us-level) drop of output voltage, the utility model can prevent the situation by utilizing the characteristic that the voltage at two ends of the capacitor can not suddenly change, so that the output voltage is smoothly transited at the switching moment; the utility model can complete the switching only by slightly increasing the voltage of the power supply A to 0.3v higher than the voltage of the power supply B.

The working principle of the utility model is as follows:

(1) when a power supply A and a power supply B exist simultaneously, a key switch K1 is pressed, current passes through a double diode SD1 and a double diode SD2 to enable an NMOS tube Q7 to be conducted, a PMOS tube Q1, a PMOS tube Q4 and a PMOS tube Q5 (the drain-source voltage drop is about 0v) are all conducted, the power supply A and the power supply B enter the input end of a power supply detection chip U1 through a double diode SD3, the power supply A and the power supply B are in a diode state, the power supply A voltage is higher than the monitoring voltage of U1, the power supply B voltage is lower than the monitoring voltage of U1, the power supply detection chip U1 outputs high level, an NMOS tube Q3 is conducted to enable a PMOS tube Q2 to be conducted, the PMOS tube Q6 is in a diode state, the on resistances of the PMOS tube Q6 and the PMOS tube Q1 and the PMOS tube Q2 are usually dozens of m, the output voltage of the power supply output end P3 is approximately equal to the power supply A voltage, and the I/O of the double diode 2 is set to be at high level after a system controller (not shown in the figure) is started, at this time, the key switch K1 is released, and the power supply output end P3 continuously supplies power.

(2) When the voltage of the power supply A is lower than the detection voltage of the power supply detection chip U1, the power supply detection chip U1 outputs a low level, the NMOS transistor Q3 is cut off, so that the PMOS transistor Q2 is turned off, the PMOS transistor Q6 is turned on, and the voltage of the output end of the power supply output end P3 is approximately equal to the voltage of the power supply B; usually, due to a parasitic capacitance between the NMOS transistor Q3 and the PMOS transistor Q2 GS (gate and source), there is a certain delay (this time is usually us-level) when the MOS transistor is turned on, and since the voltage across the chip capacitor C1 cannot suddenly change, the output voltage at the power output terminal P3 is guaranteed to be smooth at the switching moment.

(3) When the power supply B is not connected with the system, the current enables the NMOS tube Q7 to be conducted through the double diode SD1 and the double diode SD2, the PMOS tube Q1 (the drain-source voltage drop is about 0v) is conducted, the power supply A enters the input end of the power supply detection chip U1 through the double diode SD3, the power supply detection chip U1 outputs high level due to the fact that the voltage of the power supply A is higher than the monitoring voltage of U1, the NMOS tube Q3 is conducted to enable the PMOS tube Q2 to be conducted, the body diode of the PMOS tube Q6 is in a reverse cut-off state, the conducting resistance of the PMOS tube Q2 is usually dozens of m omega, the voltage of the power supply output end P3 output end voltage is approximately equal to the power supply A voltage, after the system controller is started, the I/O at the position of the double diode SD2 is set to be high level, at the time, the key switch K1 is released, and the power supply is continuously supplied to the output end of the power supply output end P3.

Compared with the prior art, the utility model has the following advantages: the voltage input and output can be realized to have small voltage drop, the self has small consumption, the power supply circuit is very suitable for occasions powered by batteries, and the seamless switching of two power supplies can be realized.

Drawings

Fig. 1 is a schematic circuit diagram of the present invention.

Description of reference numerals:

p1: power supply a input port, P2: power supply B input port, P3: power supply output terminals, Q1, Q2, Q4, Q5, Q6: PMOS transistor, Q3, Q7: NMOS tube, SD1, SD2, SD 3: double diode, K1: key switches, R1, R2, R3, R4, R5: resistance, C1: chip capacitance, I/O: controller input-output port, U1: and a power supply detection chip.

Detailed Description

The following description of the embodiments of the present invention refers to the accompanying drawings and examples:

it should be noted that the structures, proportions, sizes, and other dimensions shown in the drawings and described in the specification are only for the purpose of understanding and reading the present disclosure, and are not intended to limit the scope of the present disclosure, which is defined by the following claims, and any modifications of the structures, changes in the proportions and adjustments of the sizes, without affecting the efficacy and attainment of the same, are intended to fall within the scope of the present disclosure.

In addition, the terms "upper", "lower", "left", "right", "middle" and "one" used in the present specification are for clarity of description, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not to be construed as a scope of the present invention.

As shown in fig. 1, which illustrates an embodiment of the present invention, as shown in the figure, the dual power switching circuit disclosed in the present invention includes a power a input port P1, a power B input port P1, a power output port P1, a PMOS transistor Q1, an NMOS transistor Q1, a dual diode SD1, a key switch K1, a resistor R1, a ceramic chip capacitor C1 and a power detection chip U1, where a pin 1 of the power a input port P1, an upper right end SD of the dual diode SD1 and an upper end of the resistor R1 are all connected to a source of the PMOS transistor Q1, a pin 2 of the power a P1 is grounded, a lower end of the dual diode P1 and a pin SD1 of the power B1 are all connected to the left end of the dual diode P1, and the upper end of the key switch 1 is connected to the left end of the PMOS transistor Q1, and the left end of the dual diode 1 is connected to the left end 1, the left lower end of the double diode SD2 is connected with an I/O (input/output) port of a controller, a P2 pin 2 of an input port of a power supply B is grounded, the right end of the double diode SD2 and the upper end of the resistor R5 are connected with a grid electrode of an NMOS (N-channel metal oxide semiconductor) tube Q7, the lower end of the resistor R5 and the drain electrode of the NMOS tube Q7 are grounded, the lower end of the resistor R1, the grid electrode of a PMOS tube Q1, the grid electrode of the PMOS tube Q4, the lower end of the resistor R4 and the grid electrode of the PMOS tube Q4 are connected with a source electrode of the NMOS tube Q4, the drain electrodes of the PMOS tube Q4 and the resistor R4 are connected with a source electrode of the PMOS tube Q4, the drain electrodes of the PMOS tube Q4, the right upper end of the double diode SD 4 and the left end of the ceramic chip capacitor C4 are connected with a drain electrode of the PMOS tube Q4, the drain electrodes of the PMOS tube Q4 and the right end of the PMOS tube Q4 are connected with a drain electrode of the PMOS tube 4, the drain electrode of the PMOS tube Q4 and the drain electrodes of the NMOS tube R4, the drain electrodes of the PMOS tube Q4 are connected with a drain electrode of the NMOS tube Q4, the drain electrode of the PMOS tube Q4, the resistor R4, the drain electrodes of the NMOS tube 72 and the right end of the drain electrodes of the PMOS tube Q4, the PMOS tube R4 are connected with a drain electrodes of the NMOS tube Q4, the drain electrodes of the NMOS tube 72, the drain electrodes of the PMOS tube R4, the drain electrodes of the PMOS tube Q4, the drain electrodes of the PMOS tube 72 and the drain electrodes of the right end of the PMOS tube R4 are connected with a drain electrodes of the NMOS tube Q4, the drain electrodes of the PMOS tube Q4, the NMOS tube R4, the drain electrodes of the NMOS tube R4 are connected with a drain electrodes of the NMOS tube Q4, and the NMOS tube R4, the PMOS tube R4, the NMOS tube R4, and the right end of the drain electrodes of the NMOS tube R4 are connected with a drain electrodes of the NMOS tube Q4, and the NMOS tube R4 are connected with a drain electrodes of the NMOS tube, Ceramic chip electric capacity C1 right-hand member and PMOS pipe Q6 source all are connected with power output end P3 pin 1, power output end P3 pin 2 ground connection, NMOS pipe Q3 grid, resistance R3 left end and PMOS pipe Q6 grid all are connected with power detection chip U1 pin 1, double diode SD3 lower extreme is connected with power detection chip U1 pin 3, power detection chip U1 pin 2 ground connection.

Preferably, the voltage at pin 1 of the power supply A input port P1 is higher than the voltage at pin 1 of the power supply B input port P2.

Preferably, the power detection chip U1 is a HX61Cxx series chip.

Preferably, the lower left end of the double diode SD2 is connected with a microcontroller.

The utility model reduces the self power consumption of the whole circuit by utilizing the low loss and low voltage drop of the MOS tube conduction; the reliability and rapidity of power supply switching are ensured by using the hysteresis characteristic of the voltage detection chip; because of the parasitic capacitance of the MOS tube, the state of the MOS tube always passes through the amplification region during switching, which may cause short-time (generally us-level) drop of output voltage, the utility model can prevent the situation by utilizing the characteristic that the voltage at two ends of the capacitor can not suddenly change, so that the output voltage is smoothly transited at the switching moment; the present invention requires that the voltage of power supply a be 0.3v higher than the voltage of power supply B.

The working principle of the utility model is as follows:

(1) when a power supply A and a power supply B exist simultaneously, a key switch K1 is pressed, current passes through a double diode SD1 and a double diode SD2 to enable an NMOS tube Q7 to be conducted, a PMOS tube Q1, a PMOS tube Q4 and a PMOS tube Q5 (the grid voltage is about 0v) are all conducted, the power supply A and the power supply B enter an input end of a power supply detection chip U1 through a double diode SD3, the power supply B voltage is lower than the monitoring voltage of U1 because the power supply A voltage is higher than the monitoring voltage of U1, the power supply detection chip U1 outputs high level, the NMOS tube Q3 is conducted to enable a PMOS tube Q2 to be conducted, the PMOS tube Q6 is in a diode state, the PMOS tube Q6 is reversely cut off due to the fact that the power supply A is slightly higher than the power supply B, the body diode of the PMOS tube Q6 is reversely cut off, the conduction resistance of the PMOS tube Q1 and the PMOS tube Q2 is usually dozens of m, the output voltage of the power supply output end P3 is about equal to the power supply A voltage, the I/O2 is put at the position of the power supply output voltage after a system controller (not shown in the figure) is started, at this time, the key switch K1 is released, and the power supply output end P3 continuously supplies power.

Although the preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the spirit of the present invention.

Many other changes and modifications can be made without departing from the spirit and scope of the utility model. It is to be understood that the utility model is not to be limited to the specific embodiments, but only by the scope of the appended claims.

Claims

1. A dual power switching circuit is characterized in that: the power supply device comprises a power supply A input port P1, a power supply B input port P2, a power supply output port P3, a PMOS tube Q1, a PMOS tube Q2, a PMOS tube Q4, a PMOS tube Q5, a PMOS tube Q6, an NMOS tube Q3, an NMOS tube Q7, a double diode SD1, a double diode SD2, a double diode SD3, a key switch K1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a ceramic chip capacitor C1 and a power supply detection chip U1, wherein the upper ends of a pin 1 of the power supply A input port P1, the upper right end of the double diode SD1 and the resistor R1 are all connected with the source of the PMOS tube Q1, the power supply A input port P1 pin SD2 SD, the right lower end of the double diode SD1 and the power supply B input port P2 pin 1 are all connected with the source of the PMOS tube Q4, the left end of the double diode SD1 is connected with the upper end of the key switch K1, the lower end of the double diode K1 is connected with the key switch K1, the upper end of the double diode 1 and the double diode 1 is connected with the upper end of the double diode 1I/1, pin 2 of an input port P2 of the power supply B is grounded, the right end of the double diode SD2 and the upper end of the resistor R5 are connected with the gate of the NMOS Q7, the lower end of the resistor R7 and the drain of the NMOS Q7 are grounded, the lower end of the resistor R7, the gate of the PMOS Q7, the lower end of the resistor R7 and the gate of the PMOS Q7 are connected with the source of the NMOS Q7, the drain of the PMOS Q7 and the upper end of the resistor R7 are connected with the source of the PMOS Q7, the drain of the PMOS Q7, the upper left end of the double diode SD 7 are connected with the drain of the PMOS Q7, the left ends of the gate of the PMOS Q7 and the resistor R7 are connected with the source of the NMOS Q7, the drain of the NMOS Q7 is grounded, the source of the PMOS Q7, the source of the resistor R7, the right end of the resistor R7 and the resistor R7 are connected with the right end of the power supply Q7, the P7 and the drain of the PMOS Q7 are connected with the power supply Q7, the power output end P3 pin 2 is grounded, the NMOS tube Q3 grid, the left end of the resistor R3 and the grid of the PMOS tube Q6 are all connected with a power detection chip U1 pin 1, the lower end of the double diode SD3 is connected with a power detection chip U1 pin 3, and the power detection chip U1 pin 2 is grounded.

2. The dual power switching circuit of claim 1, wherein: the power A input port P1 pin 1 voltage is higher than the power B input port P2 pin 1 voltage.

3. The dual power switching circuit of claim 1, wherein: the power supply detection chip U1 adopts HX61CxX series chips.

4. The dual power switching circuit of claim 1, wherein: the lower left end of the double diode SD2 is connected with the microcontroller.