CN215773050U

CN215773050U - Parallel CMOS low noise gate amplifier circuit

Info

Publication number: CN215773050U
Application number: CN202022867865.1U
Authority: CN
Inventors: 赵永春; 高志祥
Original assignee: Nanjing China Electronics Panda Crystal Technology Corp
Current assignee: Nanjing China Electronics Panda Crystal Technology Corp
Priority date: 2020-12-04
Filing date: 2020-12-04
Publication date: 2022-02-08
Anticipated expiration: 2030-12-04

Abstract

The utility model relates to a parallel CMOS low-noise gate amplifier circuit which is characterized by comprising three resistors, four capacitors, two inductors and four chips, wherein one resistor, one inductor and the four chips form an impedance matching connection circuit, the four chips, the three capacitors, one resistor and the two inductors form a T-shaped filter circuit, and one resistor and the four chips form a feedback circuit. The advantages are that: 1) the bottom noise of the amplifier is reduced to-180 dBc/Hz; 2) the design is reasonable, the structure is simple, the middle frequency band is simple and convenient to debug, the stability is good, the reliability is high, and the use is flexible; 3) the gain can reach 17 dB; 4) ultra low noise figure, NF <0.5 dB.

Description

Parallel CMOS low noise gate amplifier circuit

Technical Field

The utility model relates to a parallel CMOS low-noise gate amplifier circuit, belonging to the technical field of low-noise crystal oscillators.

Background

In a traditional crystal oscillator circuit, a final-stage amplifying circuit of the traditional crystal oscillator circuit is commonly provided with a triode amplifying circuit and a gate amplifying circuit, the triode amplifying circuit is also commonly provided with three forms of a cascode and a cascode, each different combination form needs different static working points and alternating current feedback, circuit noise is greatly influenced by emitter current, input and output impedance matching and power supply, the traditional gate amplifying circuit is limited by device performance, although output noise is good, output power is limited, a triode has more device correlation factors, and device parameter debugging is complicated in order to achieve ideal signal-to-noise ratio and gain.

In some application occasions, the output power requirement of the crystal oscillator is more than 15dBm, the bottom noise requirement is as low as-180 dBc, most gains can meet most of low-noise amplifier chips on the market, but the bottom noise is deteriorated a lot after signal amplification, which is more than 10dB, the signal loss is serious, and the improvement of the sensitivity of a channel unit is not facilitated.

SUMMERY OF THE UTILITY MODEL

The utility model provides a parallel CMOS low noise gate amplifier circuit, which aims to solve the problems in the prior art and is reasonable in design, simple in structure, simple in middle frequency band and debugging, good in stability and reliability and flexible to use.

The technical solution of the utility model is as follows: the parallel CMOS low-noise gate amplifier circuit comprises three resistors, four capacitors, two inductors and four chips, wherein one resistor, one inductor and the four chips form an impedance matching connection circuit, the four chips, the three capacitors, one resistor and the two inductors form a T-shaped filter circuit, and one resistor and the four chips form a feedback circuit.

The three resistors are a first feedback resistor R1, a second feedback resistor R2 and a third coupling resistor R3, the four capacitors are a first coupling capacitor C1, a second coupling capacitor C2, a third coupling capacitor C3 and a fourth coupling capacitor C4, the two inductors are a first inductor L1 and a second inductor L2, the four chips are a first chip IC1, a second chip IC2, a third chip IC3 and a fourth chip IC4, and the four chips are connected in parallel; the impedance matching connection circuit is formed by the first feedback resistor R1, the first coupling capacitor C1 and the four chips, the T-shaped filter circuit is formed by the four chips, the second coupling capacitor C2, the third coupling capacitor C3, the third coupling resistor R3, the first inductor L1, the second inductor L2 and the fourth coupling capacitor C4, and the feedback circuit is formed by the second feedback resistor R2 and the four chips.

In the impedance matching connection circuit, one end of a first coupling capacitor C1 is connected with the 1 st pin and the 3 rd pin of the input ends of four chips, the other end of the first coupling capacitor C1 is connected with one end of a first feedback resistor R1, the other end of the first feedback resistor R1 is grounded, and the input end of the circuit is connected with a first coupling capacitor C1 and a second feedback resistor R2.

Pins

4 and 6 of output ends of four chips in the T-type filter circuit are connected with one end of a second coupling capacitor C2, the other end of the second coupling capacitor C2 is connected with one end of a third coupling resistor R3 in series, the other end of the third coupling resistor R3 is connected with one end of a first inductor L1, the other end of the first inductor L1 is connected with one end of a second inductor L2 and one end of a third coupling capacitor C3, the other end of the third coupling capacitor C3 is grounded, the other end of the second inductor L2 is connected with one end of a fourth coupling capacitor C4, and the other end of the fourth coupling capacitor C4 is connected with a circuit output end.

Pins 1 and 3 at the input ends of the four chips in the feedback circuit are connected with one end of a second feedback resistor R2, and the other end of the second feedback resistor R2 is connected with

pins

4 and 6 at the output ends of the four chips.

The four chips are connected in parallel, the 2 nd pin of the four chips is grounded, and the 5 th pin of the four chips is connected with a power supply.

The utility model has the beneficial effects that:

1) the bottom noise of the amplifier is reduced to-180 dBc/Hz;

2) the design is reasonable, the structure is simple, the middle frequency band is simple and convenient to debug, the stability is good, the reliability is high, and the use is flexible;

3) the gain can reach 17 dB;

4) ultra low noise figure, NF <0.5 dB.

Drawings

Figure 1 is a schematic diagram of a parallel CMOS low noise gate amplifier circuit.

In the figure, R1 and R2 are feedback resistors, R3 is a coupling resistor, C1-C4 are coupling capacitors, and the IC is a chip.

Detailed Description

The technical solution of the present invention is further explained with reference to the accompanying drawings.

Compared with the schematic diagram of a parallel CMOS low noise gate amplifier shown in figure 1, the parallel CMOS low noise gate amplifier circuit mainly comprises an input impedance matching connection circuit which is integrated with double inverters and is connected with pins 1 and 3 of an IC1, an IC2, an IC3 and an IC4, an output circuit which is connected with

pins

4 and 6 of the IC1, the IC2, the IC3 and the IC4, and a feedback resistor R2 which is connected with the

pins

1, 3, 4 and 6 of the IC4, wherein the input impedance matching circuit comprises a coupling capacitor C1 and a resistor R1, and the output circuit comprises a coupling capacitor C2 and a coupling resistor R3 which are connected in series, and then a T-shaped filter which is formed by connecting one end of the T-shaped filter with inductors L1, L2 and C3 is output through a coupling capacitor C4.

The integrated double-inverter IC1, IC2, IC3 and IC4 work in parallel, the common input ends 1 and 3 of each independent CMOS gate are connected together, the output ends 4 and 6 are also connected together in parallel, the driving current is large, the small fluctuation of the power supply voltage has no influence on the driving current, the influence of the temperature and the process deviation on the reliability of the operation of the integrated double-inverter IC is much smaller than that of an analog circuit, so that the integrated double-inverter IC1, the integrated double-inverter IC2, the integrated double-inverter IC3 and the integrated double-inverter IC4 can obtain extremely low noise background and large gain, and the characteristics of a digital circuit are fully utilized.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the utility model, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Example 1

A parallel CMOS low noise gate amplifier circuit mainly comprises an impedance matching circuit which integrates an IC1, an IC2, an IC3 and an IC4 of a double-inverter and is connected with 1 pin and 3 pins of the IC, wherein the model of the IC1, the IC2, the IC3 and the IC4 of the double-inverter used in the embodiment is NC7WZU 04. The circuit comprises a T-shaped filter circuit connected with pins IC1, IC2, IC3, IC 44 and 6, and a feedback resistor R2 connected with pins IC1, IC2, IC3, IC 41, 3, 4 and 6.

The impedance matching connection circuit comprises C1 connected with pins of IC1, IC2, IC3 and IC 41 and 3, and is connected with R1 with the other end grounded. The T-shaped filter circuit comprises C2 connected with pins IC1, IC2, IC3, IC 44 and 6, is connected with L1 after being connected with R3 in series, is connected with L2 through C3 with one end grounded, and is connected with C4 to output. The feedback circuit comprises R2 connected with pins IC1, IC2, IC3, IC 41 and 3, and one end of the feedback circuit is connected with pins IC1, IC2, IC3, IC 44 and IC 6.

Claims

1. The parallel CMOS low-noise gate amplifier circuit is characterized by comprising three resistors, four capacitors, two inductors and four chips, wherein one resistor, one inductor and the four chips form an impedance matching connection circuit;

the three resistors are a first feedback resistor (R1), a second feedback resistor (R2) and a third coupling resistor (R3), the four capacitors are a first coupling capacitor (C1), a second coupling capacitor (C2), a third coupling capacitor (C3) and a fourth coupling capacitor (C4), the two inductors are a first inductor (L1) and a second inductor (L2), the four chips are a first chip (IC 1), a second chip (IC 2), a third chip (IC 3) and a fourth chip (IC 4), and the four chips are connected in parallel; the impedance matching connection circuit comprises a first feedback resistor (R1), a first coupling capacitor (C1) and four chips, a T-shaped filter circuit comprises the four chips, a second coupling capacitor (C2), a third coupling capacitor (C3), a third coupling resistor (R3), a first inductor (L1), a second inductor (L2) and a fourth coupling capacitor (C4), and a feedback circuit comprises the second feedback resistor (R2) and the four chips;

in the impedance matching connection circuit, one end of a first coupling capacitor (C1) is connected with the 1 st pin and the 3 rd pin of the input ends of four chips, the other end of the first coupling capacitor (C1) is connected with one end of a first feedback resistor (R1), the other end of the first feedback resistor (R1) is grounded, and the input end of the circuit is connected with a first coupling capacitor (C1) and a second feedback resistor (R2);

the 4 th pin and the 6 th pin of output ends of four chips in the T-shaped filter circuit are connected with one end of a second coupling capacitor (C2), the other end of the second coupling capacitor (C2) is connected with one end of a third coupling resistor (R3) in series, the other end of the third coupling resistor (R3) is connected with one end of a first inductor (L1), the other end of the first inductor (L1) is connected with one end of a second inductor (L2) and one end of a third coupling capacitor (C3), the other end of the third coupling capacitor (C3) is grounded, the other end of the second inductor (L2) is connected with one end of a fourth coupling capacitor (C4), and the other end of the fourth coupling capacitor (C4) is connected with a circuit output end.

2. The parallel CMOS low noise gate amplifier circuit of claim 1, wherein the input terminals 1 st pin and 3 rd pin of four chips in said feedback circuit are connected to one end of the second feedback resistor (R2), and the other end of the second feedback resistor (R2) is connected to the output terminals 4 th pin and 6 th pin of four chips.

3. The parallel CMOS low noise gate amplifier circuit of claim 1, wherein said four chips are connected in parallel, with pin 2 of the four chips connected to ground and pin 5 connected to a power supply.