CN215731674U - Power semiconductor device with gate oxide optimized structure - Google Patents
Power semiconductor device with gate oxide optimized structure Download PDFInfo
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- CN215731674U CN215731674U CN202120679666.XU CN202120679666U CN215731674U CN 215731674 U CN215731674 U CN 215731674U CN 202120679666 U CN202120679666 U CN 202120679666U CN 215731674 U CN215731674 U CN 215731674U
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Abstract
The utility model relates to the technical field of power semiconductor devices, in particular to a power semiconductor device with a gate oxide optimization structure, which comprises a semiconductor substrate, wherein an epitaxial layer is arranged on the semiconductor substrate, a plurality of grooves are formed in the epitaxial layer from the top downwards, a first dielectric layer is arranged in each groove, a first conductive material is arranged in each first dielectric layer, a second dielectric layer is arranged on part of each first dielectric layer and the corresponding first conductive material in a covering manner, an oxide layer is arranged on each second dielectric layer, and a second conductive material is arranged on each oxide layer. The yield of the power semiconductor device is improved, and the risk of reliability is reduced.
Description
Technical Field
The utility model relates to the technical field of power semiconductor devices, in particular to a power semiconductor device with a gate oxide optimization structure.
Background
Power semiconductor devices, also known as power electronic devices, include power diodes, thyristors, VDMOS (vertical double-diffused metal oxide semiconductor) field effect transistors, LDMOS (lateral-diffused metal oxide semiconductor) field effect transistors, IGBTs (insulated gate bipolar transistors), and the like. The VDMOS field effect transistor includes a source region and a drain region formed on opposite surfaces of a semiconductor substrate, and in a high-frequency operation of the power semiconductor device, a current flows mainly along a longitudinal direction of the semiconductor substrate in an on state, and lower conduction loss and switching loss are important indexes for evaluating the device performance.
On the basis of the VDMOS field effect transistor, a trench type MOS field effect transistor has been further developed, in which a gate conductor is formed in a trench, and a gate dielectric is formed on a trench sidewall to separate the gate conductor and a semiconductor layer to form a channel in the semiconductor layer in a direction along the trench sidewall. The Trench (Trench) process changes the channel from horizontal to vertical, eliminates the response of parasitic JFET resistance of a planar structure, and greatly reduces the size of a cell. On the basis, the cell density is increased, the total width of a channel in a chip in unit area is improved, the channel width-length ratio of a device on a unit silicon chip is increased, so that the current is increased, the on-resistance is reduced, and related parameters are optimized, and the goal that a smaller-sized die has higher power and higher performance is realized. Meanwhile, the shielding conductor extends to the lower part of the grid conductor, the insulating layer and the semiconductor layer are separated from each other and are connected with the source electrode together and are grounded together, so that a charge balance effect is introduced, a Reduced Surface Field (RESURF) effect is achieved in the vertical direction of the power semiconductor device, the withstand voltage is improved through the thicker shielding dielectric layer and the deeper groove depth, and meanwhile, the on-resistance Rdson is further Reduced, so that the conduction loss is Reduced.
A schematic diagram of a prior art power semiconductor device is shown in fig. 5. By way of example, the power semiconductor device is a trench-gate MOSFET power semiconductor device.
As shown in fig. 5, the trench-gate MOSFET power semiconductor device includes a plurality of trenches 11 in an epitaxial layer 10b on a semiconductor substrate 10 a. A first dielectric layer 12 formed in the trench, a first conductive material 13, and a gate oxide 14, a second conductive material 15 formed on top of the trench 11. P-type doping 16 and N-type doping 17 are formed on the epitaxy and a third dielectric layer 18, contact holes and a metal layer 21 are formed on the epitaxy and the top of the trench, finally forming metal electrodes 22, 23, 24.
Fig. 6 to 7 respectively show a partially enlarged schematic structural view of the power semiconductor device shown in fig. 5.
FIG. 6 is an enlarged view of the area 30 in FIG. 5, in which the oxide layer between the first conductive material 13 and the second conductive material 15 is 14b, and the thickness d2 ≧ the thickness d1 of the trench sidewall gate oxide 14. Where the second conductive material 15 is elevated above the epitaxial surface, the metal electrode 24 is connected to the second conductive material 15 by a via hole having a bottom at a distance d3 from the oxide layer 14b on top of the first conductive material. If d3 is smaller, the risk of GS leakage and even GS short circuit is likely to occur. Meanwhile, in the split-gate power semiconductor device, the gate-source capacitance Cgs is influenced by the thickness of an oxide layer among polycrystals, the thicker the oxide layer is, the smaller the capacitance Cgs is, and the faster the switching speed of the device is, so that how to increase the thickness of the oxide layer 14b to the maximum extent, and optimizing the parameter performance of the device is the content of research of the personnel in the industry.
As shown in fig. 7, the enlarged schematic view of the trench top structure, wherein for the shallow junction process, the filling depth L of the second conductive material is usually short, so that in the actual process, especially in the process requiring a thick first dielectric layer, the second conductive material is usually formed by dry etching, which results in a steep boundary at the bottom of the trench sidewall near the bottom of the silicon substrate, and the oxidation rate is slow according to the crystallographic principle in the subsequent oxidation growth process, as shown in the area labeled as 40 in fig. 7, the oxide layer d4 formed at the bottom of the trench sidewall will be thinner than the oxide layer at the rest positions of the sidewall, so that the bottom of the trench sidewall is easily a weak area of gate oxide, the electric field is easily concentrated, the voltage resistance between GS is affected, and the risks of GS leakage and gate oxide breakdown are easily generated.
How to increase the thickness of the oxide layer between two layers of polycrystals, the smaller the capacitance Cgs is, the faster the switching speed of the device, and the lower cost of the metal electrode wiring mode of the second conductive material is improved, so that the GS abnormity caused by the metal wiring mode between GS is avoided. The thickness of an oxide layer formed at the bottom of the side wall of the groove is further improved, the voltage resistance between GS is optimized, the risk of leakage short circuit and even gate oxide breakdown between GS is reduced, and the method is the content of research of personnel in the industry.
SUMMERY OF THE UTILITY MODEL
Aiming at the defects in the prior art, the utility model provides a power semiconductor device with a gate oxide optimization structure, and aims to solve the technical problem of how to optimize the structure of the conventional product so as to reduce the risks of short circuit and electric leakage between a shielding conductor and a gate conductor and optimize capacitance parameters between GS (gate-to-gate) conductors, so that the yield of the power semiconductor device is improved, and the reliability risk is reduced.
In order to solve the technical problems, the technical scheme provided by the utility model is as follows: the power semiconductor device with the gate oxide optimization structure comprises a semiconductor substrate, wherein an epitaxial layer is arranged on the semiconductor substrate, a plurality of grooves are formed in the epitaxial layer from the top to the bottom, a first medium layer is arranged in each groove, a first conductive material is arranged in each first medium layer, a second medium layer is arranged on part of the first medium layer and the first conductive material in a covering mode, an oxide layer is arranged on each second medium layer, a second conductive material is arranged on each oxide layer, gate oxide wraps the second conductive material, and the epitaxial layer is covered by the gate oxide;
a first source region and a second source region which are layered up and down are arranged between two adjacent partial trenches;
the gate oxide is provided with a third medium layer, a first conductive window, a second conductive window and a third conductive window are formed in the third medium layer, the bottom end of the first conductive window extends into the first conductive material, the bottom end of the second conductive window extends into the two first source regions and the second source region, the bottom end of the third conductive window extends into the second conductive material, a first metal electrode is arranged in the first conductive window, second metal electrodes are arranged in the two adjacent second conductive windows, and a third metal electrode is arranged in the third conductive window.
Furthermore, the semiconductor substrate is a monocrystalline silicon substrate doped to be N type, and the epitaxial layer is a monocrystalline silicon epitaxial layer doped to be N type.
Furthermore, the depth of the groove is 1-15 μm.
Furthermore, an arc-shaped structure is arranged at the joint of the second dielectric layer and the gate oxide, and the thickness of the groove at the arc-shaped structure is larger than that of the gate oxide.
Further, the thickness of the gate oxide is
Further, the thickness of the oxide layer is larger than that of the gate oxide.
Further, the second conductive material has a thickness of
Further, the first source region and the second source region are doped in a P-type manner and a N-type manner respectively.
Further, the depth of the first conductive window, the second conductive window and the third conductive window in the epitaxial layer is
The beneficial effect that this technical scheme brought is: according to the power semiconductor device with the gate oxide optimization structure, the contact holes can be formed in the two sides of the second conductive material in the groove and are led out through the metal electrodes, the abnormal risk of GS (gallium nitride) caused by a metal wiring process between GS (gallium nitride) is avoided, the risks of short circuit and electric leakage between the shielding conductor and the gate conductor are reduced, the capacitance parameter between GS is optimized, the yield of the power semiconductor device is improved, and the risk of reliability is reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description serve to explain the principles of the utility model and not to limit the utility model. In the drawings:
fig. 1 is a partial structural schematic view of a power semiconductor device having a gate oxide optimized structure according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a power semiconductor device having a gate oxide optimized structure according to an embodiment of the present invention including a second conductive material and a gate oxide;
FIG. 3 is a schematic diagram of a power semiconductor device with a gate oxide optimized structure including a conductive window in an embodiment of the utility model;
fig. 4 is a schematic structural diagram of a power semiconductor device having a gate oxide optimized structure according to an embodiment of the present invention including a metal electrode;
FIG. 5 is a schematic diagram of a prior art power semiconductor device;
FIG. 6 is a partially enlarged schematic view of FIG. 5;
FIG. 7 is another enlarged partial schematic view of FIG. 5;
in the figure: 101-a semiconductor substrate, 102-an epitaxial layer, 110-a trench, 120-a first dielectric layer, 130-a first conductive material, 136-a second dielectric layer, 141-an oxide layer, 150-a second conductive material, 140-a gate oxide, 170-a first source region, 160-a second source region, 180-a third dielectric layer, 201-a first conductive window, 202-a second conductive window, 203-a third conductive window, 211-a first metal electrode, 212-a second metal electrode, 213-a third metal electrode.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, and it should be understood that the preferred embodiments described herein are merely for purposes of illustration and explanation, and are not intended to limit the present invention.
As shown in fig. 1 to 4, the power semiconductor device with the gate oxide optimized structure comprises a semiconductor substrate 101, wherein an epitaxial layer 102 is arranged on the semiconductor substrate 101, the material of the semiconductor substrate 101 is III-V semiconductor such as GaAs, InP, GaN, SiC, and group IV semiconductor such as Si, Ge. The epitaxial layer 102 is provided with a plurality of trenches 110 from the top downwards, the depth of the trenches 110 is different for trench gate power semiconductor devices with different withstand voltage levels, and generally, for a split gate power semiconductor device, the deeper the depth of the trenches 110 is, the higher the withstand voltage degree of the device is.
A first dielectric layer 120 is disposed in the trench 110, and a first conductive material 130 is disposed in the first dielectric layer 120, wherein the first dielectric layer 120 may be made of an oxide and is formed by thermal oxidation or chemical vapor deposition CVD, the thermal oxidation includes hydrothermal oxidation HTO or selective reactive oxidation SRD, and the chemical vapor deposition CVD includes pressure chemical vapor deposition LPCVD or sub-atmospheric pressure chemical vapor deposition SACVD.
The first dielectric layer 120 serves as a management layer between the shielding conductor and the semiconductor substrate in the power semiconductor device, and for trench gate power semiconductor devices with different withstand voltage grades, the thickness of the insulating layer needs to be adjusted according to withstand voltage, depth of a trench and epitaxial concentration, and generally, the stronger the withstand voltage performance is, the thicker the thickness of the insulating layer needs to be.
It should be noted that there cannot be a gap or a void between the first conductive material 130 in the trench 110, otherwise there may be a parameter problem such as leakage, which may affect reliability.
A second dielectric layer 136 is disposed on a portion of the first dielectric layer 120 and the first conductive material 130 in a covering manner, an oxide layer 141 is disposed on the second dielectric layer 136, a second conductive material 150 is disposed on the oxide layer 141, a gate oxide 140 is wrapped outside the second conductive material 150, and the epitaxial layer 102 is covered by the gate oxide 140.
It should be noted that the second conductive material 150 in the trench 110 is not filled with any gap or void, which may cause leakage and other parameter problems, and thus reliability is affected.
A first source region 170 and a second source region 160 layered up and down are disposed between two partially adjacent trenches 110.
A third dielectric layer 180 is disposed on the gate oxide 140, and the third dielectric layer 180 may be formed by CVD including LPCVD or SACVD, to form one or more combinations of dielectric layers such as NSG/BPSG/PSG/SiN/SiON for isolating the device structure in epitaxy from the subsequent metal layers.
A first conductive window 201, a second conductive window 202 and a third conductive window 203 are formed in the third dielectric layer 180, and these conductive windows can be selectively formed through the third dielectric layer 180, the gate oxide 140 and a part of the epitaxial surface by photolithography and etching processes. In order to reduce the contact resistance, it is usually necessary to perform contact hole implantation and perform RTA, furnace annealing, and other processes after the contact hole.
The bottom end of the first conductive window 201 extends into the first conductive material 130 to form a shielded poly conductive window of the split gate. The bottom end of the second conductive window 202 extends into the two first source regions 170 and the second source region 160 to form a source conductive window of the split gate. The bottom end of the third conductive window 203 extends into the second conductive material 150 to form a gate conductive window of the split gate. A first metal electrode 211 is arranged in the first conductive window 201, second metal electrodes 212 are arranged in two adjacent second conductive windows 202, a third metal electrode 213 is arranged in the third conductive window 203, the metal electrodes are usually filled in contact holes by adopting metal materials such as MOCVD, PVD and the like or a plurality of combinations of metal materials such as Ti, TiN, W, AL, ALSI, ALCU, ALSICU and the like, and then metal wiring is formed by adopting photoetching and etching processes to realize conductive communication.
The structure is a front structure of the power semiconductor device, and a complete structure is formed after a series of subsequent processes such as thinning the back surface, forming a source electrode and a drain electrode on the front surface and the back surface respectively, scribing and the like.
Therefore, the power semiconductor device with the gate oxide optimization structure is designed, so that contact holes can be formed in the two sides of the second conductive material 150 in the groove 110 and are led out through the metal electrode, the abnormal risk of GS (ground leakage) caused by a metal wiring process between GS (ground leakage) is avoided, the risks of short circuit and electric leakage between the shielding conductor and the gate conductor are reduced, the capacitance parameter between GS is optimized, the yield of the power semiconductor device is improved, and the risk of reliability is reduced.
In the present embodiment, the semiconductor substrate 101 is a single crystal silicon substrate doped to N type, and the epitaxial layer 102 is a single crystal silicon epitaxial doped to N type.
In the present embodiment, the depth of the trench 110 is 1 to 15 μm.
In this embodiment, an arc-shaped structure is provided in the contact between the second dielectric layer 136 and the gate oxide 140, and the thickness of the trench 110 at the arc-shaped structure is greater than that of the gate oxide 140, so that the GS withstand voltage can be further improved, and the GS leakage can be reduced.
In the present embodiment, the thickness of the gate oxide 140 is
This protects the surface of epitaxial layer 102 and the internal structure of trench 110.
In the embodiment, the thickness of the oxide layer 141 is greater than that of the gate oxide 140, because in the process of growth and oxidation, an oxide layer will also grow in the top region of the first poly, and the remaining second dielectric layer 136 on the top of the first conductive material 130 is added, so that the oxide layer in the top region of the first poly is finally accumulated to form the oxide layer 141, which is generally thicker than the gate oxide 140 grown on the epitaxial layer and the sidewall of the trench 110, which can also improve the voltage resistance of the GS, and optimize the capacitance parameter between GS.
In the present embodiment, the second conductive material 150 has a thickness of
The second conductive material 150 is composed of in-situ doped polysilicon, the deposition temperature is 500-580 ℃, and the square resistance is 3-20 omega.
In this embodiment, the first source region 170 and the second source region 160 are respectively P-type doped and N-type doped, which are implanted by means of multiple ion implantations, and different types of doped regions are formed by selecting appropriate dopants, and then thermal annealing is performed to activate impurities, so as to form the body doped region of the device, and the required device structures such as PN junctions.
In this embodiment, the depth of the first conductive window 201, the second conductive window 202 and the third conductive window 203 in the epitaxial layer 102 is
This reduces the magnitude of the on-resistance and enhances EAS capabilities.
However, the present invention is not limited thereto, but may be applied to any type of trench type power semiconductor device. The power semiconductor device includes but is not limited to SGT device, IGBT device, TVS device, CMOS device, Bicmos device, MEMS device, schottky device, memory and other semiconductor devices.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the utility model. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. Power semiconductor device with gate oxide optimized structure, characterized by: the semiconductor device comprises a semiconductor substrate (101), wherein an epitaxial layer (102) is arranged on the semiconductor substrate (101), a plurality of grooves (110) are formed in the epitaxial layer (102) from the top to the bottom, a first dielectric layer (120) is arranged in each groove (110), a first conductive material (130) is arranged in each first dielectric layer (120), a second dielectric layer (136) covers part of the first dielectric layer (120) and the first conductive material (130), an oxide layer (141) is arranged on each second dielectric layer (136), a second conductive material (150) is arranged on each oxide layer (141), a gate oxide (140) wraps the second conductive material (150), and the gate oxide (140) covers the epitaxial layer (102);
a first source region (170) and a second source region (160) which are layered up and down are arranged between two partially adjacent trenches (110);
a third dielectric layer (180) is arranged on the gate oxide (140), a first conductive window (201), a second conductive window (202) and a third conductive window (203) are formed in the third dielectric layer (180), the bottom end of the first conductive window (201) extends into the first conductive material (130), the bottom end of the second conductive window (202) extends into the two first source regions (170) and the second source region (160), the bottom end of the third conductive window (203) extends into the second conductive material (150), a first metal electrode (211) is arranged in the first conductive window (201), a second metal electrode (212) is arranged in the two adjacent second conductive windows (202), and a third metal electrode (213) is arranged in the third conductive window (203).
2. The power semiconductor device with the gate oxide optimized structure of claim 1, wherein: the semiconductor substrate (101) is a monocrystalline silicon substrate doped to be N-type, and the epitaxial layer (102) is a monocrystalline silicon epitaxial doped to be N-type.
3. The power semiconductor device with the gate oxide optimized structure of claim 1, wherein: the depth of the groove (110) is 1-15 mu m.
4. The power semiconductor device with the gate oxide optimized structure of claim 1, wherein: an arc-shaped structure is arranged at the joint of the second dielectric layer (136) and the gate oxide (140) and the thickness of the groove (110) at the arc-shaped structure is larger than that of the gate oxide (140).
5. The power semiconductor device with the gate oxide optimized structure of claim 1, wherein: the thickness of the gate oxide (140) is
6. The power semiconductor device with the gate oxide optimized structure of claim 1, wherein: the thickness of the oxide layer (141) is larger than that of the gate oxide (140).
7. The power semiconductor device with the gate oxide optimized structure of claim 1, wherein: the second conductive material (150) has a thickness of
8. The power semiconductor device with the gate oxide optimized structure of claim 1, wherein: the first source region (170) and the second source region (160) are doped P-type and N-type, respectively.
9. The power semiconductor device with the gate oxide optimized structure of claim 1, wherein: the first conductive window (201), the second conductive window (202) and the third conductive window (203) are positioned at the depth of the epitaxial layer (102) in the range of
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113097311A (en) * | 2021-04-02 | 2021-07-09 | 杭州宏晟微电子有限公司 | Power semiconductor device with gate oxide optimization structure and manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113097311A (en) * | 2021-04-02 | 2021-07-09 | 杭州宏晟微电子有限公司 | Power semiconductor device with gate oxide optimization structure and manufacturing method |
| CN113097311B (en) * | 2021-04-02 | 2023-12-29 | 杭州宏晟微电子有限公司 | Power semiconductor device with gate oxide optimization structure and manufacturing method |
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