CN112928167A - Process-optimized power semiconductor device and method for producing the same - Google Patents

Process-optimized power semiconductor device and method for producing the same Download PDF

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CN112928167A
CN112928167A CN202110363338.3A CN202110363338A CN112928167A CN 112928167 A CN112928167 A CN 112928167A CN 202110363338 A CN202110363338 A CN 202110363338A CN 112928167 A CN112928167 A CN 112928167A
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groove
dielectric layer
trench
conductive material
semiconductor device
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陈龙
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Hangzhou Hongsheng Microelectronics Co ltd
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Hangzhou Hongsheng Microelectronics Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to a power semiconductor device with optimized process and a manufacturing method thereof, wherein the method comprises the steps of forming a groove in a semiconductor substrate with a first doping type, and forming a first dielectric layer and a second dielectric layer in the groove; removing the first dielectric layer with a certain depth in the partial area at the top of the groove; removing the second dielectric layer in the groove to form a second groove structure; forming gate oxide in the second groove to enable the bottom oxide layer of the side wall of the groove to be composed of the first medium layer and the gate oxide, wherein the thickness of the bottom oxide layer is thicker, and a seamless filling conductive material is formed; selectively removing the conductive material at the top of the groove to separate the conductive material for a certain distance, and forming a third groove and a fourth groove in the groove; and filling a third dielectric layer in the third groove and the fourth groove, so that the risks of short circuit and electric leakage between the shielding conductor and the grid conductor are reduced, and the capacitance parameter between GS is optimized, thereby improving the yield of the power semiconductor device and reducing the reliability risk.

Description

Process-optimized power semiconductor device and method for producing the same
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a power semiconductor device with optimized process and a manufacturing method thereof.
Background
Power semiconductor devices, also known as power electronic devices, include power diodes, thyristors, VDMOS (vertical double-diffused metal oxide semiconductor) field effect transistors, LDMOS (lateral-diffused metal oxide semiconductor) field effect transistors, IGBTs (insulated gate bipolar transistors), and the like. The VDMOS field effect transistor includes a source region and a drain region formed on opposite surfaces of a semiconductor substrate, and in a high-frequency operation of the power semiconductor device, a current flows mainly along a longitudinal direction of the semiconductor substrate in an on state, and lower conduction loss and switching loss are important indexes for evaluating the device performance.
On the basis of the VDMOS field effect transistor, a trench type MOS field effect transistor has been further developed, in which a gate conductor is formed in a trench, and a gate dielectric is formed on a trench sidewall to separate the gate conductor and a semiconductor layer to form a channel in the semiconductor layer in a direction along the trench sidewall. The Trench (Trench) process changes the channel from horizontal to vertical, eliminates the response of parasitic JFET resistance of a planar structure, and greatly reduces the size of a cell. On the basis, the cell density is increased, the total width of a channel in a chip in unit area is improved, the channel width-length ratio of a device on a unit silicon chip is increased, so that the current is increased, the on-resistance is reduced, and related parameters are optimized, and the goal that a smaller-sized die has higher power and higher performance is realized. Meanwhile, the shielding conductor extends to the lower part of the grid conductor, the insulating layer and the semiconductor layer are separated from each other and are connected with the source electrode together and are grounded together, so that a charge balance effect is introduced, a Reduced Surface Field (RESURF) effect is achieved in the vertical direction of the power semiconductor device, the withstand voltage is improved through the thicker shielding dielectric layer and the deeper groove depth, and meanwhile, the on-resistance Rdson is further Reduced, so that the conduction loss is Reduced.
A schematic diagram of a prior art power semiconductor device is shown in fig. 1. By way of example, the power semiconductor device is a trench-gate MOSFET power semiconductor device.
As shown in fig. 4, the trench-gate MOSFET power semiconductor device includes a plurality of trenches 11 in an epitaxial layer 10b on a semiconductor substrate 10 a. A first dielectric layer 12 formed in the trench, a first conductive material 13, and a gate oxide 14, a conductive material 15 formed on top of the trench 11. P-type doping 16 and N-type doping 17 are formed on the epitaxy and a third dielectric layer 18, contact holes and a metal layer 21 are formed on the epitaxy and the top of the trench, finally forming metal electrodes 22, 23, 24.
Fig. 5 is a partially enlarged schematic view of the power semiconductor device shown in fig. 4.
FIG. 5 is an enlarged view of the area 30 in FIG. 4, in which the oxide layer between the first conductive material 13 and the conductive material 15 is 14b, and the thickness d2 ≧ the thickness d1 of the trench sidewall gate oxide 14. Where the conductive material 15 is elevated above the epitaxial surface, the metal electrode 24 is connected to the conductive material 15 by a via hole having a bottom located a distance d3 from the oxide layer 14b on top of the first conductive material. If d3 is smaller, the risk of GS leakage and even GS short circuit is likely to occur. Meanwhile, in the split-gate power semiconductor device, the gate-source capacitance Cgs is influenced by the thickness of an oxide layer among polycrystals, the thicker the oxide layer is, the smaller the capacitance Cgs is, and the faster the switching speed of the device is, so that how to increase the thickness of the oxide layer 14b to the maximum extent, and optimizing the parameter performance of the device is the content of research of the personnel in the industry.
In a split gate type power semiconductor device with a withstand voltage of over 100V, the depth of a trench is usually over 5um, the thickness of a shield gate is usually over 5000A, and the width of the trench is required to be narrower in order to pursue a smaller chip area, so that the vertical width ratio of the trench is large, the filling process of a conductive material is complicated, and voids and gaps are easy to occur. As shown in fig. 2, the first poly 13 is likely to form voids 13a and gaps 13b during the filling process, thereby risking leakage of GS and even short-circuiting GS due to poor filling of the first conductive material. How to optimize the filling process and technique is the content of research by those in the industry.
Meanwhile, in the prior art, the first conductive material and the conductive material are formed by deposition processes at least twice, the process is complex, the cost is high,
the method is used for optimizing the defect-free filling process and technology of the conductive material under the condition of a large longitudinal-to-width ratio, reducing the manufacturing cost, increasing the thickness of an oxide layer between two layers of polycrystals, enabling the capacitance Cgs to be smaller and the switching speed of a device to be faster, improving the metal electrode wiring mode of the conductive material at lower cost and avoiding GS abnormity caused by the metal wiring mode between GS. The thickness of an oxide layer formed at the bottom of the side wall of the groove is further improved, the voltage resistance between GS is optimized, the risk of leakage short circuit and even gate oxide breakdown between GS is reduced, and the method is the content of research of personnel in the industry.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a manufacturing method of a power semiconductor device with an optimized process, and aims to solve the technical problem of how to optimize a product structure so as to reduce the risks of short circuit and electric leakage between a shielding conductor and a grid conductor and optimize capacitance parameters between GS (gate-to-gate) so as to improve the yield of the power semiconductor device and reduce the reliability risk.
In order to solve the technical problems, the technical scheme provided by the invention is as follows: the manufacturing method of the power semiconductor device with the optimized process comprises the following steps:
s1: taking a semiconductor substrate with a specific doping type as a raw material, forming an epitaxial layer on the substrate, and forming a groove with a certain width and depth on the epitaxial layer;
s2: sequentially arranging a first dielectric layer and a second dielectric layer on the surface of the epitaxial layer and in the groove;
s3: removing the surface of the epitaxial layer and the second dielectric layer at the top of the groove by adopting a chemical mechanical planarization method;
s4: removing the first dielectric layer on the surface of the epitaxial layer and the top of the groove by wet etching or dry etching to form a first groove structure;
s5: removing the second dielectric layer in the groove by wet etching or dry etching to form a second groove structure;
s6: performing gate oxide oxidation on the side wall of the second groove close to the epitaxial layer by adopting a thermal oxidation process to form a conductive material in the second groove;
s7: selectively removing the conductive material in the groove, and separating the conductive material for a certain distance to form a third groove and a fourth groove;
s8: filling a third dielectric layer in the third groove and the fourth groove by adopting a thermal oxidation or Chemical Vapor Deposition (CVD) method;
s9: selecting a proper dopant, forming different types of doped regions by adopting a method of multiple times of ion implantation, and then carrying out thermal annealing to activate impurities to form in-vivo doped regions of the device, required PN junctions and other device structures;
s10: forming a fourth dielectric layer on the surface of the epitaxial layer and the top of the trench by adopting a Chemical Vapor Deposition (CVD) method, selectively forming a contact hole by adopting photoetching and etching processes, and injecting the contact hole;
s11: filling the contact holes by adopting MOCVD, PVD and other metal materials or combination of multiple materials in the electrodes Ti, TiN, W, AL, ALSI, ALCU, ALSICU and the like, and then forming the metal electrodes by adopting photoetching and etching processes.
Further, in step S1, the semiconductor substrate is made of group III-V semiconductors GaAs, InP, GaN, SiC, and group IV semiconductors Si, Ge, the semiconductor substrate is a single crystal silicon substrate doped N-type, the epitaxial layer is a single crystal silicon epitaxial doped N-type, and the trench has a depth to width ratio less than 10 a.
Further, in step S2, a thermal oxidation or a chemical vapor deposition CVD method is used to form the first dielectric layer, where the thermal oxidation includes a hydrothermal oxidation HTO or a selective reaction oxidation SRO, the chemical vapor deposition CVD method includes a low pressure chemical vapor deposition LPCVD method or a sub-atmospheric pressure chemical vapor deposition SACVD method, the second dielectric layer is composed of one or more of silicon nitride, silicon oxynitride, poly-crystal, amorphous, and the thickness of the second dielectric layer is greater than or equal to 10A.
Further, in step S4, when a wet etching is adopted, the first dielectric layer on the top of the trench may form an arc structure near the epitaxial sidewall according to the characteristics of the wet etching.
Further, in step S5, wet or dry etching is performed to remove all the second dielectric layers in the trench, the shape of the first dielectric layer formed in step S4 is retained, a second groove structure with an exposed epitaxial surface and exposed arc-shaped sidewalls at the top of the trench is formed, and after the second groove is formed, the aspect ratio of the region to be filled with the subsequent poly is smaller than the aspect ratio of the trench.
Further, in step S6, the thickness of the gate oxide is 50 to 2000 a, an arc-shaped structure may appear near the epitaxial sidewall of the second groove, so that the thickness at the bottom of the sidewall of the trench is consistent with the thickness of other regions, the conductive material is composed of in-situ doped polycrystalline silicon, the deposition temperature is 500 to 800 ℃, the square resistance is 3 to 20 Ω, the thickness is 1000 to 20000 a, and the conductive material fills a seamless gap in the trench.
Further, in step S7, the third groove corresponds to the shielding poly region of the split-gate power device, the conductive material in the middle of the trench needs to be retained and the conductive material on both sides needs to be removed, the region where the conductive material is removed subsequently needs to be filled with a dielectric layer, the fourth groove corresponds to the cell region structure, the conductive material on both sides of the top of the trench is retained as the gate of the split-gate power device by a selective etching method, and the conductive material in the middle region of the trench is removed from top to bottom to separate the conductive material into two segments of shielding poly and gate poly.
Further, in step S8, the thermal oxidation includes hydrothermal oxidation HTO or selective reactive oxidation SRO, and the chemical vapor deposition CVD includes low pressure chemical vapor deposition LPCVD or sub-atmospheric pressure chemical vapor deposition SACVD.
Further, in step S10, one or more combinations of dielectric layers such as NSG, BPSG, PSG, SiN, SiON, etc. are formed by CVD including LPCVD or SACVD.
The power semiconductor device with optimized process comprises a semiconductor substrate, wherein an epitaxial layer is arranged on the semiconductor substrate, a groove is formed in the epitaxial layer, a first dielectric layer is arranged in the groove, a conductive material is arranged in the first dielectric layer, a gate oxide layer wraps the outside of part of the conductive material, a fourth dielectric layer is arranged at the top of the gate oxide layer, a first conductive window, a second conductive window and a third conductive window are separately arranged at the upper part of the fourth dielectric layer, the bottom end of the first conductive window is connected with the conductive material, an upper source region and a lower source region are arranged between part of the grooves, the bottom end of the second conductive window penetrates through the upper source region and extends into the lower source region, the bottom end of the third conductive window extends into two sides of the conductive material, namely the first, and a first metal electrode, a second metal electrode and a third metal electrode are respectively arranged in the second conductive window and the third conductive window.
The beneficial effect that this technical scheme brought is: the optimized power semiconductor device is designed, seamless filling of the shielding conductor and the grid conductor is realized, the process realization difficulty is reduced, the voltage resistance between GS is optimized, and the risks of electric leakage, short circuit and even grid oxide breakdown between GS are reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart of a process optimized power semiconductor device fabrication method of the present invention;
FIG. 2 is a schematic diagram of a portion of a power semiconductor device optimized by the process of the present invention;
FIG. 3 is a schematic structural diagram of a main part of a power semiconductor device optimized by the process of the present invention;
FIG. 4 is a schematic diagram of a prior art power semiconductor device;
FIG. 5 is a schematic view of a portion of the enlarged structure of FIG. 1;
in the figure: 101-a semiconductor substrate, 102-an epitaxial layer, 110-a trench, 120-a first dielectric layer, 150-a conductive material, 140-a gate oxide layer, 180-a fourth dielectric layer, 201-a first conductive window, 202-a second conductive window, 203-a third conductive window, 170-an upper source region, 160-a lower source region, 211-a first metal electrode, 212-a second metal electrode, 213-a third metal electrode. Detailed description of the preferred embodimentsthe following description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, is intended to illustrate and explain the present invention and not to limit the same. As shown in fig. 1, the method for manufacturing the power semiconductor device with the optimized process comprises the following steps:
s1: taking a semiconductor substrate with a specific doping type as a raw material, forming an epitaxial layer on the substrate, and forming a groove with a certain width and depth on the epitaxial layer;
s2: sequentially arranging a first dielectric layer and a second dielectric layer on the surface of the epitaxial layer and in the groove;
s3: removing the surface of the epitaxial layer and the second dielectric layer at the top of the groove by adopting a chemical mechanical planarization method;
s4: removing the first dielectric layer on the surface of the epitaxial layer and the top of the groove by wet etching or dry etching to form a first groove structure;
s5: removing the second dielectric layer in the groove by wet etching or dry etching to form a second groove structure;
s6: performing gate oxide oxidation on the side wall of the second groove close to the epitaxial layer by adopting a thermal oxidation process to form a conductive material in the second groove;
s7: selectively removing the conductive material in the groove, and separating the conductive material for a certain distance to form a third groove and a fourth groove;
s8: filling a third dielectric layer in the third groove and the fourth groove by adopting a thermal oxidation or Chemical Vapor Deposition (CVD) method;
s9: selecting a proper dopant, forming different types of doped regions by adopting a method of multiple times of ion implantation, and then carrying out thermal annealing to activate impurities to form in-vivo doped regions of the device, required PN junctions and other device structures;
s10: forming a fourth dielectric layer on the surface of the epitaxial layer and the top of the trench by adopting a Chemical Vapor Deposition (CVD) method, selectively forming a contact hole by adopting photoetching and etching processes, and injecting the contact hole;
s11: filling the contact holes by adopting MOCVD, PVD and other metal materials or combination of multiple materials in the electrodes Ti, TiN, W, AL, ALSI, ALCU, ALSICU and the like, and then forming the metal electrodes by adopting photoetching and etching processes.
Therefore, the optimized power semiconductor device is designed, seamless filling of the shielding conductor and the grid conductor is realized, the process realization difficulty is reduced, the voltage resistance between GS is optimized, and the risks of electric leakage, short circuit and even grid oxide breakdown between GS are reduced.
On the whole, the groove filling process and the groove filling technology are optimized, the risk that cavities and gaps appear in polycrystalline filling under the condition that the longitudinal width ratio of the groove is large is reduced, the risks of short circuit and electric leakage between the shielding conductor and the grid conductor are reduced, the capacitance parameters between GS are optimized, the yield of power semiconductor devices is improved, and the reliability risk is reduced.
In this embodiment, in step S1, the semiconductor substrate is made of group III-V semiconductors GaAs, InP, GaN, SiC, and group IV semiconductors Si, Ge, the semiconductor substrate is an N-doped single crystal silicon substrate, the epitaxial layer is an N-doped single crystal silicon epitaxy, the ratio of the depth to the width of the trench is less than 10a, the depths of the trenches are different for trench-gate power semiconductor devices of different withstand voltage levels, and generally, for a split-gate power semiconductor device, the deeper the depth of the trench is, the higher the withstand voltage level of the device is, the range is 1-15 μm, and the width of the trench generally decreases as the chip size decreases. When the vertical-to-width ratio of the groove is larger than 10, a problem such as a gap or a void is likely to occur.
In this embodiment, in step S2, a first dielectric layer is formed by thermal oxidation or chemical vapor deposition CVD, the thermal oxidation includes hydrothermal oxidation HTO or selective reactive oxidation SRO, the chemical vapor deposition CVD includes compressive chemical vapor deposition LPCVD or sub-atmospheric pressure chemical vapor deposition SACVD, the second dielectric layer is composed of one or more of silicon nitride, silicon oxynitride, poly, and amorphous, and a thickness of the second dielectric layer is greater than or equal to 10a, so that the first dielectric layer serves as an isolation layer between a shielding conductor and a semiconductor substrate in a power semiconductor device, and for trench gate power semiconductor devices with different withstand voltage levels, a thickness of the isolation layer is adjusted along with withstand voltage, a depth of a trench, an epitaxial concentration, and the like, and generally, a higher degree of the withstand voltage is, and the isolation layer is thicker. The second dielectric layer can be filled in the groove, can also generate holes and gaps, and can only cover the inner wall of the groove and the surface of the first dielectric layer.
In this embodiment, in step S4, when the wet process is adopted, according to the characteristics of the wet etching, an arc structure is formed on the first dielectric layer at the top of the trench near the side of the epitaxial sidewall, and the arc structure can optimize the topography at the bottom of the trench sidewall and improve the thickness of the gate oxide in the subsequent oxidation process, thereby improving parameters such as GS withstand voltage and leakage, and reducing the reliability risk.
In this embodiment, in step S5, wet or dry etching is used to remove all the second dielectric layers in the trench, the shape of the first dielectric layer strange in star in S4 is retained, and a second groove structure with an exposed epitaxial surface and exposed arc-shaped sidewalls at the top of the trench is formed.
In this embodiment, in step S6, the thickness of the gate oxide is 5010 to 2000 a, an arc-shaped structure may appear near the epitaxial sidewall of the second groove, so that the thickness of the bottom of the trench wall is consistent with the thickness of other regions, the conductive material is composed of in-situ doped polycrystalline silicon, the deposition temperature is 500 to 800 ℃, the square resistance is 3 to 20 Ω, the thickness is 1000 a to 20000 a, and the conductive material fills a gap in the trench, otherwise parameter problems such as electrical leakage may occur, which affects reliability.
In this embodiment, in step S7, the third groove corresponds to the shielding poly region of the split-gate power device, the conductive material in the middle of the trench needs to be retained and the conductive materials on both sides need to be removed, the region where the conductive material is removed subsequently needs to be filled with a dielectric layer, the first groove corresponds to the cell region structure, the conductive materials on both sides of the top of the trench are retained as the gate of the split-gate power device by a selective etching method, and the conductive material in the middle region of the trench is removed from top to bottom to separate the conductive material into the shielding poly and the gate poly, so as to improve the parameters of GS withstand voltage, leakage current, and the like, and reduce.
In this embodiment, in step S8, the thermal oxidation includes hydrothermal oxidation HTO or selective reactive oxidation SRO, and the chemical vapor deposition CVD includes low pressure chemical vapor deposition LPCVD or sub-atmospheric pressure chemical vapor deposition SACVD, where the third dielectric layer and the first dielectric layer are made of the same material.
In this embodiment, in step S10, a combination of multiple dielectric layers such as NSG, NPSG, PSG, SiN, SiON, etc. is formed by CVD including LPCVD or SACVD, which is a sub-atmospheric pressure CVD method, for isolating the device structure within the epitaxy from the subsequent metal layer.
Further, selectively forming a contact hole refers to selectively forming a conductive window penetrating through the dielectric layer, the gate oxide layer and a part of the epitaxial surface by adopting photoetching and etching processes, wherein the contact window can be divided into a dielectric layer part and an epitaxial layer part, and the silicon etching depth of the epitaxial layer is 1000A to 5000A, so that the on-resistance can be reduced, and the EAS capability can be enhanced. In order to reduce the contact resistance, it is usually necessary to perform contact hole implantation and perform RTA, furnace annealing, and other processes after the contact hole.
As shown in fig. 2 and 3, the power semiconductor device with optimized process includes a semiconductor substrate 101, an epitaxial layer 102 is disposed on the semiconductor substrate 101, a trench 110 is disposed in the epitaxial layer 102, a first dielectric layer 120 is disposed in the trench 110, a conductive material 150 is disposed in the first dielectric layer 120, a gate oxide layer 140 is wrapped outside a portion of the conductive material 150, a fourth dielectric layer 180 is disposed on the top of the gate oxide layer 140, a first conductive window 201, a second conductive window 202 and a third conductive window 203 are separately disposed on the upper portion of the fourth dielectric layer 180, the bottom end of the first conductive window 201 is connected to the conductive material 150, an upper source region 170 and a lower source region 160 are disposed between portions of the trench 110, the bottom end of the second conductive window 202 penetrates through the upper source region 170 and extends into the lower source region 160, the bottom end of the third conductive window 203 extends into two sides of the conductive material 150, and first metal electrodes 211, second metal electrodes 211, third metal electrodes 211, and third metal electrodes are disposed in the first conductive window 201, A second metal electrode 212 and a third metal electrode 213.
Therefore, the optimized power semiconductor device is designed, seamless filling of the shielding conductor and the grid conductor is realized, the process realization difficulty is reduced, the voltage resistance between GS is optimized, and the risks of electric leakage, short circuit and even grid oxide breakdown between GS are reduced.
However, the present invention is not limited thereto, but may be applied to any type of trench type power semiconductor device. The power semiconductor device includes but is not limited to SGT device, IGBT device, TVS device, CMOS device, Bicmos device, MEMS device, schottky device, memory and other semiconductor devices.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. The manufacturing approach of the power semiconductor device of the optimized technology, characterized by that: the method comprises the following steps:
s1: taking a semiconductor substrate with a specific doping type as a raw material, forming an epitaxial layer on the substrate, and forming a groove with a certain width and depth on the epitaxial layer;
s2: sequentially arranging a first dielectric layer and a second dielectric layer on the surface of the epitaxial layer and in the groove;
s3: removing the surface of the epitaxial layer and the second dielectric layer at the top of the groove by adopting a chemical mechanical planarization method;
s4: removing the first dielectric layer on the surface of the epitaxial layer and the top of the groove by wet etching or dry etching to form a first groove structure;
s5: removing the second dielectric layer in the groove by wet etching or dry etching to form a second groove structure;
s6: performing gate oxide oxidation on the side wall of the second groove close to the epitaxial layer by adopting a thermal oxidation process to form a conductive material in the second groove;
s7: selectively removing the conductive material in the groove, and separating the conductive material for a certain distance to form a third groove and a fourth groove;
s8: filling a third dielectric layer in the third groove and the fourth groove by adopting a thermal oxidation or Chemical Vapor Deposition (CVD) method;
s9: selecting a proper dopant, forming different types of doped regions by adopting a method of multiple times of ion implantation, and then carrying out thermal annealing to activate impurities to form in-vivo doped regions of the device, required PN junctions and other device structures;
s10: forming a fourth dielectric layer on the surface of the epitaxial layer and the top of the trench by adopting a Chemical Vapor Deposition (CVD) method, selectively forming a contact hole by adopting photoetching and etching processes, and injecting the contact hole;
s11: filling the contact holes by adopting MOCVD, PVD and other metal materials or combination of multiple materials in the electrodes Ti, TiN, W, AL, ALSI, ALCU, ALSICU and the like, and then forming the metal electrodes by adopting photoetching and etching processes.
2. The method of manufacturing a process optimized power semiconductor device according to claim 1, characterized in that: in step S1, the semiconductor substrate is made of group III-V semiconductors GaAs, InP, GaN, SiC, and group IV semiconductors Si, Ge, the semiconductor substrate is a single crystal silicon substrate doped N-type, the epitaxial layer is a single crystal silicon epitaxial doped N-type, and the trench has a depth to width ratio less than 10 a.
3. The method of manufacturing a process optimized power semiconductor device according to claim 1, characterized in that: in step S2, a thermal oxidation or chemical vapor deposition CVD is used to form the first dielectric layer, where the thermal oxidation includes hydrothermal oxidation HTO or selective reactive oxidation SRO, the chemical vapor deposition CVD includes low pressure chemical vapor deposition LPCVD or sub-atmospheric pressure chemical vapor deposition SACVD, the second dielectric layer is composed of one or more of silicon nitride, silicon oxynitride, polycrystal, and amorphous, and the thickness of the second dielectric layer is greater than or equal to 10A.
4. The method of manufacturing a process optimized power semiconductor device according to claim 1, characterized in that: in step S4, when the wet etching is adopted, the first dielectric layer on the top of the trench is formed into an arc structure near the epitaxial sidewall according to the characteristics of the wet etching.
5. The method of manufacturing a process optimized power semiconductor device according to claim 1, characterized in that: in step S5, wet or dry etching is performed to remove all the second dielectric layers in the trench, the morphology of the first dielectric layer formed in step S4 is preserved, a second trench structure with an exposed epitaxial surface and exposed arc-shaped sidewalls at the top of the trench is formed, and after the second trench is formed, the aspect ratio of the region of the subsequent poly to be filled is smaller than the aspect ratio of the trench.
6. The method of manufacturing a process optimized power semiconductor device according to claim 1, characterized in that: in step S6, the thickness of gate oxide is 50A-2000A, an arc-shaped structure appears on the second groove close to the epitaxial sidewall, so that the thickness of the bottom of the trench sidewall is consistent with the thickness of other regions, the conductive material is composed of in-situ doped polycrystalline silicon, the deposition temperature is 500 ℃ to 800 ℃, the square resistance is 3-20 Ω, the thickness is 1000A-20000A, and the conductive material is filled with a seamless gap in the trench.
7. The method of manufacturing a process optimized power semiconductor device according to claim 1, characterized in that: in step S7, the third groove corresponds to the shielding poly region of the split-gate power device, the conductive material in the middle of the trench needs to be retained and the conductive materials on both sides need to be removed, the region where the conductive material is removed subsequently needs to be filled with a dielectric layer, the fourth groove corresponds to the cell region structure, the conductive materials on both sides of the top of the trench are retained as the gate of the split-gate power device by a selective etching means, and the conductive material in the middle region of the trench is removed from top to bottom to separate the conductive material into two segments of shielding poly and gate poly.
8. The method of manufacturing a process optimized power semiconductor device according to claim 1, characterized in that: in step S8, the thermal oxidation includes hydrothermal oxidation HTO or selective reactive oxidation SRO, and the chemical vapor deposition CVD includes low pressure chemical vapor deposition LPCVD or sub-atmospheric pressure chemical vapor deposition SACVD.
9. The method of manufacturing a process optimized power semiconductor device according to claim 1, characterized in that: in step S10, one or more combinations of dielectric layers such as NSG, BPSG, PSG, SiN, SiON, etc. are formed by CVD including LPCVD or SACVD.
10. The power semiconductor device with optimized process is characterized in that: the semiconductor device comprises a semiconductor substrate (101), an epitaxial layer (102) is arranged on the semiconductor substrate (101), a groove (110) is formed in the epitaxial layer (102), a first dielectric layer (120) is arranged in the groove (110), a conductive material (150) is arranged in the first dielectric layer (120), a gate oxide layer (140) wraps part of the conductive material (150), a fourth dielectric layer (180) is arranged at the top of the gate oxide layer (140), a first conductive window (201), a second conductive window (202) and a third conductive window (203) are separately arranged at the upper part of the fourth dielectric layer (180), the bottom end of the first conductive window (201) is connected with the conductive material (150), an upper source region (170) and a lower source region (160) are arranged between part of the groove (110), and the bottom end of the second conductive window (202) penetrates through the upper source region (170) and extends into the lower source region (160), the bottom end of the third conductive window (203) extends into two sides of the conductive material (150), and a first metal electrode (211), a second metal electrode (212) and a third metal electrode (213) are respectively arranged in the first conductive window (201), the second conductive window (202) and the third conductive window (203).
CN202110363338.3A 2021-04-02 2021-04-02 Process-optimized power semiconductor device and method for producing the same Pending CN112928167A (en)

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