CN117497586A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN117497586A
CN117497586A CN202210879733.1A CN202210879733A CN117497586A CN 117497586 A CN117497586 A CN 117497586A CN 202210879733 A CN202210879733 A CN 202210879733A CN 117497586 A CN117497586 A CN 117497586A
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China
Prior art keywords
doped region
conductive portion
epitaxial layer
trench
region
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CN202210879733.1A
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Chinese (zh)
Inventor
邹振东
廖志成
李家豪
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Vanguard International Semiconductor Corp
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Vanguard International Semiconductor Corp
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Priority to CN202210879733.1A priority Critical patent/CN117497586A/en
Publication of CN117497586A publication Critical patent/CN117497586A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A semiconductor device includes an epitaxial layer of a first conductivity type disposed on a surface of a substrate, a trench disposed in the epitaxial layer, a gate structure disposed in the trench and including an upper conductive portion and a lower conductive portion, a dielectric spacer disposed between the upper conductive portion and the lower conductive portion, a dielectric liner disposed in the trench and surrounding the gate structure, the dielectric liner having an opening at a bottom surface of the trench, a portion of the lower conductive portion filled in the opening, and a portion of the lower conductive portion and the epitaxial layer constituting a Schottky barrier diode, a doped region of a second conductivity type disposed in the epitaxial layer and located below the bottom surface of the trench and on one side of the lower conductive portion, wherein the portion of the epitaxial layer and a portion of the doped region are both in contact with the lower conductive portion.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates to semiconductor technology, and more particularly, to a semiconductor device including a vertically buried schottky barrier diode and a method of manufacturing the same.
Background
Metal-oxide-semiconductor field effect transistors (MOSFETs) are the most commonly used power transistors in integrated circuits and are typically operated under high voltage, high current conditions. The MOSFET may include horizontal structures, such as laterally diffused metal-oxide semiconductor (LDMOS) Field Effect Transistors (FETs), and vertical structures, such as trench gate metal-oxide semiconductor field effect transistors (trench gate MOSFET). For a trench-type gate MOSFET, the gate is disposed in the trench, which has the advantages of reducing the cell size and parasitic capacitance, however, the conventional trench-type gate MOSFET still cannot fully meet various requirements in power electronics applications in terms of on-state resistance (Ron), breakdown voltage (breakdown voltage), switching loss (switching loss), and the like.
Disclosure of Invention
In view of this, the present invention proposes a semiconductor device and a method for fabricating the same, which includes a schottky barrier diode (Schottkybarrier diode, SBD) embedded vertically (vertically embedded) integrated in a split gate trench type vertical double diffused metal oxide semiconductor field effect transistor (split-gate trench vertical double diffused MOSFET (VD MOSFET)), which is advantageous for the application of the semiconductor device under the operating conditions of high voltage and high frequency electric signals, in addition to the non-increase of the cell size (cell pitch), the reduction of on-resistance (Ron), the reduction of gate-to-drain capacitance (gate-drain capacitance, cgd) and the increase of breakdown voltage (breakdown voltage, BV).
According to one embodiment of the present invention, a semiconductor device is provided that includes a substrate, an epitaxial layer, a trench, a gate structure, a dielectric spacer, a dielectric liner, and a first doped region. The epitaxial layer has a first conductivity type and is arranged on a first surface of the substrate, the trench is arranged in the epitaxial layer, the grid structure is arranged in the trench and comprises an upper conductive part and a lower conductive part, the dielectric separation part is arranged between the upper conductive part and the lower conductive part, the dielectric lining layer is arranged in the trench and surrounds the grid structure, the dielectric lining layer is provided with an opening which is positioned on the bottom surface of the trench, a part of the lower conductive part is filled in the opening, the lower conductive part and a part of the epitaxial layer form a Schottky barrier diode, the first doped region has a second conductivity type and is arranged in the epitaxial layer and is positioned on one side of the lower conductive part and the lower conductive part below the bottom surface of the trench, and the part of the epitaxial layer and the part of the first doped region are both in contact with the lower conductive part.
According to an embodiment of the present invention, there is provided a method of manufacturing a semiconductor device including the steps of: providing a substrate, and forming an epitaxial layer on a first surface of the substrate, wherein the epitaxial layer has a first conductivity type; forming a first doped region and a second doped region in the epitaxial layer, wherein the first doped region and the second doped region have a second conductivity type; forming a groove in the epitaxial layer, wherein the bottom surface of the groove exposes the first doping region and the second doping region; forming a first dielectric layer on the side wall and the bottom surface of the groove in a forward direction; forming a first spacer and a second spacer on the first dielectric layer and located on two opposite sidewalls of the trench; etching the first dielectric layer to form an opening by using the first spacer and the second spacer as shields, wherein the opening exposes a portion of the epitaxial layer and a portion of each of the first doped region and the second doped region; forming a lower conductive part in the trench and filling the opening, wherein the lower conductive part is in contact with the portion of the epitaxial layer; and forming a dielectric spacer and an upper conductive portion in the trench, the upper conductive portion and the lower conductive portion being separated from each other by the dielectric spacer.
In order to make the features of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
For easier understanding, reference is made to the drawings and their detailed description when reading the present invention. Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the various features of the invention. Moreover, for the sake of clarity, various features in the drawings may not be drawn to actual scale, and thus the dimensions of some features in some of the drawings may be exaggerated or reduced on purpose.
Fig. 1 is a schematic cross-sectional view and an equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention.
Fig. 2 is a schematic top view of some components of a semiconductor device according to an embodiment of the present invention.
Fig. 3 is a schematic top view of some components of a semiconductor device according to another embodiment of the present invention.
Fig. 4 is a schematic top view of some components of a semiconductor device according to yet another embodiment of the present invention.
Fig. 5 is a schematic top view of other components of a semiconductor device according to some embodiments of the present invention.
Fig. 6, 7, 8, 9 and 10 are schematic cross-sectional views illustrating some stages of a method of fabricating a semiconductor device according to an embodiment of the invention.
10 … body diode
100 … semiconductor device
100C … equivalent circuit
101 … substrate
103 … epitaxial layer
103-1 … first epitaxial layer
103-2 … second epitaxial layer
104 … part of the epitaxial layer
105-1 … first doped region
105-2 … second doped region
105-3, 105-4, 105-5, 105-6, … doped regions
106 … groove
107 … lower conductive part
109 … upper conductive portion
110 … gate structure
111 … first dielectric layer
111-1, 111-2, … part of the first dielectric layer
111-3, 111-4, … remaining portions of the first dielectric layer
112 … dielectric separator
114 … dielectric liner
115 … opening
116 … well region
116-1 … first well region
116-2 … second well region
118 … source region
118-1 … first source region
118-2 … second source region
120-1 … first heavily doped region
120-2 … second heavily doped region
122 … second dielectric layer
122-1 … first spacer
122-2 … second spacer
124 … first conductive material layer
126 … third dielectric layer
127 … fourth dielectric layer
128 … second conductive material layer
130 … interlayer dielectric
131. 133 … contact opening
132 … gate contact
134 … source contact
136 … drain electrode
S … source electrode
D … drain electrode
G … grid electrode
SBD … Schottky barrier diode
200A, 200B … top-down layout
Steps S101, S103, S105, S107, S109, S111, S113, S115, S117, S119, S121, S123, S125, S127, S129, S131, S133 …
Detailed Description
The invention provides several different embodiments that can be used to implement different features of the invention. For simplicity of explanation, the invention also describes examples of specific components and arrangements. These examples are provided for the purpose of illustration only and are not intended to be limiting in any way. For example, the following description of a first feature being formed on or over a second feature may refer to the first feature being in direct contact with the second feature, or may refer to other features being present between the first and second features, such that the first and second features are not in direct contact. Furthermore, various embodiments of the present invention may use repeated reference characters and/or textual notations. These repeated reference characters and notations are used to make the description more concise and clear, rather than to indicate a relationship between different embodiments and/or configurations.
In addition, for the spatially related narrative terms mentioned in the present invention, for example: when "under", "low", "lower", "upper", "top", "bottom" and the like, for ease of description, the description is used to describe one element or feature's relative relationship to another element(s) or feature(s) in the figures. In addition to the orientation shown in the drawings, these spatially dependent terms are also used to describe possible orientations of the semiconductor device in use and operation. With the semiconductor device oriented differently (rotated 90 degrees or other orientations), the spatially relative descriptors describing its orientation should be interpreted in a similar manner.
Although the invention has been described in the language of first, second, third, etc., to describe various elements, components, regions, layers and/or sections, it should be understood that these elements, components, regions, layers and/or sections should not be limited by these terms. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a specific embodiment, such that the term "comprises," "comprising," or variations thereof, is used to distinguish one element, component, region, layer, and/or section from another element, component, region, layer, and/or section, that does not necessarily include or imply any prior order, nor order from the one element to another or method of manufacture. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of the embodiments of the present invention.
The terms "about" or "substantially" as referred to herein generally mean within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the amounts provided in the specification are about amounts, i.e., without a specific recitation of "about" or "substantially," the meaning of "about" or "substantially" may still be implied.
The terms "coupled," "coupled," and "electrically connected" as used herein include any direct or indirect electrical connection. For example, if a first element is coupled to a second element, that connection may be directly to the second element or indirectly to the second element through other means of attachment or connection.
While the invention is described below with respect to specific embodiments, the inventive principles of this patent disclosure are applicable to other embodiments as well. Furthermore, specific details are omitted so as not to obscure the spirit of the present invention, and such omitted details are within the knowledge of one of ordinary skill in the art.
The invention relates to a semiconductor device including a vertically buried Schottky Barrier Diode (SBD) integrated in a split gate trench type vertical double diffused metal oxide semiconductor field effect transistor (split-gate trench VDMOSFET) and a method of manufacturing the same, wherein the gate structure of the semiconductor device includes an upper conductive portion and a lower conductive portion separated from each other and disposed in a trench, and the lower conductive portion and a portion of an epitaxial layer located directly below the lower conductive portion constitute the Schottky barrier diode. In addition, at least one or a plurality of doped regions separated from each other are located below the bottom surface of the trench in the epitaxial layer, the above portion of the epitaxial layer is located between the doped regions, and the conductivity type of the doped regions is opposite to that of the epitaxial layer, and the doped regions may be also referred to as shielding regions (shielding regions). The semiconductor device of the embodiment of the invention has the advantages of not increasing the element cell size (cell pitch), reducing the on-resistance (Ron), reducing the gate-drain capacitance (Cgd), increasing the Breakdown Voltage (BV), and the like, but also can reduce the reverse recovery charge (Qrr) and the switching power loss (Psw) through the vertically buried Schottky barrier diode, and the above-mentioned multiple doped regions (shielding regions) can reduce the electric field of the gate oxide layer, reduce the gate-drain coupling area (coupling area) and the gate-drain capacitance (Cgd), and protect the Schottky contact (Schottky contact), thereby being beneficial to the application of the semiconductor device under the operating conditions of high voltage and high frequency electric signals.
Fig. 1 is a schematic cross-sectional view and an equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention. In one embodiment, as shown in fig. 1, the semiconductor device 100 includes a substrate 101, and the substrate 101 is made of silicon, silicon carbide (SiC), aluminum nitride (AlN), gallium nitride (GaN), or other suitable semiconductor materials, wherein a 4H type single crystal silicon carbide (4H-SiC) substrate has advantages of high voltage resistance, heat resistance, reduced energy consumption, and the like, and is suitable for a power device. The epitaxial layer 103 is formed on a first surface (e.g., a top surface) of the substrate 101, and the epitaxial layer 103 has a first conductivity type, such as an N-type epitaxial layer, and the material of the epitaxial layer 103 is, for example, silicon carbide (SiC), monocrystalline silicon (monocrystalline silicon), or polycrystalline silicon (polysilicon), and the N-type dopant is, for example, nitrogen (N) or phosphorus (P). A trench 106 is formed in the epitaxial layer 103 extending from the top surface of the epitaxial layer 103 to a depth of the epitaxial layer 103, a gate structure 110 is disposed within the trench 106 and includes an upper conductive portion 109 and a lower conductive portion 107, and a dielectric spacer 112 is also disposed within the trench 106 and between the upper conductive portion 109 and the lower conductive portion 107 such that the upper conductive portion 109 and the lower conductive portion 107 are longitudinally separated from each other. In addition, a dielectric liner 114 is disposed in the trench 106 surrounding the gate structure 110, and the dielectric liner 114 has an opening 115 at the bottom of the trench 106, a portion of the lower conductive portion 107 is filled in the opening 115, and the portion of the lower conductive portion 107 is in contact with a portion 104 of the epitaxial layer 103.
In addition, at least one offset doped region, for example, including a first doped region 105-1 and a second doped region 105-2, is further disposed in the epitaxial layer 103 below the bottom surface of the trench 106, and a central axis of each offset doped region in the Z direction is offset from a central axis of the lower conductive portion 107 in the Z direction in a lateral direction (X direction). The first and second doped regions 105-1 and 105-2 have a second conductivity type opposite to the first conductivity type, such as a P-type doped region, and a P-type dopant such as boron (B) or aluminum (Al). The first doped region 105-1 and the second doped region 105-2 are laterally separated from each other and are located on opposite sides of the lower conductive portion 107 and are also located on opposite sides of the opening 115, and the portion 104 of the epitaxial layer 103 is located between the first doped region 105-1 and the second doped region 105-2. Further, a portion of the first doped region 105-1 and a portion of the second doped region 105-2 are each in contact with a portion of the underlying conductive portion 107.
In some embodiments, aboveThe material of the conductive portion 109 is polysilicon, the material of the lower conductive portion 107 is schottky metal or doped polysilicon (e.g., P-type polysilicon), and the material of the epitaxial layer 103 is silicon carbide. In other embodiments, the material of the lower conductive portion 107 is schottky metal, and the material of the epitaxial layer 103 is silicon carbide, monocrystalline silicon or polycrystalline silicon, wherein the schottky metal is tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), nickel (Ni), gold (Au), iridium (Ir), platinum (Pt), tungsten carbide (WC), nickel silicide (Ni 2 Si) or an alloy thereof, and the like. According to an embodiment of the present invention, the work function of the material of the lower conductive portion 107 is larger than the work function of the material of the epitaxial layer 103, such that a heterojunction is created between the lower conductive portion 107 and a portion 104 of the epitaxial layer 103, and the lower conductive portion 107 and the portion 104 of the epitaxial layer 103 constitute a schottky barrier diode (Schottkybarrier diode, SBD) which is vertically buried in the semiconductor device 100.
With continued reference to FIG. 1, the semiconductor device 100 further includes a first well 116-1 and a second well 116-2 disposed in the epitaxial layer 103 and respectively located on opposite sides of the trench 106, wherein the first well 116-1 and the second well 116-2 have a second conductivity type, such as a P-well (P-well). The first well region 116-1 and the second well region 116-2 may extend from the top surface of the epitaxial layer 103 to slightly above the bottom surface of the upper conductive portion 109, or may be slightly below or flush with the bottom surface of the upper conductive portion 109, with the first well region 116-1 and the second well region 116-2 serving as body regions (body regions) of the semiconductor device 100. In addition, the semiconductor device 100 further includes a first source region 118-1 and a second source region 118-2 disposed in the first well region 116-1 and the second well region 116-2, respectively, wherein the first source region 118-1 and the second source region 118-2 have a first conductivity type, such as an N-type heavily doped region (N + A dopped region). The semiconductor device 100 further includes a first heavily doped region 120-1 and a second heavily doped region 120-2 disposed in the first well region 116-1 and the second well region 116-2, respectively, and adjacent to the first source region 118-1 and the second source region 118-2, respectively, the first heavily doped region 120-1 and the second heavily doped region 120-2 having a second conductivity type, such as a P-type heavily doped region (P) + A dopped region). First source region 118-1, second source region 118-2, first heavily doped region 120-1, and second heavily doped regionThe impurity regions 120-2 each extend from the top surface of the epitaxial layer 103 to a depth position, wherein the bottom surfaces of the first and second heavily doped regions 120-1 and 120-2 may be lower than the bottom surfaces of the first and second source regions 118-1 and 118-2.
Still referring to fig. 1, the semiconductor device 100 further includes an interlayer dielectric layer 130 covering the top surface of the epitaxial layer 103, and a gate contact 132 disposed in the interlayer dielectric layer 130 and electrically coupled to the upper conductive portion 109 of the gate structure 110, wherein the upper conductive portion 109 can be used as a control gate. A source contact 134 is disposed in the interlayer dielectric 130 and electrically coupled to the first source region 118-1 and the first heavily doped region 120-1, and another source contact 134 is electrically coupled to the second source region 118-2 and the second heavily doped region 120-2. In addition, the semiconductor device 100 further includes a drain electrode 136 disposed on a second surface (e.g., a bottom surface) of the substrate 101. Fig. 1 also shows an equivalent circuit 100C of the semiconductor device 100, the upper conductive portion 109 of the gate structure 110 is a gate G in the equivalent circuit 100C, the first source region 118-1 and the second source region 118-2 are a source S in the equivalent circuit 100C, the drain electrode 136 is a drain D in the equivalent circuit 100C, and the gate G, the source S and the drain D constitute a vertical double-diffused metal oxide semiconductor field effect transistor (VDMOSFET). In addition, the PN junctions formed by the first heavily doped region 120-1 and the first well region 116-1 and the epitaxial layer 103 constitute a body diode (body diode) 10 in the equivalent circuit 100C, and the PN junctions formed by the second heavily doped region 120-2 and the second well region 116-2 and the epitaxial layer 103 also constitute a body diode (body diode) 10 in the equivalent circuit 100C, and both ends of the body diode 10 are electrically connected to the source electrode S and the drain electrode D, respectively. In addition, the lower conductive portion 107 and the portion 104 of the epitaxial layer 103 form a schottky barrier diode SBD in the equivalent circuit 100C, two ends of the schottky barrier diode SBD are electrically connected to the source S and the drain D, respectively, wherein the lower conductive portion 107 is electrically coupled to the source contact 134, and the schottky barrier diode SBD and the body diode 10 in the equivalent circuit 100C are electrically connected in parallel to each other.
In the embodiment of the present invention, during the operation of the semiconductor device 100, when the semiconductor device 100 is forward biased (drain voltage Vd > source voltage Vs), the lower conductive portion 107 and a portion 104 of the epitaxial layer 103 are reverse biased. At this time, the first doped region 105-1 and the second doped region 105-2 are reverse biased with the portion 104 of the epitaxial layer 103, so that the depletion region between the first doped region 105-1 and the second doped region 105-2 and the portion 104 of the epitaxial layer 103 increases, and the leakage current flowing from the epitaxial layer 103 to the underlying conductive portion 107 can be avoided. In addition, to avoid current flowing from the epitaxial layer 103 to the lower conductive portion 107 when the semiconductor device 100 is forward biased (Vd > Vs), the gap between the first doped region 105-1 and the second doped region 105-2 may be adjusted according to practical requirements, such that the depletion region formed between the first doped region 105-1 and the second doped region 105-2 may occupy a portion or all of the portion 104 of the epitaxial layer 103.
According to the embodiment of the invention, since the schottky barrier diode SBD is a unipolar (unipole) device, the schottky barrier diode SBD is turned off (turn-off) faster than the body diode 10 of a bipolar (bipolarar) device, and the schottky barrier diode SBD connected in parallel with the body diode 10 helps to reduce the reverse recovery charge (Qrr) rapidly when the equivalent circuit of the semiconductor device is performing the switching operation, thereby reducing the switching power loss (switching power loss, psw), especially for high frequency electric signals (e.g. higher than 5.00e+04 hertz (Hz)), the semiconductor device 100 of the embodiment of the invention has better switching performance. Meanwhile, the vertical buried schottky barrier diode SBD according to the embodiment of the present invention is integrated in the semiconductor device 100, so that the size (cell pitch) of the element unit of the semiconductor device 100 is not increased, and the semiconductor device 100 according to the embodiment of the present invention may not need to additionally provide a Schottky Barrier Diode (SBD) chip in addition to a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) chip, that is, the embodiment of the present invention can integrate the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and the Schottky Barrier Diode (SBD) in a single chip structure, which is more space-saving than the conventional MOSFET and SBD dual chip structure.
According to the embodiment of the invention, the first doped region 105-1 and the second doped region 105-2 of the semiconductor device 100 have the function of a shielding region (shielding region), so that the electric field strength of a specific region (for example, the bottom surface of the trench 106) is reduced, and the gate-drain capacitance (Cgd) is reduced. As shown in fig. 1, the first doped region 105-1 and the second doped region 105-2 are each in contact with a dielectric liner 114 located at the bottom surface of the trench 106, and in some embodiments, the outer edges of the first doped region 105-1 and the second doped region 105-2 each extend beyond the edges of the trench 106 to reduce the electric field strength of the dielectric liner 114 (also referred to as a gate dielectric layer) located at the bottom surface of the trench 106, and to reduce the coupling area (coupling area) between the gate and the drain, thereby reducing the gate-drain capacitance value (Cgd), while also protecting the Schottky contact (Schottky contact) at the junction of the underlying conductive portion 107 and the portion 104 of the epitaxial layer 103. In addition, the lower conductive portion 107 and the upper conductive portion 109 of the semiconductor device 100 are separated from each other, and the lower conductive portion 107 is electrically coupled to the source contact 134, so that the gate-drain capacitance (Cgd) can be further reduced to reduce the switching loss (switching loss) of the semiconductor device 100.
Fig. 2 is a schematic top view of some components of a semiconductor device according to an embodiment of the present invention. As shown in fig. 2, in an embodiment, the first doped region 105-1 and the second doped region 105-2 of the semiconductor device 100 are each located at opposite sides of the lower conductive portion 107 in a top view, and the first doped region 105-1 and the second doped region 105-2 are each overlapped with a portion of the lower conductive portion 107 or further overlapped with the lower conductive portion 107 filled into the opening 115 of the dielectric liner 114, and a portion 104 of the epitaxial layer 103 is located between the first doped region 105-1 and the second doped region 105-2, and an outer edge of the first doped region 105-1 and an outer edge of the second doped region 105-1 each exceed an edge of the trench 106. In this embodiment, the extension directions (e.g., Y-axis directions) of the first doped region 105-1, the second doped region 105-2, and the lower conductive portion 107 are all parallel to each other in a plane direction (e.g., XY plane) parallel to the surface of the substrate 101. Furthermore, in some embodiments, the top-down shape of the opening 115 of the dielectric liner 114 may be rectangular, and the first and second doped regions 105-1, 105-2 may be located on opposite sides of the opening 115. In addition, the top-view shape of the first and second doped regions 105-1 and 105-2 may be triangular, rectangular, polygonal, circular, elliptical, or other suitable geometric shape, and in some embodiments, the first and second doped regions 105-1 and 105-2 may be a plurality of separate blocks disposed along the extending direction thereof (e.g., the Y-axis direction). Each of the first doped region 105-1 and the second doped region 105-2 overlaps with a partial region of the lower conductive portion 107, a partial region of the trench 106, and a partial region of the opening 115 in a plan view.
Fig. 3 is a schematic top view of some components of a semiconductor device according to another embodiment of the present invention. As shown in fig. 3, in this embodiment, the semiconductor device 100 includes a plurality of doped regions 105-3, 105-4, 105-5, and 105-6, wherein the doped regions 105-3, 105-4, 105-5, and 105-6 each have a second conductivity type, such as a P-type doped region, and the doped regions 105-3, 105-4, 105-5, and 105-6 are disposed in the epitaxial layer 103 and under the bottom surface of the trench 106, as can be seen in fig. 1. In a plane direction (e.g., XY plane) parallel to the surface of the substrate 101, the extension directions (e.g., X-axis directions) of these doped regions 105-3, 105-4, 105-5, and 105-6 are parallel to each other and are all perpendicular to the extension direction (e.g., Y-axis direction) of the lower conductive portion 107. In this embodiment, doped regions 105-3 and 105-6 are located on opposite sides of lower conductive portion 107, respectively, doped regions 105-4 and 105-5 are located between doped regions 105-3 and 105-6, and the outside edges of doped regions 105-3, 105-4, 105-5, and 105-6 are all beyond the edges of trench 106. In some embodiments, the dielectric liner 114 may have a plurality of openings 115, each opening 115 may have a triangular, rectangular, polygonal, circular, elliptical, or other suitable geometry in plan view, and these doped regions 105-3, 105-4, 105-5, and 105-6 may be disposed on opposite sides of each opening 115. In addition, the top view shape of each doped region 105-3, 105-4, 105-5, and 105-6 may be triangular, rectangular, polygonal, circular, elliptical, or other suitable geometric shape, and in some embodiments each doped region 105-3, 105-4, 105-5, and 105-6 may be a plurality of separate blocks disposed along its extension (e.g., in the X-axis direction). These doped regions 105-3, 105-4, 105-5, and 105-6 each overlap with a partial region of the underlying conductive portion 107, a partial region of the trench 106, and a partial region of the opening 115 in a top view.
Fig. 4 is a schematic top view of some components of a semiconductor device according to yet another embodiment of the present invention. As shown in fig. 4, in this embodiment, the semiconductor device 100 includes a first doped region 105-1 and a second doped region 105-2 disposed in the epitaxial layer 103 and under the bottom surface of the trench 106, and a plurality of doped regions 105-3, 105-4 and 105-5 are also disposed in the epitaxial layer 103 and are at the same level as the first doped region 105-1 and the second doped region 105-2, wherein the doped regions 105-1, 105-2, 105-3, 105-4 and 105-5 each have a second conductivity type, such as a P-type doped region, and the doped regions 105-1, 105-2, 105-3, 105-4 and 105-5 can be fabricated simultaneously using the same mask and the same ion implantation process. In a planar direction (e.g., XY plane) parallel to the surface of the substrate 101, the extension directions (e.g., Y axis direction) of the first doped region 105-1 and the second doped region 105-2 are parallel to the extension direction (e.g., Y axis direction) of the lower conductive portion 107, and the extension directions (e.g., X axis direction) of the plurality of doped regions 105-3, 105-4, and 105-5 are parallel to each other and are all perpendicular to the extension direction (e.g., Y axis direction) of the lower conductive portion 107, i.e., the extension directions (e.g., Y axis direction) of the first doped region 105-1 and the second doped region 105-2 are all perpendicular to the extension directions (e.g., X axis direction) of the other doped regions 105-3, 105-4, and 105-5. In this embodiment, the arrangement of the first doped region 105-1 and the second doped region 105-2 can suppress the surface electric field of the schottky contact more effectively. These doped regions 105-1, 105-2, 105-3, 105-4, and 105-5 each overlap with a portion of the underlying conductive portion 107, a portion of the trench 106, and a portion of the opening 115 of the dielectric liner 114 in top view, as described in detail above with reference to fig. 2 and 3, and not repeated here.
Fig. 5 is a schematic top-down layout of other components of a semiconductor device according to some embodiments of the present invention. As shown in the top-down layout 200A of fig. 5, in one embodiment, the first source region 118-1 and the second source region 118-2 of the semiconductor device 100 are located on opposite sides of the upper conductive portion 109 and are separated from the upper conductive portion 109 by the dielectric liner 114. The first heavily doped region 120-1 is located outside the first source region 118-1, the second heavily doped region 120-2 is located outside the second source region 118-2, and one source contact 134 overlaps the first heavily doped region 120-1 and a portion of the first source region 118-1, and the other source contact 134 overlaps the second heavily doped region 120-2 and a portion of the second source region 118-2, as viewed from above.
In addition, as shown in the top-down layout 200B of fig. 5, in this embodiment, the semiconductor device 100 includes a plurality of first heavily doped regions 120-1 disposed in the region of the first source region 118-1 and a plurality of second heavily doped regions 120-2 disposed in the region of the second source region 118-2, and in the embodiment of the top-down layout 200B, the area of the source contact 134 in the embodiment of the top-down layout 200B is smaller than the area of the source contact 134 in the embodiment of the top-down layout 200A because the plurality of first heavily doped regions 120-1 and the plurality of second heavily doped regions 120-2 do not occupy additional area compared to the embodiment of the top-down layout 200A. In addition, the embodiment of the top-down layout 200B may further reduce the size (cell pitch) of the device cells of the semiconductor device 100.
Fig. 6, 7, 8, 9 and 10 are schematic cross-sectional views illustrating some stages of a method of fabricating a semiconductor device according to an embodiment of the invention. As shown in fig. 6, a substrate 101, such as a 4H type single crystal silicon carbide (4H-SiC) substrate, is first provided, and then an epitaxial growth process is performed on a surface (e.g., a top surface) of the substrate 101 and simultaneously a first conductivity type doping is performed to form a first conductivity type first epitaxial layer 103-1, such as an N type 4H type single crystal silicon carbide (4H-SiC) epitaxial layer. Next, a second conductive type dopant is implanted into the first epitaxial layer 103-1 by using an ion implantation process and a mask to form a first doped region 105-1 and a second doped region 105-2 of the second conductive type, such as a P-type doped region, which are separated from each other. With continued reference to fig. 6, in step S101, a second epitaxial layer 103-2 of the first conductivity type is formed on the first epitaxial layer 103-1 by using an epitaxial growth process and adding dopants of the first conductivity type at the same time, and the first doped region 105-1 and the second doped region 105-2 are covered. The second epitaxial layer 103-2 may have the same composition as the first epitaxial layer 103-1, for example, an N-type 4H-type single crystal silicon carbide (4H-SiC) epitaxial layer, and the first epitaxial layer 103-1 and the second epitaxial layer 103-2 together constitute the epitaxial layer 103 of fig. 1.
Referring still to fig. 6, in step S103, a second conductive type well region 116, such as a P-type well region, is formed in the second epitaxial layer 103-2 by using different ion implantation processes and using different masks. A source region 118 of the first conductivity type, such as an N-type heavily doped region, is then formed in the well region 116. Then, a first heavily doped region 120-1 and a second heavily doped region 120-2 of a second conductivity type, such as a P-type heavily doped region, are formed in the well region 116, wherein the first heavily doped region 120-1 and the second heavily doped region 120-2 are located on opposite sides of the source region 118. With continued reference to fig. 6, at step S105, a trench 106 is formed through the source region 118, the well region 116 and the second epitaxial layer 103-2 by an etching process and using a hard mask (not shown), via the opening of the hard mask and using an etchant, and a bottom surface of the trench 106 exposes a portion of the first doped region 105-1, the second doped region 105-2 and the first epitaxial layer 103-1, while producing the first well region 116-1 and the second well region 116-2, and the first source region 118-1 and the second source region 118-2, which are located on opposite sides of the trench 106 as shown in fig. 1.
Next, referring to fig. 7, in step S107, a first dielectric layer 111 and a second dielectric layer 122 are sequentially deposited (patterned) on the sidewalls and bottom of the trench 106 and on the top surface of the epitaxial layer 103, wherein in one embodiment, the first dielectric layer 111 is silicon oxide, the second dielectric layer 122 is silicon nitride, and the thickness of the second dielectric layer 122 is greater than the thickness of the first dielectric layer 111, for example, 2 to 3 times the thickness of the first dielectric layer 111. Referring still to fig. 7, in step S109, the horizontal portion of the second dielectric layer 122 is removed by using an anisotropic etching process to form a first spacer 122-1 and a second spacer 122-2 on the first dielectric layer 111, which are respectively located on two opposite sidewalls of the trench 106.
With continued reference to fig. 7, in step S111, an etching process is performed on the first dielectric layer 111 using the first spacer 122-1 and the second spacer 122-2 as etching masks to remove the portions of the first dielectric layer 111 not covered by the first spacer 122-1 and the second spacer 122-2, leaving a portion 111-1 and 111-2 of the first dielectric layer 111 and forming an opening 115 exposing a portion 104 of the epitaxial layer 103, and a portion of the first doped region 105-1 and a portion of the second doped region 105-2. Referring still to fig. 7, in step S113, using an etching process having etching selectivity to the material of the first dielectric layer 111 and the second dielectric layer 122, the first spacer 122-1 and the second spacer 122-2 are removed, a portion 111-1 and 111-2 of the first dielectric layer 111 is remained, and then a first conductive material layer 124 is deposited in the trench 106 and on the top surface of the epitaxial layer 103, the first conductive material layer 124 fills the opening 115 and covers the portion 111-1 and 111-2 of the first dielectric layer 111. In some embodiments, the first conductive material layer 124 is, for example, schottky metal or P-doped polysilicon.
Then, referring to fig. 8, in step S115, an etching back (etching back) process is performed on the first conductive material layer 124 to form the lower conductive portion 107 in the trench 106. The lower conductive portion 107 fills the opening 115 and contacts a portion 104 of the epitaxial layer 103 exposed by the opening 115, as well as a portion of the first doped region 105-1 and a portion of the second doped region 105-2. In some embodiments, the top surface of the lower conductive portion 107 is lower than the bottom surfaces of the first well region 116-1 and the second well region 116-2. With continued reference to fig. 8, at step S117, a third dielectric layer 126 is deposited within trench 106 and on top of epitaxial layer 103, third dielectric layer 126 covering underlying conductive portion 107 and the aforementioned portions 111-1 and 111-2 of first dielectric layer 111. In some embodiments, the material of the third dielectric layer 126 may be the same as the first dielectric layer 111, for example, silicon oxide.
Still referring to fig. 8, in step S119, an etch-back process is performed on the third dielectric layer 126 and the aforementioned portions 111-1 and 111-2 of the first dielectric layer 111 to form the dielectric spacers 112 on the top surface of the lower conductive portion 107, and the top surfaces of the remaining portions 111-3 and 111-4 of the first dielectric layer 111 are level with the top surfaces of the dielectric spacers 112. With continued reference to fig. 8, in step S121, a fourth dielectric layer 127 is grown on the sidewalls of the trench 106 and the top surface of the epitaxial layer 103 by a thermal oxidation process, and the fourth dielectric layer 127 is located on the top surface of the remaining portions 111-3 and 111-4 of the first dielectric layer 111, wherein the fourth dielectric layer 127 is, for example, silicon oxide, and the thickness of the fourth dielectric layer 127 is smaller than that of the first dielectric layer 111.
Then, referring to fig. 9, in step S123, a second conductive material layer 128 is deposited on the fourth dielectric layer 127 and the dielectric spacers 112, the second conductive material layer 128 filling the trench 106 and being deposited over the top surface of the epitaxial layer 103. In some embodiments, the second conductive material layer 128 is, for example, polysilicon. With continued reference to fig. 9, in step S125, a chemical mechanical planarization (chemical mechanical planarization, CMP) process is performed on the second conductive material layer 128 and the fourth dielectric layer 127, and portions of the second conductive material layer 128 and the fourth dielectric layer 127 outside the trench 106 are removed to form the upper conductive portion 109 and complete the dielectric liner 114, wherein the dielectric liner 114 is composed of a portion of the fourth dielectric layer 127 and a portion of the first dielectric layer 111, the dielectric spacer 112 is composed of a portion of the third dielectric layer 126, and the upper conductive portion 109 and the lower conductive portion 107 are separated from each other by the dielectric spacer 112, and the dielectric liner 114 surrounds the upper Fang Daodian portion 109 and the lower conductive portion 107. Still referring to fig. 9, in step S127, an interlayer dielectric layer 130 is formed to cover the upper conductive portion 109 and the epitaxial layer 103. The interlayer dielectric 130 may comprise a plurality of dielectric layers, and a plurality of metal layers and a plurality of vias penetrating the dielectric layers may be formed in the interlayer dielectric 130 later as an interconnect layer (interconnect layer) for electrical connection.
Next, referring to fig. 10, in step S129, a plurality of contact openings 131 and 133 are formed in the interlayer dielectric layer 130 by using an etching process and using a mask, wherein the contact openings 131 expose a portion of the upper conductive portion 109, one contact opening 133 exposes a portion of the first source region 118-1 and the first heavily doped region 120-1, and the other contact opening 133 exposes a portion of the second source region 118-2 and the second heavily doped region 120-2. With continued reference to fig. 10, at step S131, a conductive material is deposited to fill the contact openings 131 and 133, and a Chemical Mechanical Planarization (CMP) process is performed to form a gate contact 132 and a plurality of source contacts 134, wherein the gate contact 132 is electrically coupled to the upper conductive portion 109 and the plurality of source contacts 134 are electrically coupled to the first source region 118-1 and the second source region 118-2, respectively. In addition, the lower conductive portion 107 is also electrically coupled to the source contact 134. Still referring to fig. 10, in step S133, a metal layer is deposited on a surface (e.g., bottom surface) of the substrate 101, and the metal layer is patterned to form the drain electrode 136, thereby completing the semiconductor device 100 of fig. 1.
According to an embodiment of the present invention, the semiconductor device has a split gate trench type structure in which a lower conductive portion of a gate is in contact with a portion of an epitaxial layer to form a vertically buried Schottky Barrier Diode (SBD), and at least one doped region (or referred to as a bias doped region) is present on one side of the portion of the epitaxial layer, the doped region having a conductivity type opposite to that of the epitaxial layer, and the doped region has a shield region (shield region) function. In addition to other semiconductor devices having only a split gate trench type structure and one shielding region directly under the trench, but without the vertically buried schottky barrier diode and at least one biased shielding region, the semiconductor device of embodiments of the present invention can maintain static (static) and dynamic (dynamic) performance, such as maintaining threshold voltage (threshold voltage, vt), on-state resistance (Ron), breakdown voltage (breakdown voltage, BV), flyback capacitance (reverse transfer capacitance, crss), high frequency quality factor (high-frequency figure ofmerit, HF-FOM), etc., the semiconductor device of embodiments of the present invention can achieve equivalent performance of about 6% to 20%, particularly at high frequency (e.g., 1.00 Hz), and can further reduce power consumption (more than the semiconductor devices of embodiments of the present invention) by reducing reverse recovery current (reverse recovery current, irr), reverse recovery charge (reverse recovery charge, qrr), turn-offenergy dissipation, eoff), turn-on energy consumption (turn-on energy dissipation, eon), total switching loss (total switching loss), etc., and operating at a higher frequency (e.00.g., lower power consumption than the semiconductor devices of the present invention of about 10.10% more power. In addition, according to the embodiment of the invention, when the vertically buried schottky barrier diode of the semiconductor device is manufactured, an additional photomask is not required, and a self-aligned (self-aligned) technology is used to complete a contact opening (contact opening) so as to save manufacturing cost.
The above description is only of the preferred embodiments of the present invention, and all the equivalent changes and modifications according to the claims should be considered as falling within the scope of the present invention.

Claims (20)

1. A semiconductor device, comprising:
a substrate;
an epitaxial layer having a first conductivity type and disposed on a first surface of the substrate;
a trench disposed in the epitaxial layer;
the grid structure is arranged in the groove and comprises an upper conductive part and a lower conductive part;
a dielectric spacer disposed between the upper conductive portion and the lower conductive portion;
a dielectric liner layer disposed in the trench and surrounding the gate structure, the dielectric liner layer having an opening at a bottom surface of the trench, a portion of the lower conductive portion being filled in the opening, and the lower conductive portion and a portion of the epitaxial layer forming a schottky barrier diode; and
a first doped region having a second conductivity type and disposed in the epitaxial layer and located under the bottom surface of the trench and on one side of the lower conductive portion,
wherein the portion of the epitaxial layer and a portion of the first doped region are both in contact with the underlying conductive portion.
2. The semiconductor device of claim 1, further comprising a second doped region of the second conductivity type disposed in the epitaxial layer and located below the bottom surface of the trench and on the other side of the lower conductive portion, a portion of the second doped region being in contact with the lower conductive portion, wherein the first doped region and the second doped region are separated from each other and are located on opposite sides of the opening, respectively.
3. The semiconductor device of claim 2, wherein the first doped region and the second doped region each overlap a portion of the underlying conductive portion in a top view, and the portion of the epitaxial layer is located between the first doped region and the second doped region.
4. The semiconductor device of claim 2, wherein the first doped region and the second doped region are in contact with the dielectric liner at the bottom of the trench, and an outer edge of the first doped region and an outer edge of the second doped region each extend beyond an edge of the trench in plan view.
5. The semiconductor device according to claim 2, wherein the first doped region, the second doped region and the lower conductive portion are all parallel to each other in an extending direction in a plane direction parallel to a surface of the substrate in a plan view.
6. The semiconductor device according to claim 2, wherein the first doped region and the second doped region each have an extension direction perpendicular to an extension direction of the lower conductive portion in a plane direction parallel to a surface of the substrate in a top view.
7. The semiconductor device of claim 6, further comprising a third doped region of the second conductivity type disposed in the epitaxial layer and under the bottom surface of the trench, the third doped region being located between the first doped region and the second doped region, and the first doped region, the second doped region and the third doped region being at a same level, in a planar direction parallel to the surface of the substrate as viewed from above, the third doped region extending in a direction parallel to the first doped region and the second doped region.
8. The semiconductor device of claim 6, further comprising a third doped region and a fourth doped region of the second conductivity type disposed in the epitaxial layer below the bottom surface of the trench, the first doped region, the second doped region, the third doped region and the fourth doped region being at a same level such that, when viewed from above, in a planar direction parallel to the surface of the substrate, the extension directions of the third doped region and the fourth doped region are perpendicular to the extension directions of the first doped region and the second doped region and parallel to the extension direction of the underlying conductive portion.
9. The semiconductor device according to claim 1, further comprising:
a first well region and a second well region having the second conductivity type, disposed in the epitaxial layer and respectively located at two opposite sides of the trench;
a first source region and a second source region having the first conductivity type and respectively disposed in the first well region and the second well region; and
and a drain electrode arranged on a second surface of the substrate.
10. The semiconductor device of claim 1, wherein the upper conductive portion is electrically coupled to a gate contact and the lower conductive portion is electrically coupled to a source contact.
11. The semiconductor device of claim 1, wherein the material of the lower conductive portion comprises a schottky metal or a doped polysilicon and the material of the epitaxial layer comprises silicon carbide or the material of the lower conductive portion comprises a schottky metal and the material of the epitaxial layer comprises silicon carbide, monocrystalline silicon or polysilicon.
12. The semiconductor device of claim 2, wherein a top view shape of the opening comprises a triangle, rectangle, polygon, circle, or oval, and a top view shape of the first doped region and the second doped region each comprises a triangle, rectangle, polygon, circle, or oval.
13. A method for manufacturing a semiconductor device, comprising:
providing a substrate, and forming an epitaxial layer on a first surface of the substrate, wherein the epitaxial layer has a first conductivity type;
forming a first doped region and a second doped region in the epitaxial layer, wherein the first doped region and the second doped region have a second conductivity type;
forming a trench in the epitaxial layer, wherein the bottom surface of the trench exposes the first doped region and the second doped region;
forming a first dielectric layer on the side wall and the bottom surface of the trench in a forward direction;
forming a first spacer and a second spacer on the first dielectric layer and on two opposite sidewalls of the trench;
etching the first dielectric layer to form an opening by using the first spacer and the second spacer as a mask, wherein the opening exposes a portion of the epitaxial layer and a portion of each of the first doped region and the second doped region;
forming a lower conductive portion in the trench and filling the opening, wherein the lower conductive portion is in contact with the portion of the epitaxial layer; and
a dielectric spacer and an upper conductive portion are formed in the trench, and the upper conductive portion and the lower conductive portion are separated from each other by the dielectric spacer.
14. The method for manufacturing a semiconductor device according to claim 13, further comprising, before forming the trench:
forming a well region in the epitaxial layer, the well region having the second conductivity type; and
forming a source region in the well region, the source region having the first conductivity type,
wherein the trench is formed in the epitaxial layer through the source region and the well region.
15. The method for manufacturing a semiconductor device according to claim 14, further comprising:
forming a drain electrode on a second surface of the substrate;
forming a gate contact electrically coupled to the upper conductive portion; and
a source contact is formed and electrically coupled to the source region, wherein the lower conductive portion is electrically coupled to the source contact.
16. The method of manufacturing a semiconductor device according to claim 13, wherein forming the first spacer and the second spacer comprises:
depositing a second dielectric layer on the first dielectric layer in a forward direction; and
an anisotropic etch process is used to remove horizontal portions of the second dielectric layer.
17. The method of claim 13, wherein the first spacer and the second spacer are removed after the opening of the first dielectric layer is formed and before the lower conductive portion is formed.
18. The method of claim 13, wherein forming the lower conductive portion comprises depositing a first conductive material layer and etching back the first conductive material layer, and forming the upper conductive portion comprises depositing a second conductive material layer and performing a chemical mechanical planarization process on the second conductive material layer.
19. The method of claim 18, wherein the second conductive material layer comprises polysilicon, the first conductive material layer comprises a schottky metal or a doped polysilicon, and the epitaxial layer comprises silicon carbide, or the first conductive material layer comprises a schottky metal and the material of the epitaxial layer comprises silicon carbide, single crystal silicon, or polysilicon, and wherein the lower conductive portion and the portion of the epitaxial layer form a schottky barrier diode.
20. The method of claim 13, wherein forming the dielectric spacer comprises depositing a third dielectric layer over the lower conductive portion and etching back the third dielectric layer.
CN202210879733.1A 2022-07-25 2022-07-25 Semiconductor device and method for manufacturing the same Pending CN117497586A (en)

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