CN215679358U

CN215679358U - Hypervelocity information acquisition and storage equipment based on ZYNQ chip

Info

Publication number: CN215679358U
Application number: CN202121144697.1U
Authority: CN
Inventors: 曾桂根; 张学逸
Original assignee: Nanjing University of Posts and Telecommunications
Current assignee: Nanjing University of Posts and Telecommunications
Priority date: 2021-05-26
Filing date: 2021-05-26
Publication date: 2022-01-28
Anticipated expiration: 2031-05-26

Abstract

The utility model discloses a ZYNQ chip-based ultra-high-speed information acquisition and storage device, which comprises a logic controller slot, and is used for installing a logic controller, an expansion module comprising a sensor expansion slot and an FMC expansion slot, the sensor expansion slot and the FMC expansion slot are both electrically connected with the logic controller slot, the memory module comprises a memory slot and a memory strip arranged in the memory slot, the memory slot is electrically connected with the logic controller slot, the power module is electrically connected with the logic control slot, by modularizing the acquisition part and further by using an onboard interface supporting high data transmission, throughput of large flow data can be realized, meanwhile, various types of interfaces are arranged, so that the device can be connected with various sensors, the use of various application scenes can be met, and the high-speed acquisition and storage of data can be realized.

Description

Hypervelocity information acquisition and storage equipment based on ZYNQ chip

Technical Field

The utility model relates to ultrahigh-speed information acquisition and storage equipment based on a ZYNQ chip, belonging to the technical field of radio verification.

Background

At present, a high-speed data acquisition, transmission, storage and playback system has wide requirements and applications in the fields of industry and communication, and the acquisition, transmission and real-time storage of a large amount of data are always difficult points in the field of digital signal processing, however, the acquisition and storage of digital signals are often separated, or special acquisition cards such as camera video and the like cannot meet the condition of simultaneously supporting different high-speed data acquisition cards or simultaneous handling of large data of multiple sensors. Meanwhile, the board card is too large to adapt to distributed application.

In the algorithm research in the aspects of wireless positioning, multi-antenna MIMO systems and the like, multi-channel ultrahigh-speed radio baseband signals need to be simultaneously acquired from a field complex radio environment for algorithm simulation.

The existing acquisition and testing platform only realizes a built-in NAND Flash solid state storage array or a mode of connecting a gigabit optical fiber with a PC, on one hand, the mode of the built-in solid state storage array can cause the difficulty in replacement after the particles are damaged after a large number of times of reading and writing, thereby increasing the replacement cost of the particles, on the other hand, the mode of connecting the gigabit optical fiber with the PC causes the acquisition system to be incapable of remote transmission or even remote real-time monitoring due to the length of a connecting line, most of the existing platforms are in a special field, such as image acquisition, high-speed digital-to-analog conversion and the like, the single interface cannot support not only the transmission of wireless communication but also various sensors simultaneously, the throughput of mass data can still be caused when a large number of sensors sample simultaneously, certain flexibility is lacked, and the function is single, meanwhile, the transmission efficiency is low, and the information interaction capability during sensor sampling cannot be well met.

The information disclosed in this background section is only for enhancement of understanding of the general background of the utility model and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.

SUMMERY OF THE UTILITY MODEL

The utility model aims to overcome the defects in the prior art, and provides a ZYNQ chip-based ultrahigh-speed information acquisition and storage device to solve the technical problems that in the prior art, a single interface cannot support various sensors of different types, mass data throughput is caused when a large number of sensors are acquired simultaneously, the transmission efficiency is low due to single function and simultaneous transmission, and the information interaction capacity during sensor sampling cannot be met.

In order to solve the technical problems, the utility model is realized by adopting the following technical scheme:

the super-high speed information acquisition and storage device based on the ZYNQ chip comprises

The logic controller slot is used for installing the logic controller;

the expansion module comprises a sensor expansion slot and an FMC expansion slot, and the sensor expansion slot and the FMC expansion slot are electrically connected with the logic controller slot;

and the memory module comprises a memory slot and a memory strip installed in the memory slot, and the memory slot is electrically connected with the logic controller slot.

And the power module is electrically connected with the logic control slot.

As a preferred technical solution of the present invention, the power module includes a main power supply and an auxiliary power supply, the main power supply is electrically connected to an external power supply through a power adapter, an output voltage of the main power supply is 12V, the auxiliary power supply is electrically connected to the main power supply, and the auxiliary power supply includes a 5V voltage output, a 3.3V voltage output, a 1.8V voltage output, and a 1.2V voltage.

As a preferred technical solution of the present invention, the auxiliary power supply is electrically connected to the logic controller slot.

As a preferred technical scheme of the utility model, the memory slot is an M.2Mkey slot.

As a preferred technical scheme, the device also comprises a debugging module, wherein the debugging module is electrically connected with the logic controller through a logic controller slot, and the debugging module comprises an MCU JTAG debugging interface, an FPGA JTAG downloading interface, a gigabit network port, a USB interface, an SD card module, a BOOT selection switch, a UART communication serial port and a serial port transceiving debugging interface.

As a preferred technical scheme of the utility model, the logic controller is a ZYNQ7035 chip.

Compared with the prior art, the utility model has the following beneficial effects:

according to the utility model, the collection part is modularized, and an onboard interface supporting high-speed data transmission is further used, so that the handling of large-flow data can be realized, and meanwhile, various types of interfaces are arranged, so that various sensors can be connected, the use of various application scenes can be met, and the high-speed collection and storage of data can be realized.

Drawings

FIG. 1 is a schematic structural view of the present invention;

fig. 2 is a block diagram of the architecture of the present invention.

In the figure: 1-a sensor expansion slot; 2-FMC expansion slots; 3-a memory slot; 4-a logic controller; 5-a main power supply; 6-auxiliary power supply; 7-MCU JTAG debug interface; 8-kilomega network port; 9-USB interface; 10-SD card module; 11-BOOT selection switch; 12-UART communication serial port; 13-serial port receiving and dispatching debugging interface.

Detailed Description

The utility model is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention. Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.

As shown in fig. 1 to 2, the ZYNQ chip-based ultra-high speed information acquisition and storage device includes a logic controller slot for installing a logic controller 4, an expansion module including a sensor expansion slot 1 and an FMC expansion slot 2, the sensor expansion slot 1 and the FMC expansion slot 2 both electrically connected to the logic controller slot, and the storage module including a memory slot 3 and a memory strip installed in the memory slot 3, wherein the memory slot 3 is electrically connected to the logic controller slot, and a power module is electrically connected to the logic controller slot.

It should be noted that the logic controller slot, the sensor expansion slot 1, the FMC expansion slot 2, the memory slot 3, and the power module are all disposed on the substrate, and the substrate is used for carrying and realizing normal connection between different components.

The logic controller 4 is a ZYNQ7035 chip, the logic controller 4 can be of other models in the actual production and processing process, and the logic controller slots are correspondingly arranged according to the logic controller 4.

4 DDR3 cache particles are loaded on the substrate, the highest operation speed of the DDR3 SDRAM at the PS end can reach 533MHz (data rate of 1066 Mbps), the highest operation speed of the DDR3 SDRAM at the PL end can reach 800MHz (data rate of 1600 Mbps), and real-time data acquisition and real-time storage are guaranteed under the scheme of DMA and ping-pong transmission.

Compared with a common FPGA transmission architecture, the Ethernet FPGA type ZYNQ7035 chip is used, on the premise of supporting a PCIe serial bus, a large-scale programmable logic block can support the realization of a complex real-time logic preprocessing algorithm on a signal acquired at a high speed, an ARM A9 architecture is adopted for the rest of embedded parts, a Linux operating system is supported, the realization of the complex data processing algorithm is made possible, the difficulty in building a man-machine interaction platform is reduced, and meanwhile, the use of other universal interfaces is made simpler.

The power module comprises a main power supply 5 and an auxiliary power supply 6, the main power supply 5 is electrically connected with an external power supply through a power adapter, the output voltage of the main power supply 5 is 12V, the auxiliary power supply 6 is electrically connected with the main power supply 5, and the auxiliary power supply 6 comprises 5V voltage output, 3.3V voltage output, 1.8V voltage output and 1.2V voltage.

The main power supply 5 is electrically connected with an external power supply through the power adapter, the power supply of the whole device is switched on and off, the power input is prevented from flowing backwards and being short-circuited, the auxiliary power supply 6 is used for converting the voltage output by the main power supply 5, so that the main power supply can normally supply power for other parts, and the multiple voltage outputs arranged here can ensure that the main power supply can normally work when hardware with multiple different working voltages is expanded.

It should be noted that the auxiliary power supply 6 is electrically connected to the logic controller slot, and the supply voltage of the ZYNQ7035 chip is 5V.

FMC expansion slot 2 is FMC standard protocol, FMC expansion slot 2 includes processing engine and I/O engine, said primary 5 and auxiliary 6 power supply outputs are electrically connected to FMC expansion slot 2 input, FMC expansion slot 2 includes FMC-LPC expansion slot and FMC-HPC expansion slot.

The FMC-LPC expansion slot uses an FMC standard protocol made by XILINX, the FMC is called as FPGA Mezzanine Card, the FPGA Mezzanine Card is the FPGA middle layer board Card, and the whole FMC module consists of a daughter board module and a Card loading module. The daughter card and the carrier card are connected through a connector, the connector on the daughter card module uses a male socket (male), the connector on the carrier card uses a female socket (female), and the pins of the carrier card connector and the chip with configurable IO resources are connected.

Example one

The pins are connected together through a PCB design, connector pins on the daughter board module and I/O interfaces are also connected through the PCB design, different I/O interfaces can be designed on the daughter board PCB to realize different functions, therefore, different expansion functions can be realized through the design of the daughter board by the same card carrier, the application of the chip is more flexible, except for more flexible configuration, the FPGA sandwich card (FMC) standard simultaneously supports the signal transmission rate of 10Gb/s, the potential total bandwidth between the sandwich board and the card carrier reaches 40Gb/s, the FMC standard aims to provide the standard sandwich board (daughter card) size, the connector and the module interface for the FPGA on the base board (card carrier), the I/O interfaces are separated from the FPGA through the mode, the design of the I/O interface module is simplified, and the repeated utilization rate of the card carrier is maximized.

The use of the FMC standard modularizes the board design into two parts, a processing engine (card-loaded) and an I/O engine (FMC module), so that a single card-loaded (including one or more FPGAs and the appropriate number and type of FMC connectors) can be reused as the basis for different applications, and thus the FMC-LPC extension slot can support not only ADI official high-speed AD/DA acquisition cards but even software radio modules.

The FMC-LPC expansion slot supports single-ended and differential signaling rates up to 2Gb/s and signaling rates up to 10Gb/s to the FPGA serial connector, except for 34 user-defined differential pairs, the LPC connector provides 1 serial transceiver pair, a clock, a JTAG interface and 1I 2C interface as an optional support for the underlying Intelligent Platform Management Interface (IPMI) commands, and furthermore, both the HPC and LPC connectors use the same mechanical connector, the only difference being which signals are actually transplanted, so that a card using the LPC connector can also be plugged at the HPC, and the HPC card can also provide many derived functions when plugged at the LPC, provided that it is properly designed, and finally, the FMC expansion slot is powered by both the primary power supply 5 and the auxiliary power supply 6, the requirements under different design conditions are met.

The sensor expansion slot 1 adopts a simple ox horn seat interface mode and can be used for plugging different types of sensor modules, if the FMC-LPC expansion slot is designed for the requirement of high-speed few-channel acquisition, the design of the sensor expansion slot is used for simultaneously supporting simultaneous signal acquisition of multiple sensors, no matter in automobile test, intelligent driving or aerospace test, more than several signal quantities need to be simultaneously acquired, and under the condition that dozens of or even nearly hundreds of signal quantities are simultaneously acquired and stored, the combination of the sensor expansion slot and the memory slot 5 is used, so that the whole system is small and exquisite and convenient.

The memory slot 3 is an m.2mkey slot, the memory stripe is installed on the substrate through the m.2mkey slot, and the memory stripe is preferably DDR3 cache particles. NVMe has many advantages over AHCI. Low latency, maximum support for 64K queues, simpler command execution, etc., resulting in faster speed, lower latency for PCIe SSDs. Supporting the PCIe interface protocol.

In the utility model, PCIe Gen 2X 4 is used for data transmission, PCI-e2.0 protocol supports 5.0 GT/s, that is, each Lane supports 5G bits transmitted in each second, at the same time, 8b/10b coding scheme is used in physical layer protocol, thus obtaining 2GB/s data read-write speed, satisfying most high speed signal real-time acquisition and nonvolatile storage requirement, besides, different from common connection with PC, in ZYNQ7035 software system design, PCIe uses DMA mode to transmit data, adopting the mode to transmit data, while ensuring data transmission speed, really realizing reality, finally, standard M.2M key interface can support multiple storage strips on the market, can support expansion of storage strips with different capacities, thus being suitable for different data volume size occasions, in addition, the storage bar can be conveniently exchanged by using the slot, particularly, the storage particles can be easily damaged by reading and writing data at high speed for multiple times, and compared with a method of arranging a NAND Flash solid-state storage array in a board card, the time for exchanging the storage particles is greatly saved by using the storage slot 5, and the cost for exchanging the storage particles is also greatly reduced.

The debugging module is electrically connected with the logic controller 4 through a logic controller slot and comprises an MCU JTAG debugging interface 7, an FPGA JTAG downloading interface, a kilomega network port 8, a USB interface 9, an SD card module 10, a BOOT selection switch 11, a UART communication serial port 12 and a serial port transceiving debugging interface 13.

An FPGA JTAG download interface is used for downloading and debugging a logic controller, simultaneously, a multi-core multi-thread processing mode is adopted in consideration of large and small core design used in an acquisition system, an MCU JTAG debugging interface is added in the equipment system for satisfying the download and debugging of a self-made CPU small core, in addition, an SD card module 10 and a BOOT selection switch 11 are both connected with a ZYNQ7035 core chip for supporting SD card image loading and multiple BOOT mode selection, a serial port transceiving debugging interface 13 receives an external asynchronous serial signal for realizing simple command line interaction, the system running state can be monitored in real time while interaction experience is increased, in addition, a gigabit network port 8 uses a KSZ9031RNX chip for supporting the network port transmission of an RGMII protocol, simultaneously supporting 10/100/1000Mbps network transmission rate and MDI/MDX self-adaptation, various speed self-adaptation, and Master/Slave self-adaptation enables the communication and data transmission with a PC to be more convenient and faster, the physical interface USB2.0X4 enables high-speed USB2.0 Host mode data communication while the interface components are more scalable and versatile to support external power transfer.

The utility model also comprises an Audio interface and an HDMI output interface, wherein the Audio interface is used for outputting Audio signals, and the HDMI output interface is mainly used for outputting digital high-definition signals.

The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.

Claims

1. The ultrahigh-speed information acquisition and storage equipment based on the ZYNQ chip is characterized by comprising

A logic controller slot for installing a logic controller (4);

the expansion module comprises a sensor expansion slot (1) and an FMC expansion slot (2), wherein the sensor expansion slot (1) and the FMC expansion slot (2) are electrically connected with the logic controller slot;

the memory module comprises a memory slot (3) and a memory strip installed in the memory slot (3), and the memory slot (3) is electrically connected with the logic controller slot;

and the power module is electrically connected with the logic control slot.

2. The ZYNQ chip-based ultra-high-speed information acquisition and storage device is characterized in that the power module comprises a main power supply (5) and an auxiliary power supply (6), the main power supply (5) is electrically connected with an external power supply through a power adapter, the output voltage of the main power supply (5) is 12V, the auxiliary power supply (6) is electrically connected with the main power supply (5), and the auxiliary power supply (6) comprises a 5V voltage output, a 3.3V voltage output, a 1.8V voltage output and a 1.2V voltage.

3. The ZYNQ chip-based ultra-high speed information acquisition and storage device according to claim 2, wherein the auxiliary power supply (6) is electrically connected with a logic controller slot.

4. The ZYNQ chip-based ultra-high-speed information acquisition and storage device according to claim 1, wherein the memory slot (3) is an M.2Mkey slot.

5. The ZYNQ chip-based ultra-high-speed information acquisition and storage device is characterized by further comprising a debugging module, wherein the debugging module is electrically connected with the logic controller (4) through a logic controller slot, and comprises an MCU JTAG debugging interface (7), an FPGA JTAG downloading interface, a gigabit network port (8), a USB interface (9), an SD card module (10), a BOOT selection switch (11), a UART communication serial port (12) and a serial port transceiving debugging interface (13).

6. The ZYNQ-chip-based ultra-high-speed information acquisition and storage device according to claim 1, wherein the logic controller (4) is a ZYNQ7035 chip.