CN215656528U - Structure for detecting boxed wafers - Google Patents

Structure for detecting boxed wafers Download PDF

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Publication number
CN215656528U
CN215656528U CN202122157373.8U CN202122157373U CN215656528U CN 215656528 U CN215656528 U CN 215656528U CN 202122157373 U CN202122157373 U CN 202122157373U CN 215656528 U CN215656528 U CN 215656528U
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China
Prior art keywords
guide rail
linear guide
fixed
placing
detection
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Application number
CN202122157373.8U
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Chinese (zh)
Inventor
忻超
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhongguancun Technology Leasing Co ltd
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Ningbo Qting Vision Technology Co ltd
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Priority to CN202122157373.8U priority Critical patent/CN215656528U/en
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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)

Abstract

The utility model discloses a structure for detecting boxed wafers, which comprises a first linear guide rail and a second linear guide rail which are fixed on a worktable, wherein a detection placing box is fixed on a slide block on the first linear guide rail and the second linear guide rail, the structure also comprises a conveying device, a chip wafer defect detecting camera is fixed above the first linear guide rail, a qualified chip correcting camera is also fixed above the first linear guide rail, a unqualified chip correcting camera is fixed above the second linear guide rail, the conveying device can realize three-axis movement and help convey unqualified wafers passing through the lower part of the chip wafer defect detecting camera to the second linear guide rail, the wafers of the utility model are firstly placed on the first linear guide rail, after the two-time detection by the chip wafer defect detecting camera and the qualified chip correcting camera, if the unqualified wafers are unqualified, a conveying sucker of the conveying device places the wafers on the second linear guide rail, and (4) passing the checking of the unqualified chip correction camera, and realizing the qualified and unqualified sorting of the wafer.

Description

Structure for detecting boxed wafers
Technical Field
The utility model belongs to the field of detection, and particularly relates to a structure for detecting a boxed wafer.
Background
Traditional semiconductor products need to be photographed and detected when detecting, unqualified wafers to be detected are removed, but sometimes deviation is easy to occur in once photographing detection, and therefore the structure for detecting the boxed wafers for overcoming the defects is very important.
SUMMERY OF THE UTILITY MODEL
In order to solve at least one technical problem, the utility model provides a boxed wafer detection structure, which comprises a first linear guide rail and a second linear guide rail which are fixed on a workbench in parallel, wherein sliders on the first linear guide rail and the second linear guide rail are respectively fixed with a detection placing box; the detection placing box comprises a detection box body, wherein stand columns are integrally formed at four corners of the detection box body, placing grooves are formed in the stand columns, the detection placing box further comprises placing plates, the placing plates are placed at four placing positions formed by the placing grooves, and wafers are placed on the placing plates. The depth of the placing groove is greater than the thickness of the placing plate.
The carrying device comprises an X-axis linear guide rail fixed on the workbench, a Y-axis linear guide rail is fixed on a sliding block of the X-axis linear guide rail, a Z-axis linear guide rail is fixed on a sliding block of the Y-axis linear guide rail, and the carrying sucker is fixed on a sliding block of the Z-axis linear guide rail. And a connecting rod is fixed between the carrying sucker and the slide block of the Z-axis linear guide rail.
The upper surface integrated into one piece who places the board has the circular arc arch of matrix arrangement, because the wafer is thinner, it and place can form the adsorption affinity between the board for the transport sucking disc is difficult to adsorb, and the circular arc arch that consequently sets up can reduce area of contact, and can provide certain friction, is convenient for steadily place and transport the absorption transport of sucking disc.
Compared with the prior art, the utility model has the advantages that: the wafer sorting device is simple in structure, the carrying device can realize three-axis movement, and helps to carry unqualified wafers passing through the lower part of the chip wafer defect detection camera to the second linear guide rail.
Drawings
FIG. 1 is a perspective view of the present invention;
FIG. 2 is a perspective view of the test placement box of the present invention;
FIG. 3 is a schematic cross-sectional view of the subject holding board;
reference numerals: 1-a first linear guide; 2-a second linear guide; 3-detecting and placing the box; 4, carrying the sucker; 5-chip wafer defect detection camera; 6-qualified chip correction camera; 7-unqualified chip correction camera; 8, detecting a box body; 9-upright post; 10-placing a groove; 11-placing a plate; 12-X axis linear guide; 13-Y axis linear guide; 14-Z axis linear guide; 15-a connecting rod; 16-arc bulge; 17-wafer.
Detailed Description
In order that those skilled in the art will better understand the utility model and thus more clearly define the scope of the utility model as claimed, it is described in detail below with respect to certain specific embodiments thereof. It should be noted that the following is only a few embodiments of the present invention, and the specific direct description of the related structures is only for the convenience of understanding the present invention, and the specific features do not of course directly limit the scope of the present invention.
Referring to the attached drawings, the utility model adopts the following technical scheme, and provides a boxed wafer detection structure which comprises a first linear guide rail and a second linear guide rail which are fixed on a workbench in parallel, wherein detection placing boxes are fixed on sliding blocks on the first linear guide rail and the second linear guide rail respectively; the detection placing box comprises a detection box body, wherein stand columns are integrally formed at four corners of the detection box body, placing grooves are formed in the stand columns, the detection placing box further comprises placing plates, the placing plates are placed at four placing positions formed by the placing grooves, and wafers are placed on the placing plates. The depth of the placing groove is greater than the thickness of the placing plate.
The carrying device comprises an X-axis linear guide rail fixed on the workbench, a Y-axis linear guide rail is fixed on a sliding block of the X-axis linear guide rail, a Z-axis linear guide rail is fixed on a sliding block of the Y-axis linear guide rail, and the carrying sucker is fixed on a sliding block of the Z-axis linear guide rail. And a connecting rod is fixed between the carrying sucker and the slide block of the Z-axis linear guide rail.
The upper surface integrated into one piece who places the board has the circular arc arch of matrix arrangement, because the wafer is thinner, it and place can form the adsorption affinity between the board for the transport sucking disc is difficult to adsorb, and the circular arc arch that consequently sets up can reduce area of contact, and can provide certain friction, is convenient for steadily place and transport the absorption transport of sucking disc.
The chip wafer defect detection camera, the qualified chip correction camera and the unqualified chip correction camera can be fixed on the workbench through the bracket, so that the lens of the cameras faces downwards.
Compared with the prior art, the utility model has the advantages that: the wafer sorting device is simple in structure, the carrying device can realize three-axis movement, and helps to carry unqualified wafers passing through the lower part of the chip wafer defect detection camera to the second linear guide rail.
The above description is not intended to limit the present invention, and the present invention is not limited to the above examples, and variations, modifications, additions and substitutions which may be made by those skilled in the art within the spirit of the present invention are within the scope of the present invention.

Claims (5)

1. A structure for detecting a boxed wafer is characterized in that: the wafer defect detection device comprises a first linear guide rail (1) and a second linear guide rail (2) which are fixed on a workbench and arranged in parallel, wherein detection placing boxes (3) are fixed on sliding blocks on the first linear guide rail (1) and the second linear guide rail (2), the wafer defect detection device also comprises a carrying device, the carrying device comprises a carrying sucker (4), the wafer on the detection placing box (3) on the first linear guide rail (1) is placed on the detection placing box (3) on the second linear guide rail (2) by the carrying sucker (4), a wafer defect detection camera (5) is fixed above the first linear guide rail (1), a qualified chip correction camera (6) is fixed above the first linear guide rail (1), and an unqualified chip correction camera (7) is fixed above the second linear guide rail (2);
the detection placing box (3) comprises a detection box body (8), wherein four corners of the detection box body (8) are integrally formed with a stand column (9), a placing groove (10) is formed in the stand column (9), the detection placing box further comprises a placing plate (11), the placing plate (11) is placed at four placing positions formed by the placing groove (10), and wafers are placed on the placing plate (11).
2. The structure for inspecting boxed wafers according to claim 1, characterized in that: the depth of the placing groove (10) is larger than the thickness of the placing plate (11).
3. The structure for inspecting boxed wafers according to claim 1, characterized in that: the carrying device comprises an X-axis linear guide rail (12) fixed on a workbench, a Y-axis linear guide rail (13) is fixed on a sliding block of the X-axis linear guide rail (12), a Z-axis linear guide rail (14) is fixed on a sliding block of the Y-axis linear guide rail (13), and the carrying sucker (4) is fixed on a sliding block of the Z-axis linear guide rail (14).
4. The structure for inspecting boxed wafers according to claim 2, characterized in that: and a connecting rod (15) is fixed between the carrying sucker (4) and the slide block of the Z-axis linear guide rail (14).
5. The structure for inspecting boxed wafers according to claim 1, characterized in that: the upper surface of the placing plate (11) is integrally formed with arc bulges (16) which are arranged in a matrix.
CN202122157373.8U 2021-09-07 2021-09-07 Structure for detecting boxed wafers Active CN215656528U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202122157373.8U CN215656528U (en) 2021-09-07 2021-09-07 Structure for detecting boxed wafers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202122157373.8U CN215656528U (en) 2021-09-07 2021-09-07 Structure for detecting boxed wafers

Publications (1)

Publication Number Publication Date
CN215656528U true CN215656528U (en) 2022-01-28

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CN202122157373.8U Active CN215656528U (en) 2021-09-07 2021-09-07 Structure for detecting boxed wafers

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117410211A (en) * 2023-12-11 2024-01-16 天通控股股份有限公司 Coding and defect identification system and control method for boxed wafers

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117410211A (en) * 2023-12-11 2024-01-16 天通控股股份有限公司 Coding and defect identification system and control method for boxed wafers
CN117410211B (en) * 2023-12-11 2024-03-22 天通控股股份有限公司 Coding and defect identification system and control method for boxed wafers

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GR01 Patent grant
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Effective date of registration: 20221123

Address after: 314200 Room 134, Building 6, No. 2 Chuangye Road, Xindai Town, Pinghu City, Jiaxing City, Zhejiang Province

Patentee after: Jiaxing Qingfei Photoelectric Technology Co.,Ltd.

Address before: 315100 room 702, building a, Kexin building, No. 655, bachelor Road, Yinzhou District, Ningbo City, Zhejiang Province

Patentee before: NINGBO QTING VISION TECHNOLOGY Co.,Ltd.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20240110

Address after: 610, Floor 6, Block A, No. 2, Lize Middle Second Road, Chaoyang District, Beijing 100102

Patentee after: Zhongguancun Technology Leasing Co.,Ltd.

Address before: 314200 Room 134, Building 6, No. 2 Chuangye Road, Xindai Town, Pinghu City, Jiaxing City, Zhejiang Province

Patentee before: Jiaxing Qingfei Photoelectric Technology Co.,Ltd.