CN215641535U

CN215641535U - Synchronous sampling system for providing electric energy parameter analysis

Info

Publication number: CN215641535U
Application number: CN202120293161.XU
Authority: CN
Inventors: 吴卓倚; 万飞; 陈祈星; 袁吉顺; 刘伟
Original assignee: Chengdu Nengtong Technology Co ltd
Current assignee: Chengdu Nengtong Technology Co ltd
Priority date: 2021-02-02
Filing date: 2021-02-02
Publication date: 2022-01-25
Anticipated expiration: 2031-02-02

Abstract

The utility model provides a synchronous sampling system for providing electric energy parameter analysis, which comprises an FPGA unit, a multi-path synchronous sampling ADC unit, a fundamental wave capturing ADC unit, a DDS frequency synthesizer and a synchronous time window system, wherein the FPGA unit is connected with the multi-path synchronous sampling ADC unit; the frequency can be obtained within ms by adopting a logic device FPGA, and the fundamental frequency of the measured power grid can be obtained. And the frequency value can be immediately transmitted to a frequency generation device outside the FPGA, a DDS is selected as a frequency generator, the DDS can support a frequency from several KHz to tens of MHz, and the frequency interval can reach 20000000/16777216 ≈ 1.2Hz or even 20000000/4294967296 ≈ 0.005 Hz. And the whole reaction time can be completed within tens of ms, so the method can effectively solve the difficulty of clock synthesis in the prior time window synchronous sampling technology.

Description

Synchronous sampling system for providing electric energy parameter analysis

Technical Field

The utility model belongs to the technical field of electric energy parameter analysis, and particularly relates to a synchronous sampling system for providing electric energy parameter analysis.

Background

In the electric energy parameter analysis, the problems of electric parameter fundamental wave frequency, harmonic wave and inter-harmonic wave analysis are involved. In the process of collecting and analyzing electric energy parameters, the input grid parameter frequency needs to be tracked, and the sampling rate of a sampler ad (analog to digital) device needs to be set. The AD sampling rate is typically provided by a dedicated clock generator on the pcb (printed Circuit board). Since the power frequency of the prior art does not exceed 400Hz (e.g., at an airport power supply), some motor devices require the inverter to output ac power at a frequency of up to 500Hz or more, or 30 Hz. Therefore, synchronous sampling in a frequency range of 30 Hz-500 Hz or even more is required for measuring the harmonic wave or the inter-harmonic wave of the electric energy parameter.

The synchronous sampling of the electric energy parameters means that the fundamental wave tracking is carried out on the input electric energy, then the frequency multiplication is carried out according to the fundamental wave, and then the clock after the frequency multiplication is input into an AD device to carry out the synchronous sampling of the fundamental wave time window. As people always only aim at the common power frequency such as 50Hz power grid (Europe and China), 60Hz power grid (North America region) and 400Hz (aviation equipment) for tracking and time window synchronous sampling. However, due to the environmental protection requirement of modern technology, the use of ac power is increasing, so that various motors and frequency converters are also widely used and developed.

The prior power grid frequency tracking and time window synchronous sampling technology has the problems that the tracking technology is general, but the time window synchronous technology is poor, even some instruments are not used for real synchronous sampling, only a plurality of points are randomly sampled, and then harmonic waves and inter-harmonic waves are calculated.

Common fundamental frequency tracking technologies include FFT + FT spectrum refinement technology combined with phase-locked loop methods, including digital phase-locked loop frequency multiplication methods and analog phase-locked loop methods. The conventional analog phase-locked loop method is too expensive, occupies too much PCB and is too difficult to debug. The digital phase-locked loop frequency multiplication method cannot achieve true approximation, and belongs to a fractional frequency division-like mode, so that accurate frequency output cannot be achieved when the frequency reaches dozens of MHz. Besides, fractional division is an approximation method, and is limited to the influence of the maximum operating frequency of a digital device of hundreds of MHz, which causes the sampling clock to have a jitter of ns level, and the accuracy of this method cannot meet the requirement of accurate measurement. In addition, in order to meet the above requirements, a dedicated clock generator is required, but the clock generator consumes much power and is expensive.

SUMMERY OF THE UTILITY MODEL

Aiming at the problems of poor time window synchronous sampling effect, low precision, large power consumption, high cost and the like in the power grid frequency tracking and time window synchronous sampling technology in the prior art, the utility model provides a synchronous sampling system for providing electric energy parameter analysis. The signal output by the DDS is provided for the ADC after being shaped to be used as sampling control, high-precision synchronous sampling is realized through the first time synchronous driving unit and the second time synchronous driving unit, and compared with an analog phase-locked loop technology, the digital phase-locked loop frequency multiplication method is lower in cost, simpler in debugging and higher in precision.

The novel concrete implementation content of this experiment is as follows:

the utility model provides a synchronous sampling system for providing electric energy parameter analysis, which is connected with a plurality of paths of electric parameter conditioning channels and a power grid voltage conditioning channel and is used for receiving a power grid signal and carrying out frequency measurement so as to realize frequency doubling sampling on the received power grid signal under the condition of time window alignment, wherein the synchronous sampling system comprises an FPGA unit, a plurality of paths of synchronous sampling ADC units, a fundamental wave capturing ADC unit, a DDS frequency synthesizer and a synchronous time window system;

the input end of the multi-path synchronous sampling ADC unit is connected with a plurality of paths of electric parameter conditioning channels, and the plurality of paths of electric parameter conditioning channels comprise a plurality of paths of power grid voltage parameter channels and a plurality of paths of power grid current parameter channels; the output end of the multi-path synchronous sampling ADC unit is connected with the FPGA unit;

a DDS control configuration port is arranged on the FPGA and is connected with the DDS frequency synthesizer through the DDS control configuration port;

the output end of the DDS frequency synthesizer is connected with the multi-path synchronous sampling ADC unit;

the synchronous time window system comprises a first time synchronous driving unit and a second time synchronous driving unit which are lapped on a DDS frequency synthesizer, the DDS frequency synthesizer is connected with the multi-path synchronous sampling ADC unit through the first synchronous driving unit, and is connected with the FPGA unit through the second synchronous driving unit;

the FPGA unit is internally provided with an FFT and FT frequency measurement module, the input end of the fundamental wave capturing ADC is connected with a power grid voltage conditioning channel, and the output end of the fundamental wave capturing ADC is connected with the FFT and FT frequency measurement module of the FPGA unit.

In order to better implement the present invention, the present invention further includes a DDS clock output and termination matching buffer unit, wherein the DDS clock output and termination matching buffer unit is connected between the output end of the DDS frequency synthesizer and the multi-channel synchronous sampling ADC unit.

In order to better realize the utility model, the digital television receiver further comprises a power supply unit, wherein the power supply unit comprises a common-mode inductance module, the input end of the common-mode inductance module is connected with a 12V power supply, and the output end of the common-mode inductance module is connected with an FPGA unit, a multi-path synchronous sampling ADC unit, a fundamental wave capturing ADC unit, a DDS frequency synthesizer, a DDS clock output and termination matching buffer unit. In electronic devices, a common mode inductor module is commonly used for filtering power supply noise.

In order to better implement the utility model, further, the fundamental wave capturing ADC unit includes a voltage follower TLV2462LD, and the input end 3 of the voltage follower TLV2462LD is connected to the UA _ BW signal of the grid voltage conditioning channel; the No. 1 output end of the voltage follower TLV2462LD is also connected with the No. 2 input end;

the fundamental wave capturing ADC unit further comprises a fundamental wave capturing ADC chip, the fundamental wave capturing ADC chip adopts an AD7476ARTZ chip, and the No. 1 output end of the voltage follower TLV2462LD is also connected with the No. 3 VIN input end of the fundamental wave capturing ADC chip;

the fundamental wave capturing ADC unit is further provided with a driving chip TXB0102DCUR, the No. 5 SDATA terminal of the fundamental wave capturing ADC chip is connected with the No. 8B 1 terminal of the driving chip TXB0102DCUR, the No. 5S _ DATA terminal of the driving chip TXB0102DCUR is connected with the FFT + FT frequency measurement module of the FPGA unit, and the FFT + FT frequency measurement module is a tracking and evaluation module designed in the FPGA chip.

To better implement the present invention, further, the fundamental capture ADC unit further includes an LTC1067lGN chip and a comparator LM 2930D; the No. 8 INVA terminal of the LTC1067lGN chip is connected with a UA _ BW signal, the No. 11 BPB terminal is connected with the No. 5 input end of the voltage follower TLV2462LD, the No. 7 output end of the voltage follower TLV2462LD is connected with the No. 3 input end of a comparator LM2903D, and the No. 1 output end of the comparator LM2903D outputs a UA _ F signal.

In order to better realize the utility model, the FPGA unit adopts an FPGA XC6SLX45-2CSG3241 chip.

IN order to better implement the present invention, the DDS frequency synthesizer uses an AD9832 chip to form a DDS frequency synthesis circuit, the DDS clock output and terminal matching buffer unit uses a comparator LTC6752, a transistor Q1 BCR503 is connected outside the IOUT terminal No. 14 of the AD9832 chip, the emitter of the transistor Q1 BCR503 is connected to the + IN terminal No. 2 of the comparator LTC6752, and the IOUT terminal No. 14 of the AD9832 chip is also connected to the IN terminal No. 3 of the comparator LTC 6752; the No. 7Q terminal of the comparator LTC6752 is connected with the multi-path synchronous sampling ADC unit.

In order to better implement the utility model, further, the multi-path synchronous sampling ADC unit adopts an AD7761BSTZ chip, and

terminals

64, 63, 2, 1, 8, 7, 10, and 9 of the AD7761BSTZ chip are respectively connected to a power grid voltage parameter channel; no. 49, No. 50, No. 47, No. 48, No. 41, No. 42, No. 39 and No. 40 of the AD7761BSTZ chip are respectively connected with one power grid current parameter channel; the terminal No. 32 of the AD7761BSTZ chip is connected with the terminal No. 7Q of the comparator LTC 6752.

In order to better implement the present invention, the first time synchronization driving unit and the second time synchronization driving unit both use an SN74LVC16245DGGR driver, and

terminals

37, 38, 40, 41, 43, 44, 46, and 47 of the first time synchronization driving unit are respectively connected to terminals 20 to 27 of the AD7761BSTZ chip; the terminals No. 2, No. 3, No. 5, No. 6, No. 8, No. 9, No. 11 and No. 12 of the first time synchronization driving unit are respectively connected with the terminals No. T18, No. T17, No. P17, No. P18, No. U17, No. U18, No. N17 and No. N18 of the FPGA XC6SLX45-2CSG3241 chip of the FPGA unit;

no. 27, No. 29, No. 30, No. 32, No. 33, No. 35 and No. 36 terminals of the second time synchronization driving unit are respectively connected with the No. 4 terminal of the comparator LTC6752 and the No. 8, No. 7, No. 9 and No. 10-12 terminals of the AD9832 chip.

In order to better implement the utility model, further, the common-mode inductance module comprises a filter H1205S-2W and a linear power supply LM117IMP-ADJ/NOPE which are connected in sequence, and further comprises a filter MIDR03-12S 05M; the output end of the linear power supply LM117IMP-ADJ/NOPE and the filter MIDR03-12S05M is connected with the FPGA unit, the multi-path synchronous sampling ADC unit, the fundamental wave capturing ADC unit, the DDS frequency synthesizer, the DDS clock output and the termination matching buffer unit.

Compared with the prior art, the utility model has the following advantages and beneficial effects:

the utility model is realized by adopting a logic device FPGA, and the frequency can obtain the fundamental wave frequency of the measured power grid within a few ms. And the frequency value can be immediately transmitted to a frequency generation device outside the FPGA, a DDS is selected as a frequency generator, the DDS can support a frequency from several KHz to tens of MHz, the frequency interval can reach MCLK/(16777216), and even some devices reach MCLK/(4294967296) precision. And the whole reaction time can be completed within tens of ms, so the method can effectively solve the difficulty of clock synthesis in the prior time window synchronous sampling technology. In addition, the DDS is used as a frequency generator and is combined with the FFT + FT frequency spectrum refining technology, the frequency value is immediately transmitted to a frequency generating device outside the FPGA through the DDS, high-precision synchronous sampling is realized through the first time synchronous driving unit and the second time synchronous driving unit, and compared with an analog phase-locked loop technology, the digital phase-locked loop frequency multiplication method is lower in cost, simpler in debugging and higher in precision.

Drawings

FIG. 1 is a block diagram of the modules of the present invention;

FIG. 2 is a schematic circuit diagram of a first portion of the power supply unit of the present invention;

FIG. 3 is a schematic circuit diagram of a second portion of the power supply unit of the present invention;

FIG. 4 is a schematic diagram of a first circuit portion of a fundamental capture ADC unit according to the present invention;

FIG. 5 is a schematic diagram of a second circuit portion of a fundamental capture ADC unit according to the present invention;

FIG. 6 is a schematic diagram of a multi-channel synchronous sampling ADC unit circuit according to the present invention;

FIG. 7 shows a first time-synchronous driving unit according to the present invention

FIG. 8 is a schematic circuit diagram of a second time-synchronized driving unit;

FIG. 9 is a schematic diagram of a DDS frequency synthesizer circuit;

FIG. 10 is a schematic diagram of a reference current source cell circuit;

fig. 11 is a schematic circuit diagram of a plurality of power grid voltage parameter channels and a plurality of power grid current parameter channels connected to the plurality of synchronous sampling ADC units of fig. 6;

FIG. 12 is a schematic circuit diagram of a first portion of an FPGA cell chip;

FIG. 13 is a schematic circuit diagram of the second part of the FPGA unit chip.

Detailed Description

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and therefore should not be considered as a limitation to the scope of protection. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Example 1:

the embodiment provides a synchronous sampling system for providing electric energy parameter analysis, which is connected with a plurality of paths of electric parameter conditioning channels and a power grid voltage conditioning channel and is used for receiving a power grid signal and performing frequency measurement so as to realize frequency doubling sampling on the received power grid signal under the condition of time window alignment, and as shown in fig. 1, the synchronous sampling system comprises an FPGA unit, a plurality of paths of synchronous sampling ADC units, a fundamental wave capturing ADC unit, a DDS frequency synthesizer and a synchronous time window system;

In order to better realize the utility model, the digital television receiver further comprises a power supply unit, wherein the power supply unit comprises a common-mode inductance module, the input end of the common-mode inductance module is connected with a 12V power supply, and the output end of the common-mode inductance module is connected with an FPGA unit, a multi-path synchronous sampling ADC unit, a fundamental wave capturing ADC unit, a DDS frequency synthesizer, a DDS clock output and termination matching buffer unit.

The working principle is as follows: the fundamental wave frequency of the power grid parameters transmitted by the fundamental wave capturing ADC is measured through the FFT + FT frequency measurement module in a fast enough response mode, then the frequency control value is transmitted to the DDS frequency synthesizer, the DDS frequency synthesizer outputs the required clock frequency, the clock frequency reaches the multi-channel synchronous sampling ADC unit after being carefully buffered by the DDS clock output and end connection matching buffer unit, and sampling of the accurate synchronous time window is achieved.

The multi-path synchronous sampling ADC unit is a target device for realizing power grid parameter acquisition and implementing synchronous time window sampling;

the fundamental wave capturing ADC unit is used as a part of an FFT + FT frequency measurement realization device, and data obtained by sampling according to an FFT + FT algorithm is transmitted to an FPGA for operation to obtain an accurate fundamental wave period of a measured power grid;

the digital device realizes the transportation of FFT + FT. The time series obtained by ordinary precision sampling is processed by FFT to obtain rough frequency distribution information. The digital device can be selected from an FPGA (field programmable gate array), the FPGA can provide an FFT IP core for operation, the output of the FFT IP core is a production line, the maximum value of the frequency spectrum sequence can be obtained by using a production line processing mode, then the frequency spectrum thinning window is transmitted to a soft core such as Microblaze in the FPGA, even a special frequency spectrum thinning fitting operation logic, and the maximum value is calculated and then the lower frequency value is recorded; the frequency value obtained by FFT + FT operation is mapped to a frequency control word register of the DDS through normalization operation, for example, a sampling clock and a frequency control word of the DDS have certain frequency precision which can be MCLK/(16777216) or even MCLK/(4294967296), and the MCLK can be switched by the clock to achieve extremely high precision which is usually below 0.1Hz or even 0.001 Hz. The fundamental wave period is generally between 30Hz and 500Hz, and the fundamental wave period is normalized into a DDS control word after being multiplied by 512 times. The digital device processes the control word and writes the control word into an internal register of the DDS device through an interface between the digital device and the DDS device, usually a serial SPI interface, and the control word is validated.

Note that: the output of the DDS frequency synthesizer may require a termination resistor to convert the current signal into a voltage signal. A double-to-single ended driver may be required. The driver can match different logic levels and input the logic levels to a multi-path synchronous sampling ADC unit as a sampling clock, namely, the logic level of the clock required by a specific ADC is adapted.

Example 2:

in this embodiment, based on the above embodiment 1, as shown in fig. 2, fig. 3, fig. 4, fig. 5, fig. 6, fig. 7, fig. 8, fig. 9, fig. 10, fig. 11, fig. 12, and fig. 13, to better implement the present invention, further, the fundamental wave capturing ADC unit includes a voltage follower TLV2462LD, where the No. 3 input terminal of the voltage follower TLV2462LD is connected to the UA _ BW signal of the grid voltage conditioning channel; the No. 1 output end of the voltage follower TLV2462LD is also connected with the No. 2 input end;

the fundamental wave capturing ADC unit is further provided with a driving chip TXB0102DCUR, the No. 5 SDATA terminal of the fundamental wave capturing ADC chip is connected with the No. 8B 1 terminal of the driving chip TXB0102DCUR, and the No. 5S _ DATA terminal of the driving chip TXB0102DCUR is connected with the FFT + FT frequency measurement module of the FPGA unit.

terminals

Fig. 10 is a reference current source unit circuit, and the effects of ultra-low noise, high precision, and low temperature drift performance can be achieved by adding the reference current source unit circuit.

The working principle is as follows: the implementation of the utility model comprises a total of three parts: (1) the fundamental wave capturing ADC unit and the FFT + FT frequency measurement module form an FFT + FT frequency measurement front end; (2) an FPGA processing control part composed of an FPGA; (3) the synchronous system is composed of a multi-channel synchronous sampling ADC unit, a first time synchronous driving unit and a second time synchronous driving unit of a DDS frequency synthesizer;

for the first part: the signal UA _ BW of the circuit which converts the power signal safely and information to low voltage and low distortion without loss is impedance-converted by the voltage follower in fig. 2 and 3. The voltage follower consists of TLV2462ID, driving ADC AD 7476. The AD7476 works at a sampling rate of 5K, and the acquired data is transmitted to the FPGA xc6slx45 device through a driving chip TXB0102DCUR through a serial spi interface.

The xc6slx45 device synthesizes 12bit data by serial-to-parallel conversion of the acquired AD7476 serial data and 2048 pointsAnd sending a frame to an FFT core for operation. And the operation result finds an extreme value through one-dimensional extreme value search, and two digits before and after the extreme value index number are sent to the sine interpolation operation unit. The sine interpolation operation unit performs operation at 0.01 per step, and a unimodal extreme value array of 201 extreme points is fitted. The array has a spectral resolution of

The 0.03Hz frequency resolution can be obtained by combining the time consumption of the measured algorithm and the actually required frequency measurement precision. If higher frequency resolution is pursued, finer fitting can be performed under the condition of ensuring a certain ADC sampling rate, and more precise frequency measurement and faster frequency tracking can be obtained by adopting a special fitting unit.

The frequency values calculated in the FPGA are normalized to 32-bit frequency resolution. For example, the actual fundamental frequency of the power is 339.755Hz at present, then FFT + FT can obtain a 2048-point FFT index of 140 according to the above setting. The frequency obtained by taking 139, 140 and 141 points and carrying out 100 times of interpolation is 339.758 or 339.752. The MCLK of the DDS can be obtained without grading, and a more accurate measurement mode can be obtained if grading is adopted. If the MCLK of the DDS is 5MHz, then a frequency resolution of

Hz, then the frequency control words here should be either 199858 or 199854. Here, the control value of DDS multiplies these two values by 512 multiplication coefficients 102327296 and 102325248, respectively, and both are written into the FREG0 register and the FREG1 register of DDS AD9832, respectively. Both registers can control the frequency output of the DDS, where setting two frequency control words can be used to achieve error cancellation.

Error cancellation can be performed subsequently with higher accuracy FFT + FT or using a high accuracy frequency measurement circuit, theoretically there is no other way to cancel the error than using an analog PLL tracking input to always perform error cancellation, but there is no suitable PLL for tracking frequencies from 30Hz to 500 Hz. Good results are obtained when the frequency precision reaches 0.001Hz due to test tests, and no accumulated error is shown. The method provides a method for performing operation in a digital device by adopting subsequent FFT + FT with higher precision, for example, performing 1000-time or 5000-time interpolation on the prior FFT + FT, and then directly writing the value into an FREG0 register to control DDS to be output by the frequency control word.

The output of the DDS is connected to a digital BJT base level, waveform shaping is carried out through a comparator LTC6752-2, and then the waveform shaped data is provided for AD7761 to be subjected to sampling control, sampled data is input to an FPGA pin through a driver 16T245 in a source synchronization mode, and the sampled data is transmitted to analysis in a frame length of ten 512 points after serial-to-parallel conversion is carried out by the FPGA.

Other parts of this embodiment are the same as those of embodiment 1, and thus are not described again.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and all simple modifications and equivalent variations of the above embodiments according to the technical spirit of the present invention are included in the scope of the present invention.

Claims

1. A synchronous sampling system for providing electric energy parameter analysis is connected with a plurality of paths of electric parameter conditioning channels and a power grid voltage conditioning channel and is used for receiving a power grid signal and carrying out frequency measurement so as to realize frequency doubling sampling on the received power grid signal under the condition of time window alignment, and the synchronous sampling system is characterized by comprising an FPGA unit, a plurality of paths of synchronous sampling ADC units, a fundamental wave capturing ADC unit, a DDS frequency synthesizer and a synchronous time window system;

2. The synchronous sampling system for providing electrical energy parameter analysis of claim 1, further comprising a DDS clock output and termination matching buffer unit coupled between the DDS frequency synthesizer output and a multi-channel synchronous sampling ADC unit.

3. The synchronous sampling system for providing electric energy parameter analysis according to claim 2, further comprising a power supply unit, wherein the power supply unit comprises a common mode inductance module, an input end of the common mode inductance module is connected with a 12V power supply, and an output end of the common mode inductance module is connected with the FPGA unit, the multi-path synchronous sampling ADC unit, the fundamental wave capturing ADC unit, the DDS frequency synthesizer, the DDS clock output and the termination matching buffer unit.

4. The synchronous sampling system for providing power parameter analysis of claim 3, wherein the fundamental capture ADC unit comprises a voltage follower TLV2462LD, wherein the No. 3 input terminal of the voltage follower TLV2462LD is connected to the UA _ BW signal of the grid voltage conditioning channel; the No. 1 output end of the voltage follower TLV2462LD is also connected with the No. 2 input end;

5. The synchronous sampling system for providing electrical energy parameter analysis according to claim 4, wherein the fundamental capture ADC unit further comprises an LTC1067lGN chip and a comparator LM 2930D; the No. 8 INVA terminal of the LTC1067lGN chip is connected with a UA _ BW signal, the No. 11 BPB terminal is connected with the No. 5 input end of the voltage follower TLV2462LD, the No. 7 output end of the voltage follower TLV2462LD is connected with the No. 3 input end of a comparator LM2903D, and the No. 1 output end of the comparator LM2903D outputs a UA _ F signal.

6. The synchronous sampling system for providing power parameter analysis according to claim 5, wherein the FPGA unit employs an FPGA XC6SLX45-2CSG3241 chip.

7. The synchronous sampling system for providing power parameter analysis of claim 6, wherein the DDS frequency synthesizer employs an AD9832 chip to form a DDS frequency synthesizing circuit, the DDS clock output and terminal matching buffer unit employs a comparator LTC6752, a transistor Q1 BCR503 is connected outside the IOUT 14 terminal of the AD9832 chip, the emitter of the transistor Q1 BCR503 is connected to the + IN 2 terminal of the comparator LTC6752, and the IOUT 14 terminal of the AD9832 chip is further connected to the IN 3 terminal of the comparator LTC 6752; the No. 7Q terminal of the comparator LTC6752 is connected with the multi-path synchronous sampling ADC unit.

8. The synchronous sampling system for providing electric energy parameter analysis according to claim 7, wherein the multi-channel synchronous sampling ADC unit adopts an AD7761BSTZ chip, and terminals 64, 63, 2, 1, 8, 7, 10 and 9 of the AD7761BSTZ chip are respectively connected with a power grid voltage parameter channel; no. 49, No. 50, No. 47, No. 48, No. 41, No. 42, No. 39 and No. 40 of the AD7761BSTZ chip are respectively connected with one power grid current parameter channel; the terminal No. 32 of the AD7761BSTZ chip is connected with the terminal No. 7Q of the comparator LTC 6752.

9. The synchronous sampling system for providing the electric energy parameter analysis according to claim 8, wherein the first time synchronous driving unit and the second time synchronous driving unit both adopt SN74LVC16245DGGR drivers, and terminals No. 37, No. 38, No. 40, No. 41, No. 43, No. 44, No. 46 and No. 47 of the first time synchronous driving unit are respectively connected with terminals No. 20-27 of the AD7761BSTZ chip; the terminals No. 2, No. 3, No. 5, No. 6, No. 8, No. 9, No. 11 and No. 12 of the first time synchronization driving unit are respectively connected with the terminals No. T18, No. T17, No. P17, No. P18, No. U17, No. U18, No. N17 and No. N18 of the FPGA XC6SLX45-2CSG3241 chip of the FPGA unit;

10. The synchronous sampling system for providing power parameter analysis of claim 3, wherein the common mode inductance module comprises a filter H1205S-2W and a linear power supply LM117IMP-ADJ/NOPE connected in sequence, and further comprises a filter MIDR03-12S 05M; the output end of the linear power supply LM117IMP-ADJ/NOPE and the filter MIDR03-12S05M is connected with the FPGA unit, the multi-path synchronous sampling ADC unit, the fundamental wave capturing ADC unit, the DDS frequency synthesizer, the DDS clock output and the termination matching buffer unit.