CN202019349U

CN202019349U - Multipath parallel high-speed analog/digital (A/D) sampling circuit board based on low cost

Info

Publication number: CN202019349U
Application number: CN2010206675012U
Authority: CN
Inventors: 王伟权
Original assignee: Sichuan Jiuzhou Electric Group Co Ltd
Current assignee: Sichuan Jiuzhou Electric Group Co Ltd
Priority date: 2010-12-20
Filing date: 2010-12-20
Publication date: 2011-10-26
Anticipated expiration: 2020-12-20

Abstract

The utility model discloses a multipath parallel high-speed analog/digital (A/D) sampling circuit board based on low cost and comprises an analog signal input module, a clock generation and distribution module, a parallel analog-to-digital converter (ADC) module, a field programmable gate array (FPGA) module and a digital signal processor (DSP), wherein the analog signal input module mainly realizes input of an analog signal; and the clock generation and distribution module mainly provides a uniform clock reference for the parallel ADC module. By the multipath parallel high-speed A/D sampling circuit board based on low cost, the high-speed A/D sampling can be realized with low cost, so the hardware development cost is reduced and the A/D sampling circuit meets the development idea of the conventional software defined radio.

Description

A/D sample circuit plate based on low-cost multidiameter delay two-forty

Technical field

The utility model relate to a kind of can widely used Digital Signal Processing, this technology relates generally to the high-speed data acquisition aspect.

Background technology

Based on Modern Communication Theory, with the Digital Signal Processing is core, with microelectric technique is that the software and radio technique that supports has been obtained very big development in recent years, has caused the huge concern and the extensive interest of electronic applications such as comprising military communication, personal mobile communication, microelectronics and computer.But,, almost be impossible from the radiofrequency signal Direct Digitalization owing to be subjected to the restriction of semiconductor technology.And the required A/D that quantizes of intermediate-freuqncy signal, and the required devices such as FPGA, DSP of follow-up digital medium-frequency signal processing, satisfied the requirement of software radio to a certain extent.

Along with the development of Digital Signal Processing in recent years, many theories, sampling, signal multiphase filtering etc. are increasingly mature such as owing, and all are if digitization, even the digitized processing of Wideband Intermediate Frequency signal provides the basis of realizing.

Therefore, at lower cost intermediate-freuqncy signal being carried out the parallel high-speed Digital Signal Processing is the important channel of realizing software radio.

In classical signal was handled, the multidiameter delay sampled-data system certainly existed difference at each interchannel, thereby can introduce new error, made overall performance descend.Source of error is because the clock of required precision is difficult to accomplish under present technical conditions, and the time delay between each road does not wait and having caused sampling to be actually nonuniform sampling, thereby causes that sampled point is offset; Another source is that the interchannel gain is inconsistent.Be difficult to compound undistortedly after these errors make input signal by the multi-channel parallel systematic sampling.But these two kinds of errors are all only relevant with the sampling device with circuit structure, belong to systematic error, can pass through error measure after sampling system constitutes, and adopt software mode to revise.

Summary of the invention

The technical scheme that its technical problem that solves the utility model adopts is: a kind of A/D sample circuit plate based on low-cost multidiameter delay two-forty comprises analog signal input circuit, clock generating and distribution module, ADC module, FPGA module and DSP module; Described analog module mainly realizes the input to analog signal, to drive the ADC module; Clock generating and distribution module provide same clock reference for the ADC module; FPGA module and DSP module are mainly used in carries out sampling correcting and verification the verifying results with the digital signal of handling back formation through high-speed sampling.

According to analyzing in the past, these high-speed data Sampling techniques are carried out specific design from soft, hard both direction and are realized:

1. hardware aspect

L adopts more accurate clock chip and divides distribution chip;

L clock, input analog signal etc. want strict isometric at the printed circuit board upward wiring;

L provides accurate same reference voltage to each A/D chip, and uses same power supply chip.

Be checking relevant design validity, this programme has designed interlock circuit figure, and concrete principle is referring to Fig. 1, this shows that hardware module is divided into 5 parts, is respectively: analog signal input module, clock generating and distribution module, Parallel ADC module, FPGA module and DSP module.We are referred to as collecting part wherein preceding 3 modules, and we are referred to as the inventory analysis part latter two part.

A) analog signal input module

Adopt a broadband difference amplifier AD8351 to form, the major function that it is finished is that analog input signal is carried out the single-ended transfer difference operation to drive ADC, to obtain best sample effect.

B) clock generating and distribution module

This module mainly is made up of an ADF4360-7 and an AD9510, and wherein ADF4360-7 is responsible for producing the equivalent sampling clock, and AD9510 is responsible for this clock 4 frequency divisions and 4 road LVPECL signals of exporting phase shift successively 90 degree are driven 4 ADC respectively.

C) ADC module

Adopt 4 AD9480 to carry out parallel sampling, strict guarantee clock line and analog signal incoming line are isometric to the distance of every ADC when PCB makes a plate, and adopt the unified reference voltage source of ADR510 as amplifier and 4 ADC.

D) FPGA module

Select the XC3S400PQ208-4 of XLINX company to receive the clock and the data of the LVDS level of AD9480 output, and left in the internal RAM coexistence 32KBytes (being equivalent to every road 8KBytes) in.Back notice DSP reads in check and the error correction (present stage is realized algorithm for error correction earlier in DSP, understand decomposition algorithm later on and real-time implementation in FPGA) that data are carried out sample effect.

E) DSP module

Select TMS320VC5509A to carry out the checking of sample effect and the error correction work at initial stage, DSP communicates by letter with FPGA by the EMIF interface, and sense data is also handled from the inner FIFO that realizes of FPGA.

2. software aspect

In the high-speed data acquisition process, it is relatively complicated that error is introduced process, just does theory analysis herein no longer at this point.But its main error mainly is summed up as three classes:

A) the non-homogeneous introducing error of A/D biasing amplitude

The biased error of A/D is to produce the additional frequency component identical with the A/D number to the influence of system, the additional frequency component is positioned on the fixed frequency point relevant with the A/D number with sample frequency, and equally spaced be distributed on the frequency axis frequency-independent of its position and input signal.

B) the non-homogeneous introducing error of A/D gain range

If the sampling angular frequency s=2 π/T of system.Comprise M to spectral line in a frequency period, M is the parallel port number that adopts.The main spectral line of signal is positioned at that (ω 0 so, ω s-ω 0) locates, additional frequency component spectral line is equally spaced to be distributed on the frequency axis, frequency interval is ω s/M, and the center of every pair of spectral line uniformly-spaced evenly distributes with ω s/M, the coefficient of every pair of spectral line be A (k)/2j and-A (M-k)/2j, and A (k)=A (M-k), A (k) is the non-homogeneous introducing error of gain range.

C) time delay error

Periodic signal produces a series of additional spectral lines after nonuniform sampling, adjacent spectral line is spaced apart f on frequency axis _s/ M.

f _sBe sample frequency, M is the parallel port number that adopts.

Comprehensive above the analysis, the software correcting mode is as follows:

The rectification of time delay error:

According to the time shifting property of Fourier transform, time error Δ t _kWith sampling period T _sRatio be a _k, then Dui Ying frequency domain is changed to frequency domain value and multiply by Allow sampled signal be by ideal frequency response All-pass filter can realize correction to time error, select suitable window function can obtain the practical filter coefficient, reference model is seen Fig. 2.

The rectification of biased error:

In order to eliminate the biased error between ADC, we deduct its intrinsic direct current biasing o after allowing every road ADC sample _k, promptly allow the direct current biasing of 4 road ADC all become 0, so just eliminated the influence of biasing to sampling.

The rectification of gain error:

In order to eliminate the gain error between ADC, the amplitude that then will back three road signals all multiply by with first via signal compares g _k, so just back three road signals all are consistent with the gain of first via signal.Thereby eliminate interchannel gain error.

Description of drawings

Below in conjunction with drawings and Examples the utility model is further specified.

Fig. 1 is circuit theory diagrams of the present utility model.

Fig. 2 is the all-pass filter structures block diagram that multinomial approaches.

Fig. 3 is parallel sampling data time domain and spectrum amplitude figure (wherein being high order harmonic component shown in the circle).

Fig. 4 is image data time domain and spectrum amplitude figure.

Embodiment

Below in conjunction with accompanying drawing, the utility model is done detailed explanation.

In order to make the purpose of this utility model, technical scheme and advantage clearer,, the utility model is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.

This high-speed data Sampling techniques are carried out specific design from soft, hard both direction and are realized:

L adopts more accurate clock chip and divides distribution chip;

The above only is preferred embodiment of the present utility model; not in order to restriction the utility model; all any modifications of within spirit of the present utility model and principle, being done, be equal to and replace and improvement etc., all should be included within the protection range of the present utility model.

Claims

1. A/D sample circuit plate based on low-cost multidiameter delay two-forty, it is characterized in that: this circuit board comprises analog signal input circuit, clock generating and distribution module, ADC module, FPGA module and DSP module; Described analog module mainly realizes the input to analog signal, to drive the ADC module; Clock generating and distribution module provide same clock reference for the ADC module; FPGA module and DSP module are used for the digital signal of handling back formation through high-speed sampling is carried out sampling correcting and verification the verifying results.

2. the A/D sample circuit plate based on low-cost multidiameter delay two-forty according to claim 1 is characterized in that: clock and data that described FPGA module receives the LVDS level of ADC module output leave in the internal RAM; The FIFO of described FPGA inside is only with being operated under the 125MHz.

3. the A/D sample circuit plate based on low-cost multidiameter delay two-forty according to claim 1 is characterized in that: described DSP module, select chip TMS320VC5509A for use, and be used for the checking of sample effect and the error correction work at initial stage.